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Random number generator (RNG) is largely used to supply the initial computation stage for many digital systems, noise generation in DSP, and cryptographic applications. As for cryptographic applications, RNGs should be efficiently implemented to ensure maximum unpredictability with minimum Area-Time trade off. In this paper, we are implementing fas...
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... is a simple RNG that is built of D-Flip-flops and XOR gates where each D-Flip-flop uses asynchronous reset that is independent of clock. The major feature of N-bit LFSR [6] is that each generated random number will repeat itself after 2í µí±í µí± − 1 clock cycles. A standard binary polynomial function (counter) for í µí±í µí± = 8: { X 8 + X 7 + X 6 + X 4 + X 2 + 1 } is used to generate random numbers. LFSR is easy to implement in hardware as multiple LFSR's are often combined to achieve better security. Fig. 1 shows the typical design example of N-bit LFSR (7-stages). ...
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... LFSR [6] is that each generated random number will repeat itself after 2í µí±í µí± − 1 clock cycles. A standard binary polynomial function (counter) for í µí±í µí± = 8: { X 8 + X 7 + X 6 + X 4 + X 2 + 1 } is used to generate random numbers. LFSR is easy to implement in hardware as multiple LFSR's are often combined to achieve better security. Fig. 1 shows the typical design example of N-bit LFSR (7-stages). ...
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Field programmable system-on-chip (FPSoC) devices, combining high-performance processors and FPGA fabric in the same chip, are currently a leading technology in the design of complex digital systems. Since design times are longer than those of systems based on graphic processing units or standalone processors, many efforts are being devoted to deve...
Citations
... In general, RNGs can be classified into two types, namely, pseudo-random number generators (PRNGs) and true random number generators (TRNGs) [6][7][8]. However, because of the merits of TRNGs in terms of unpredictability, they have been preferred over PRNG in many more cases including, but not restricted to, cryptographic key generation, nonce generation, one-time pads, random simulations, gaming, test pattern generators and device authentication [9,10]. ...
True random key generator (TRNG) architectures play a notable role in strengthening information security infrastructure. The development of new entropy sources based on reconfigurable hardware is always in demand, especially for the integrity of devices in IoT applications. TRNGs can be adopted for generating unique device IDs that form the data network in the IoT. A ring oscillator (RO) is an efficient entropy source which can be implemented on FPGAs or realised as ASIC hardware. This work proposes a non-identical RO array as an entropy source. The TRNG architecture, based on an increasing odd number of inverters per ring, was extensively studied. The various statistical and hardware analyses provided encouraging results for this reliable entropy unit. The suggested device-independent non-identical RO structure was implemented on five different types of FPGA hardware belonging to the Xilinx and Intel families, consuming 13 registers and nearly 15 combinational functions. This TRNG achieved a throughput of 3.5 Mbps. While the emergence of the Gaussian response evaluated true randomness, the NIST 800-90B and NIST 800-22 tests yielded good results in terms of the justification of randomness evolving from the proposed TRNG architecture.
... Nevertheless, the non-linear feedback shift register (NLFSR) is more resistant to several types of attacks. Trivium [20] is considered an NLFSR and is used in the proposed model to provide more resistance to such attacks. ...
Privacy-preserving of medical information (such as medical records and images) is an essential right for patients to ensure security against undesired access parties. This right is typically protected by law through firm regulations set by healthcare authorities. However, sensitive-private data usually requires the application of further security and privacy mechanisms such as encipherment (encryption) techniques. ’Medical images’ is one such example of highly demanding security and privacy standards. This is due to the quality and nature of the information carried among these images, which are usually sensitive-private information with few features and tonal variety. Hence, several state-of-the-art encryption mechanisms for medical images have been proposed and developed; however, only a few were efficient and promising. This paper presents a hybrid crypto-algorithm, MID-Crypt, to secure the medical image communicated between medical laboratories and doctors’ accounts. MID-Crypt is designed to efficiently hide medical image features and provide high-security standards. Specifically, MID-Crypt uses a mix of Elliptic-curve Diffie–Hellman (ECDH) for image masking and Advanced Encryption Standard (AES) with updatable keys for image encryption. Besides, a key management module is used to organize the public and private keys, the patient’s digital signature provides authenticity, and integrity is guaranteed by using the Merkle tree. Also, we evaluated our proposed algorithm in terms of several performance indicators including, peak signal-to-noise ratio (PSNR) analysis, correlation analysis, entropy analysis, histogram analysis, and timing analysis. Consequently, our empirical results revealed the superiority of MID-Crypt scoring the best performance values for PSNR, correlation, entropy, and encryption overhead. Finally, we compared the security measures for the MID-Crypt algorithm with other studies, the comparison revealed the distinguishable security against several common attacks such as side-channel attacks (SCA), differential attacks, man-in-the-middle attacks (MITM), and algebraic attacks.
... Some of the Primality testers are used to prove a number is prime where some are used to prove a compositeness. Thus, the prime number generation module consists of two stages of computations: generating the random number [14,15] and then test its primality. In order to generate a prime number, the random number generating stage should be followed by primality testing [8] phase to check whether the generated number is prime or not. ...
Due to the demand for large prime numbers to be used by many public key cryptographic systems such as RSA and SSC (Schmidt-Samoa cryptosystem), this led for the development of fast and reliable methods for primality testing to determine whether a given integer is prime or composite. Many algorithms were proposed by to address the efficient method of testing the primality of the integer number. In this paper, we propose a pipelined reconfigurable FPGA implementation for the primality testing coprocessor using Millar-Rabin method by employing the maximum possible parallelism of the internal operations. The proposed design targeted the \( {\text{ALTERA Cyclone }}\,{\text{IV FPGA}} \) (\( {\text{EP}}4{\text{CGX}}22{\text{CF}}19{\text{C}}7) \) along with \( {\text{Quartus II}} \) simulation package. The proposed design was evaluated in terms of the maximum operational frequency, the total path delay, the total design area and the total thermal power dissipation. The synthesized results revealed that the proposed parallel architecture implementation has recorded: critical path delay of \( 22.65 \,{\text{ns}} \), maximum operational frequency of \( 51.11\,{\text{MHz}} \), hardware design area (number of logic elements) of \( 6184\,{\text{LEs}} \), and total thermal power dissipation estimated as 151.30 mW. Consequently, the proposed PT architecture can be efficiently employed by many public key cryptographic mechanisms.
On-device intelligence and AI-powered edge devices require compressed deep learning algorithm and energy efficient hardware. Compute-in-memory (CIM) architecture is a more suitable candidate than traditional Complementary Metal-Oxide-Semiconductor (CMOS) technology for deep learning applications since computations are performed directly within the memory itself, reducing the need for data movement between memory and processing units. However, the current deep learning compression techniques are not designed to take advantage of CIM architecture. In this work, we proposed Twofold Sparsity, a joint bit- and network-level sparsity method to highly sparsify the deep leaning models by taking advantage of CIM architecture for energy-efficient computations. Twofold Sparsity method sparsify the network during training by adding two regularizations, one to sparsify the weights using Linear Feedback Shift Register (LFSR) mask, and the other one to sparsify the values in the bit-level by making bits zero. During inference, the same LFSRs is used to choose the correct sparsed weights for multiplication between input and weights and 2bit/cell RRAM based CIM is responsible to do the computation. Twofold Sparsity method achieved 1.3x to 4.35x energy efficiency in different sparsity rates compared to baselines and eventually enabling powerful deep learning models to be run on power constrained edge devices.
