A B C D E

1 1

Fortworth Banias 2

EAL20 LA-2462 Schematic

uFC-PGA Dothan / Montara-GM+
3
M11P-128M VRAM / ICH4-M 3

2004-08-12
REV: 0.1

4 4

Compal Electronics, Inc.

Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
EAL20 LA-2462 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 17, 2004 Sheet 1 of 47
A B C D E
 A B C D E

Compal Confidential
Fan Control Mobile Banias/Dothan
Model Name : EAL20 page 4
Thermal Sensor Clock Generator
File Name : LA-2462 Celeron-M ADI ADM1032AR Cypress CY28346ZCT-2
uFCPGA-478 CPU page 4,5
1
page 4 page 12 1

H_A#(3..31) P SB H_D#(0..63)
400MHz

LCD Conn.
page 20 Memory BUS(DDR) 200pin DDR-SO-DIMM X2
ATI M11-P Intel 855GME BANK 0, 1, 2, 3 page 10,11
2.5V DDR200/266/333
CRT Conn. BGA-708 Pin AGP4X/DVO uFCBGA-732
page 21
with 32/64/128MB 1.5V 266MHz page 6,7,8,9

TV-OUT Conn. On Board VRAM

page 13,14,15,16,17,18
page 21
Port 2,3
Hub-Link USB conn
TV Encoder x2 page 35
CH-7011A
2
page 19 2
Port 4
PCI BUS USB conn
3.3V 33 MHz
x1 page 35
IDSEL:AD16 IDSEL:AD18 IDSEL:AD17 IDSEL:AD20 USB 2.0
(PIRQE#, (PIRQ[G..H]#, (PIRQB#, (PIRQ[A..B]#, Intel ICH4-M
GNT#0, GNT#3/4, GNT#1, GNT#2, 3.3V 48MHz
REQ#0) REQ#3/4) REQ#1) REQ#2)
BGA-421 3.3V 24.576MHz AC-LINK
IEEE 1394a Mini PCI LAN CardBus 3.3V ATA-100
VIA VT6301S socket RTL8100CL ENE CB714/CB1410 page 22,23,24
page 27 page 30 page 26 page 28 IDE
CDROM AC97 Codec MDC Conn
Conn. page ALC250 Ver.C page 31
25 page 31
1394 Conn. RJ45/RJ11 5 in 1 Slot Slot 0
page 27 page 26 page 29 page 29
AMP EAL20 Sub Board
HDD Conn.
3
page 25
TPA0232
page 32 LED/SW Board 3
LPC BUS 3.3V 33MHz
Conn
SW DJ Ckt. Audio Board LS-2462 page 36
SMsC LPC47N217 C onn
page 25
ENE KB910 Super I/O T/P Board
RTC CKT. page 34 page 33 LS-2463 page 32 Conn
page 24
LS-2461 page 36

Power On/Off CKT. Touch Pad Int.KBD PARALLEL FIR

WL-KSW Board
page 36 page 33 page 33
page 37

LS-2464
DC/DC Interface CKT. 512KB BIOS
page 35

4
page 38 4

Power Circuit DC/DC

page 38,39,40,41 Compal Electronics, Inc.
42,43,44,45 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
D ate: Friday, September 17, 2004 Sheet 2 of 47
A B C D E
 A

Symbol note:
Voltage Rails
:means digital ground.
Power Plane Description S0-S1 S3 S5
:means analog ground.
VIN Adapter power supply (19V) N/A N/A N/A
B+ AC or battery power rail for power circuit N/A N/A N/A @ :means reserved.
+CPU_CORE Core voltage for CPU ON OFF OFF
+VCCP 1.05V rail for Processor I/O ON OFF OFF
Fortworth Banias Comparison Table
+1.25VS 1.25V switched power rail for DDR Vtt ON OFF OFF
+VGA_CORE 1.2V/1.0V switched power rail for VGA core power ON OFF OFF
Item * Descrite UMA Page
+1.35VS 1.35V switched power rail for GMCH core power ON OFF OFF
+1.5VALW 1.5V always on power rail ON ON ON*
VGA ATI M11P UMA 13 ~ 16
+1.5VS 1.5V switched power rail for AGP interface ON OFF OFF
+1.8VS 1.8V switched power rail for CPU PLL & Hub-Link ON OFF OFF VRAM 128MB/64MB N/A 13 ~ 14
+2.5V 2.5V power rail for system DDR ON ON OFF
TV Encoder N/A CH7011A 19
+2.5VS 2.5V power rail for VGA DDR ON OFF OFF
+3VALW
+3V 3.3V always on power rail ON ON ON*
+3V 3.3V switched power rail ON ON OFF
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
+5VS 5V switched power rail ON OFF OFF
+12VALW 12V always on power rail ON ON ON*
RTCVCC RTC power ON ON ON

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Board ID Table for AD channel
Vcc 3.3V +/- 5%
1 Ra 10K +/- 5% 1

ICH4-M I2C / SMBUS ADDRESSING BID/PID Rb/Rc V AD_BID min V AD_BID typ V AD_BID max
DEVICE HEX ADDRESS 0 0 0 V 0 V 0 V
1 8.2K +/- 5% 1.412 V 1.486 V 1.560 V
DDR SO-DIMM 0 A0 1010000X
2 18K +/- 5% 2.015 V 2.121 V 2.227 V
DDR SO-DIMM 1 A2 1010001X
3 33K +/- 5% 2.406 V 2.533 V 2.659 V
CLOCK GENERATOR (EXT.) D2 1101001X
4 56K +/- 5% 2.660 V 2.800 V 2.940 V
5 NC 3.135 V 3.300 V 3.465 V
KB910 I2C / SMBUS ADDRESSING
DEVICE HEX ADDRESS
SM1 24C16 A0H 1010000Xb
Board ID PCB Revision
SM1 SMART BATTERY 16H 0001011Xb
SM2 ADM0132 98H 1001100Xb * 0 0.1
CPU THERMAL MONITOR 1 0.2
SM2 ALC250 AUDIO CODEC 00H 0000000Xb 2 0.3
3 0.4
4 0.5
External PCI Devices 5
DEVICE PCI Device ID IDSEL # REQ/GNT # PIRQ 6
7
1394 D0 AD16 0 E
LAN D1 AD17 1 F
CARD BUS D4 AD20 2 A
5IN1 D4 AD20 2 B
Mini-PCI D2 AD18 3,4 G ,H
AGP BUS N /A AGP_DEVSEL# N /A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
Date: Friday, September 17, 2004 Sheet 3 of 47
A
 A B C D E

H_D#[ 0..63]
H_D#[0..63] <6>
U12A

H_A#[3..31] H_A#3 P4 A19 H_ D#0

<6> H_A#[3..31]
H_A#4
H_A#5
U4
A3#
A4#
Banias D0#
D1#
A25 H_ D#1
H_ D#2
+VCCP +VCCP
V3 A22
H_A#6 A5# D2# H_ D#3
R3 B21

2
H_A#7 A6# D3# H_ D#4
V2 A24
H_A#8 A7# D4# H_ D#5 R144 R147
W1 B26
H_A#9 A8# D5# H_ D#6
T4 A21 54.9_0402_1% 54.9_0402_1%
H_A#10 A9# D6# H_ D#7 @ @
W2 B20
H_A#11 A10# D7# H_ D#8
Y4 C20

1
H_A#12 A11# D8# H_ D#9
Y1 B24
H_A#13 A12# D9# H _D#10 H_CPURST# ITP_TDO
U1 D24
4 H_A#14 A13# D10# H _D#11 4
AA3 E24
H_A#15 A14# D11# H _D#12
Y3 C26
H_A#16 A15# D12# H _D#13
AA2 B23
H_A#17 A16# D13# H _D#14
AF4 E23
H_A#18 A17# D14# H _D#15
AC4 C25
H_A#19 A18# D15# H _D#16
AC7 H23
H_A#20 A19# D16# H _D#17 +VCCP
AC3 G25
H_A#21 A20# D17# H _D#18
AD3 L23
H_A#22 A21# D18# H _D#19 ITP_TMS ITP_TRST#
AE4 M26 1 2 1 2
H_A#23 A22# D19# H _D#20 R149 39.2_0603_1% R154 680_0402_5%
AD2 H24
H_A#24 A23# D20# H _D#21 ITP_TDI ITP_TCK
AB4 F25 1 2 1 2
H_A#25 A24# D21# H _D#22 R151 150_0402_1% R153 27.4_0402_1%
AC6
A25# ADDR GROUP DATA GROUP D22#
G24
H_A#26 AD5 J23 H _D#23
H_A#27 A26# D23# H _D#24
AE2 M23
H_A#28 A27# D24# H _D#25
AD6 J25
H_REQ #[0..4] H_A#29 A28# D25# H _D#26
<6> H_REQ#[0:4] AF3 L26
H_A#30 A29# D26# H _D#27
AE1 N24
H_A#31 A30# D27# H _D#28
AF1 M25
A31# D28# H _D#29
H26
H_ REQ#0 D29# H _D#30
R2 N25
H_ REQ#1 REQ0# D30# H _D#31
P3 K25
H_ REQ#2 REQ1# D31# H _D#32
T2 Y26
H_ REQ#3 REQ2# D32# H _D#33
P1 AA24
H_ REQ#4 T1
REQ3#
REQ4#
D33#
D34#
T25
U23
H _D#34
H _D#35
Thermal Sensor ADI ADM1032AR
D35# H _D#36 +3VS
<6> H_ADSTB#0 U3 V23
ADSTB0# D36# H _D#37
<6> H_ADSTB#1 AE5 R24
ADSTB1# D37# H _D#38
R26
D38# H _D#39
R23
D39# H _D#40 W = 15mil U11
<12> CLK_CPU_ITP A16 AA23
ITP_CLK0 D40# H _D#41
<12> CLK_CPU_ITP# A15 U26 2 1 8 EC_SMC_2 <31,34>

1
ITP_CLK1 D41# H _D#42 C94 R121@ VDD SCLK
V24 1
3 D42# H _D#43 H_THERMDA 3
<12> CLK_CPU_BCLK B15 U25 2 7 EC_SMD_2 <31,34>
BCLK0 D43# D+ SDATA

0.1U_0402_16V4Z

10K_0402_5%
B14 HOST CLK V26 H _D#44
<12> CLK_CPU_BCLK# BCLK1 D44# 1
Y23 H _D#45 C88 H_TH ERMDC 3 6
D45# H _D#46 2 D- ALERT#
AA26

2
D46# H _D#47 2200P_0402_25V7K
Y25 4 5
D47# H _D#48 THERM# GND
<6> H_ADS# N2 AB25
ADS# D48# H _D#49
<6> H_BNR# L1 AC23
BNR# D49# H _D#50 ADM1032AR_SOP8
<6> H_BPRI# J3 AB24
BPRI# D50# H _D#51
<6> H_BR0# N4
BR0# D51#
AC20 Address:1001_100X
L4 AC22 H _D#52
<6> H_DEFER# DEFER# D52# H _D#53
<6> H _ D R DY#
H2 AC25
DRDY# D53# H _D#54
<6> H_HIT# K3 AD23
HIT# D54# H _D#55
<6> H_HITM# K4
HITM# CONTROL GROUP D55#
AE22
1 2 H_IERR# A4 AF23 H _D#56
+VCCP R152
56_0402_5%
<6> H_LOCK#
H_CPURST#
J2
B11
IERR#
LOCK#
D56#
D57#
AD24
AF20
H _D#57
H _D#58
Fan Control circuit
<6> H_CPURST# RESET# D58# H _D#59
AE21
D59# H _D#60 +5VS
D60#
AD21 Joint use LM358A with Power
<6> H_RS#0 H_ RS#0 H1 AF25 H _D#61 C412
H_ RS#1 K1
RS0# D61#
AF22 H _D#62 0.1U_0402_16V4Z Battery detect circuit.
<6> H_RS#1 RS1# D62#
H_ RS#2 L2 AF26 H _D#63 1 2
<6> H_RS#2 RS2# D63#
<6> H _TRDY# M3 1

1
TRDY# PU5B C397

1
D25 5 LM358A_SO8 C D21
DINV0# H_DINV#0 <6> <34> EN_DFAN1 +
J26 7 FAN 1_ON 1 2 2 Q32 10U_0805_10V4Z
DINV1# H_DINV#1 <6> 0 2
C8 T24 1 2 6 R361 100_0402_5% B FMMT619_SOT23 1SS355_SOD323
BPM0# DINV2# H_DINV#2 <6> -
B8 AD20 R358 1 E
H_DINV#3 <6>

2
BPM1# DINV3# 10K_0402_5%
A9
BPM2#
+3VALW 1 R145 2 C9 C410

1
150_0402_1% BPM3# 0.1U_0402_16V4Z
C23 H_DSTBN#0 <6>
ITP_DBRESET# R1501 DSTBN0# 2
<23> ITP_DBRESET# 2 0_0402_5% A7 K24 H_DSTBN#1 <6>
D20
DBR# DSTBN1#
<6> H_DBSY# M2 W25 H_DSTBN#2 <6> 1 2 1N4148_SOD80
2 DBSY# DSTBN2# R364 8.2K_0402_5% 2
<7,22> H_DPSLP# B7 AE24 H_DSTBN#3 <6>
DPSLP# DSTBN3# JP7
C19 C22 H_DSTBP#0 <6>

2
<7> H_DPWR# DPWR# DSTBP0# FAN1_VOUT
A10 L24 H_DSTBP#1 <6>
PRDY# DSTBP1# 1
+VCCP 1 2 B10
PREQ# MISC DSTBP2#
W24 H_DSTBP#2 <6> 2
R374 H_PR OCHOT# B17 AE25
PROCHOT# DSTBP3# H_DSTBP#3 <6> 3
330_0402_5% +3VS 1 2
H_CPUPW RGD E4 R297 10K_0402_5% ACES_85205-0300
<22> H_CPUPW RGD PWRGOOD
H_CPUSLP# A6
<22> H_CPUSLP# SLP#
ITP_TCK A13 1
TCK <34> FANSPEED1
ITP_TDI C12 H_FER R# C702 1 2@ 100P_0402_50V8J 1 @
ITP_TDO TDI H_A20M# @ C313
A12 C2 H_A20M# <22>
R1462 TDO A20M# 1000P_0402_50V7K
1 @ 1K_0402_5% TEST1 C5 D3 H_FERR# <22>
H_CPUSLP# C703 1 2@ 100P_0402_50V8J C310
TEST1 FERR# 1000P_0402_50V7K 2
1 2 @ 1K_0402_5% TEST2 F23 A3 H_IGNNE#
H_IGNNE# <22>
R378 ITP_TMS TEST2 IGNNE# H_INIT# H_ DPSLP# C704 1 2
C11 B5 H_INIT# <22> 2@ 100P_0402_50V8J
ITP_TRST# TMS INIT# H_INTR
B13 D1 H_INTR <22>
TRST# LINT0/INTR C705 1
D4 H_ NMI
H_NMI <22>
H_STPCLK# 2@ 100P_0402_50V8J Close to Fan Conn.
LINT1/NMI
THERMAL C6 H_STPCLK# H_I NIT# C706 1 2@ 100P_0402_50V8J
STPCLK# H_STPCLK# <22>
H_THERMDA B18 B4 H_SMI#
H_TH ERMDC A18
THERMDA DIODE SMI# H_SMI# <22>
H_SMI# C707 1 2@ 100P_0402_50V8J
H _THERMTRIP# C17 THERMDC
THERMTRIP# LEGACY CPU
H_IGNNE# C708 1 2@ 100P_0402_50V8J

mFCBGA479 H_ NMI C709 1 2@ 100P_0402_50V8J

1 H_PR OCHOT# 1
1 2 +VCCP
R148 56_0402_5% 1 2 2 1
+VCCP THRMTRIP# <23>
R155 R156
56_0402_5% 56_0402_5%

H_THERMTRIP#
Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL INTEL CPU BANIAS (1 of 2)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
D ate: Friday, September 17, 2004 Sheet 4 of 47
A B C D E
 A B C D E

+CPU_CORE
U12B +CPU_CORE U 12C
R44 54.9_0402_1%
1 @ 2 VC CSENSE AE7 A2 F20 T26
VSSSENSE AF6 VCCSENSE VSS VCC VSS
1 2 A5 1 1 1 1 F22 U2
R45 @ 54.9_0402_1% VSSSENSE VSS VCC VSS
A8 G5 U6
VSS + C333 + C334 + C336 + C335 VCC VSS
A11 G21 U22
+ CPU_VCCA VSS 220U_D2_2VM 220U_D2_2VM 220U_D2_2VM 220U_D2_2VM VCC VSS
1 F26 A14 H6 U24 1
VCCA0 VSS @ VCC VSS
B1 A17 H22 V1
VCCA1 VSS 2 2 2 2 VCC VSS
1 R75 2 N1 A20 J5 V4
+1.8VS 0_1206_5% VCCA2 VSS VCC VSS
AC26 A23 J21 V5
VCCA3 VSS VCC VSS
A26 K22 V21
VSS VCC VSS
1 R108 2 P23 B3 U5 V25
+1.5VS @ 0_1206_5% +VCCP VCCQ0 VSS VCC VSS
W4 B6 V6 W3
VCCQ1 VSS +CPU_CORE VCC VSS
B9 V22 W6
VSS VCC VSS
B12 W5 W22
Dothan VCCA update(WW45 2003) D10
VCCP
Banias VSS
VSS
B16
10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M W21
VCC
VCC
VSS
VSS
W23
D12 B19 Y6 W26
Dothan B-Step support 1.5V only for VCCA D14
VCCP
VCCP
VSS
VSS
B22
1
C387
1
C382
1
C38
1
C52
1
C443
1
C385
1
C383
Y22
VCC
VCC
Banias VSS
VSS
Y2
D16 B25 AA5 Y5
VCCP VSS 10U_1206_6.3V6M VCC VSS
E11 C1 AA7 Y21
VCCP VSS 2 2 2 2 2 2 2 VCC VSS
E13 C4 AA9 Y24
VCCP VSS 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M VCC VSS
E15 C7 AA11 AA1
VCCP VSS VCC VSS
F10 C10 AA13 AA4
VCCP VSS VCC VSS
F12 C13 AA15 AA6
VCCP VSS +CPU_CORE VCC VSS
F14 C15 AA17 AA8
VCCP VSS VCC VSS
F16 C18 AA19 AA10
VCCP VSS 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M VCC VSS
K6 C21 AA21 AA12
VCCP VSS VCC VSS
L5 C24 AB6 AA14

POWER, GROUNG, RESERVED SIGNALS AND NC

VCCP VSS 1 1 1 1 1 1 1 VCC VSS
L21 D2 AB8 AA16
VCCP VSS C409 C442 C424 C80 C43 C39 C41 VCC VSS
M6 D5 AB10 AA18
VCCP VSS 10U_1206_6.3V6M VCC VSS
M22 D7 AB12 AA20
VCCP VSS 2 2 2 2 2 2 2 VCC VSS
N5 D9 AB14 AA22
VCCP VSS VCC VSS
N21
VCCP VSS
D11 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M AB16
VCC POWER, GROUND VSS
AA25
P6 D13 AB18 AB3
VCCP VSS VCC VSS
P22 D15 AB20 AB5
VCCP VSS +CPU_CORE VCC VSS
R5 D17 AB22 AB7
VCCP VSS VCC VSS
R21 D19 AC9 AB9
VCCP VSS 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M VCC VSS
T6 D21 AC11 AB11
2 VCCP VSS VCC VSS 2
T22 D23 1 1 1 1 1 1 1 AC13 AB13
VCCP VSS VCC VSS
U21 D26 AC15 AB15
VCCP VSS C42 C63 C75 C446 C444 C386 C384 VCC VSS
E3 AC17 AB17
VSS 10U_1206_6.3V6M VCC VSS
E6 AC19 AB19
VSS 2 2 2 2 2 2 2 VCC VSS
D6 E8 AD8 AB21
+CPU_CORE VCC VSS 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M VCC VSS
D8 E10 AD10 AB23
VCC VSS VCC VSS
D18 E12 AD12 AB26
VCC VSS VCC VSS
D20 E14 AD14 AC2
VCC VSS +CPU_CORE VCC VSS
D22 E16 AD16 AC5
VCC VSS VCC VSS
E5 E18 AD18 AC8
VCC VSS 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M VCC VSS
E7 E20 AE9 AC10
VCC VSS VCC VSS
E9 E22 1 1 1 1 1 1 1 AE11 AC12
VCC VSS VCC VSS
Resistor placed within E17
VCC VSS
E25 AE13
VCC VSS
AC14
E19 F1 C425 C408 C373 C374 C441 C375 C51 AE15 AC16
0.5" of CPU pin.Trace E21
VCC VSS
F4 10U_1206_6.3V6M AE17
VCC VSS
AC18
should be at least 25 VCC VSS 2 2 2 2 2 2 2 VCC VSS
F6 F5 AE19 AC21
VCC VSS 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M VCC VSS
miles away from any F8
VCC VSS
F7 AF8
VCC VSS
AC24
other toggling signal. F18 F9 AF10 AD1
VCC VSS VCC VSS
F11 AF12 AD4
VSS +CPU_CORE VCC VSS
F13 AF14 AD7
VSS VCC VSS
<45> PSI# E1 F15 AF16 AD9
PSI# VSS 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M VCC VSS
F17 AF18 AD11
+VCCP VSS VCC VSS
<45> C PU_VID0 E2 F19 1 1 1 1 1 1 1 AD13
VID0 VSS VSS
<45> C PU_VID1 F2 F21 AD15
VID1 VSS C40 C62 C76 C77 C78 C79 C445 VSS
<45> C PU_VID2 F3 F24 AD17
VID2 VSS VSS
1

<45> C PU_VID3 G3 G2 10U_1206_6.3V6M AD19

R66 VID3 VSS 2 2 2 2 2 2 2 VSS
<45> C PU_VID4 G4 G6 AD22
1K_0402_1% VID4 VSS 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M VSS
<45> C PU_VID5 H4 G22 M4 AD25
VID5 VSS VSS VSS
G23 M5 AE3
VSS VSS VSS
G26 M21 AE6
2

GTL _REF0 VSS VSS VSS

AD26 H3 M24 AE8
3 GTLREF0 VSS VSS VSS 3
E26 H5 N3 AE10
2

GTLREF1 VSS VSS VSS

1 1 G1 H21 N6 AE12
GTLREF2 VSS VSS VSS
R65 AC1
GTLREF3 VSS
H25 Vcc-core C,uF ESR, mohm ESL,nH N22
VSS VSS
AE14
2K_0402_1% C30 C29 J1 N23 AE16
1U_0603_10V4Z 220P_0402_50V7K VSS Decoupling VSS VSS
J4 N26 AE18
2 2 CO MP0 VSS VSS VSS
P25 J6 SPCAP,Polymer 4X220uF 12m ohm/4 3.5nH/4 P2 AE20
1

CO MP1 COMP0 VSS VSS VSS

P26 J22 P5 AE23
CO MP2 COMP1 VSS VSS VSS
AB2
COMP2 VSS
J24 MLCC 0805 X5R 35X10uF 5m ohm/35 0.6nH/35 P21
VSS VSS
AE26
CO MP3 AB1 K2 P24 AF2
COMP3 VSS VSS VSS
K5 R1 AF5
VSS VSS VSS
K21 R4 AF9
VSS VSS VSS
B2 K23 R6 AF11
RSVD VSS VSS VSS
AF7 K26 R22 AF13
RSVD VSS VSS VSS
C14 L3 R25 AF15
RSVD VSS +CPU_VCCA VSS VSS
C3 L6 T3 AF17
R158 RSVD VSS VSS VSS
L22 T5 AF19
VSS VSS VSS
2 1 C16 L25 T21 AF21
@ 1K_0402_5% TEST3 VSS VSS VSS
M1 T23 AF24
1

VSS 10U_1206_6.3V6M 10U_1206_6.3V6M 10U_1206_6.3V6M VSS VSS

R88 R93 R60 R58 1 1 1 1 1 1 1 1
mFCBGA479 mFCBGA479
27.4_0402_1% 54.9_0402_1% 27.4_0402_1% 54.9_0402_1% C74 C71 C34 C37 C64 C58 C104 C97
0.01U_0402_16V7K 10U_1206_6.3V6M
2

2 2 2 2 2 2 2 2

0.01U_0402_16V7K 0.01U_0402_16V7K 0.01U_0402_16V7K

+VCCP

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K

1 1
4 1 1 1 1 1 1 1 1 1 1 4
C93 + C113 + @ C399
C457 C434 C413 C392 C456 C404 C454 C419 C437 0.1U_0402_10V6K
150U_D2_6.3VM 150U_D2_6.3VM
2 2 2 2 2 2 2 2 2 2 2 2
Resistor placed within
0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
0.5" of CPU pin.Trace
should be at least 25 Compal Electronics, Inc.
miles away from any Title
other toggling signal. INTEL CPU BANIAS (2 of 2)
Size Document Number R ev
0.1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EAL20 LA-2462
Date: Friday, September 17, 2004 Sheet 5 of 47
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A B C D E
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS INC
 5 4 3 2 1

U14A
H_A#[3 ..31] H_D#[0..63]
<4> H_A#[3..31] H_D#[0..63] <4>
H_REQ#[0..4] Montara-GM(L)
<4> H_REQ#[0..4]
H_ A#3
H_ A#4
P23
HA#3 HD#0
K22 H_D#0
H_D#1
HOST REF VOLTAGE
T25 H27
HUB_PD[0..10] H_ A#5 HA#4 HD#1 H_D#2
D <22> HUB_PD[0..10] T28 K25 D
H_ A#6 HA#5 HD#2 H_D#3
R27 L24
H_ A#7 HA#6 HD#3 H_D#4 +VCCP +VCCP +VCCP
U23 J27
H_ A#8 HA7# HD#4 H_D#5
U24 G28
H_ A#9 HA#8 HD#5 H_D#6
R24 L27

2
H_ A#10 HA#9 HD#6 H_D#7
U28 L23
H_ A#11 HA#10 HD#7 H_D#8 R137 R138 R161
V28 L25
H_ A#12 HA#11 HD#8 H_D#9
U27 J24 301_0603_1% 301_0603_1% 49.9_0603_1%
H_ A#13 HA#12 HD#9 H_D#10
T27 H25
H_ A#14 HA#13 HD#10 H_D#11
V27 K23 W=10mil W=10mil W=10mil

1
H_ A#15 HA#14 HD#11 H_D#12 HXSWING H YSWING HCCVREF
U25 G27
H_ A#16 HA#15 HD#12 H_D#13
V26
HA#16 HD#13
K26 (0.35V) (0.35V) (0.7V)

2
H_ A#17 Y24 J23 H_D#14 2 2 2 2
H_ A#18 HA#17 HD#14 H_D#15 R136 R139 C106 R162 C119
V25 H26
H_ A#19 HA#18 HD#15 H_D#16 C108 C122
V23 F25
H_ A#20 HA#19 HD#16 H_D#17 150_0603_1% 0.1U_0402_16V4Z 150_0603_1% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
W25 F26
H_ A#21 HA#20 HD#17 H_D#18 1 1 1
100_0603_1% 1U_0603_10V4Z 1
Y25 B27

1
H_ A#22 HA#21 HD#18 H_D#19
AA27 H23
H_ A#23 HA#22 HD#19 H_D#20
W24 E27
H_ A#24 HA#23 HD#20 H_D#21
W23 G25
H_ A#25 HA#24 HD#21 H_D#22
W27 F28
H_ A#26 HA#25 HD#22 H_D#23
Y27 D27
H_ A#27 HA#26 HD#23 H_D#24 + VCCP +VCCP
AA28 G24
H_ A#28 HA#27 HD#24 H_D#25
W28 C28
H_ A#29 HA#28 HD#25 H_D#26
AB27 B26

2
H_ A#30 HA#29 HD#26 H_D#27
Y26 G22
H_ A#31 HA#30 HD#27 H_D#28 R425 R417
AB28 C26
HA#31 HD#28 H_D#29
E26 49.9_0603_1% 49.9_0603_1%
H_REQ#0 HD#29 H_D#30
R28 G23
H_REQ#1 HREQ#0 HD#30 H_D#31
P25 B28 W=10mil W=20mil

1
H_REQ#2 HREQ#1 HD#31 H_D#32 HAV REF HDVREF
R23 B21
H_REQ#3 HREQ#2 HD#32 H_D#33
R25
HREQ#3 HD#33
G21 (0.7V) (0.7V)

2
C H_REQ#4 H_D#34 C

<4> H_ADSTB#0
T23
T26
HREQ#4
HADSTB#0
HOST HD#34
HD#35
C24
C23 H_D#35
2 2 2
C490
AA26 D22 H_D#36 R427 C516 C494
<4> H_ADSTB#1 HADSTB#1 HD#36 R416
C25 H_D#37 0.1U_0402_16V4Z 0.1U_0402_16V4Z
HD#37 H_D#38 100_0603_1% 1 1
1U_0603_10V4Z 1
<12> CLK_MCH_BCLK# AD29 E24

1
BCLK# HD#38 H_D#39 100_0603_1%
<12> CLK_MCH_BCLK AE29 D24
H YSWING BCLK HD#39 H_D#40
K28 G20
HXSWING HYSWING HD#40 H_D#41
W=10mil B18
HXSWING HD#41
E23
R390 1 2 27.4_0402_1% HYRCO MP H28 B22 H_D#42
R134 1 HXRCOMP HYRCOMP HD#42 H_D#43
2 27.4_0402_1% B20 B23
HXRCOMP HD#43 H_D#44
F23
HDVREF HD#44 H_D#45
K21 F21
HVREF0 HD#45 H_D#46
J21 C20
HVREF1 HD#46 H_D#47
J17 C21
HCCVREF
HAV REF
Y28
HVREF2
HCCVREF
HD#47
HD#48
G18 H_D#48
H_D#49
HUB I/F REF VOLTAGE
Y22 E19
HAVREF HD#49 H_D#50
E20
H_DSTBN#0 HD#50 H_D#51 +1.5VS
J28 G17
<4> H_DSTBN#0 H_DSTBN#1 HDSTBN#0 HD#51 H_D#52
C27 D20
<4> H_DSTBN#1 H_DSTBN#2 HDSTBN#1 HD#52 H_D#53
E22 F19
HDSTBN#2 HD#53

2
<4> H_DSTBN#2 H_DSTBN#3 H_D#54
D18 C19
<4> H_DSTBN#3 H_DSTBP#0 HDSTBN#3 HD#54 H_D#55 R171
K27 C17
<4> H_DSTBP#0 H_DSTBP#1 HDSTBP#0 HD#55 H_D#56
D26 F17 80.6_0603_1%
<4> H_DSTBP#1 H_DSTBP#2 HDSTBP#1 HD#56 H_D#57
E21 B19
<4> H_DSTBP#2 H_DSTBP#3 HDSTBP#2 HD#57 H_D#58
E18 G16

1
<4> H_DSTBP#3 H_DINV#0 HDSTBP#3 HD#58 H_D#59
<4> H_DINV#0
J25
DINV0# HD#59
E16 W=20mil
H_DINV#1 E25 C16 H_D#60 HU B_VSWING HUB _VSWING (0.796V)
<4> H_DINV#1 H_DINV#2 DINV1# HD#60 H_D#61
B25 E17
<4> H_DINV#2 H_DINV#3 DINV2# HD#61 H_D#62
G19 D16 2 2

2
<4> H_DINV#3 DINV3# HD#62 H_D#63 C146
C18 C145
CPURST# HD#63
<4> H_CPURST# F15 R172
B CPURST# 51.1_0603_1% 0.01U_0402_16V7K B
0.1U_0402_16V4Z
H UB_PD0 U7 1 1
H UB_PD1 HL_0
U4

1
H UB_PD2 HL_1
U3
HL_2 ADS#
L28 H_ADS# <4> W=20mil
H UB_PD3 V3 M25 HUB _VREF HUB _VREF (0.35V)
HL_3 HTRDY# H_ T RDY# <4>
H UB_PD4 W2 N24
HL_4 DRDY# H_DRDY# <4>
H UB_PD5 W6 M28 2 2
H_ DEFER# <4>

2
H UB_PD6 HL_5 DEFER# C169 C170
V6 N28 H_HITM# <4>
H UB_PD7 HL_6 HITM# R180
W7 N27 H_HIT# <4>
H UB_PD8 HL_7 HIT# 40.2_0603_1% 0.1U_0402_16V4Z 0.01U_0402_16V7K
T3 P27 H_LOCK# <4>
H UB_PD9 HL_8 HLOCK# 1 1
V5 M23 H_BR0# <4>
HL_9 BREQ0#
HUB I/F

HUB_PD10 V4 N25 H _BNR# <4>

1
HI_PSTRB HL_10 BNR#
<22> HUB_PSTRB W3 P28 H_BPRI# <4>
HI_PSTRB# HLSTB BPRI#
<22> HUB_PSTRB# V2 M26 H_ D BSY# <4>
HUB_RCOMP HLSTB# DBSY#
+1.35VS 2 1 T2 N23 H_RS#0 <4>
R461 37.4_0402_1% HU B_VSWING HLRCOMP RS#0
U2 P26 H_RS#1 <4>
HUB _VREF PSWING RS#1
W1 M27 H_RS#2 <4>
HLVREF RS#2

RG82855GME_uFCBGA732

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
INTEL 855GME-HOST(1/4)
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
Date: Friday, September 17, 2004 Sheet 6 of 47
5 4 3 2 1
 5 4 3 2 1

U14B 855GME DVO/AGP Pin Muxing

DVOC_D[0..11]
<13,19> DVOC_D[0..11] Montara-GM(L) Ball DVO Mode AGP Mode
DVOB_D[0..11] DVOB_ D0 R3 C9
<13> DVOB_D[0..11] DVOBD0/(NC) BLUE GMCH_CRT_B <21>
DVOB_ D1 R5 D9 R3 DVOBD0 GAD3
AGP_SBA[0..7] DVOB_ D2 DVOBD1/(NC) BLUE#
<13> AGP_SBA[0..7] R6 C8 GMCH_CRT_G <21> R5 DVOBD1 GAD2
DVOB_ D3 DVOBD2/(NC) GREEN
R4 D8 R6 DVOBD2 GAD5
DVOB_ D4 DVOBD3/(NC) GREEN#
P6 A7 GMCH_CRT_R <21> R4 DVOBD3 GAD4
DVOB_ D5 DVOBD4/(NC) RED CLK_ MCH_48M CLK_SSC_66M
P5 A8 P6 DVOBD4 GAD7
DVOB_ D6 DVOBD5/(NC) RED#
N5 H10 G MCH _CRT_HSYNC <21> P5 DVOBD5 GAD6

2
DVOB_ D7 DVOBD6/(NC) HSYNC
P2 J9 N5 DVOBD6 GAD8

DAC
G M CH_CRT_VSYNC <21>

2
DVOB_ D8 DVOBD7/(NC) VSYNC REFSET @ R142
N2 E8 P2 DVOBD7 GCBE#0
DVOB_ D9 DVOBD8/(NC) REFSET R418 33_0402_5%
D N3 B6 GMCH_CRT_CLK <21> N2 DVOBD8 GAD10 D

2
DVOB_ D10 DVOBD9/(NC) DDCACLK 33_0402_5% @
M1 G9 GMCH_CRT_DATA <21> N3 DVOBD9 GAD9
CLK_ MCH_66M DVOB_ D11 DVOBD10/(NC) DDCADATA R420
M5 M1 DVOBD10 GAD12

1
DVOBD11/(NC)
127_0603_1% M5 DVOBD11 GAD11

1
1
AG P_ADSTB0 P3 2 2 P3 DVOBCLK GADSTB0
<13> AGP_ADSTB0 DVOBCLK/(NC)
@ AG P_ADSTB0# P4 G14 C491 C107 P4 DVOBCLK# GADSTB0#

1
<13> AGP_ADSTB0# DVOBCLK#/(NC) IYAM0 GMCH_TXOUT0- <20>
R469 AGP_AD0 T6 E15 @ @ T6 DVOBHSYNC GAD0
<13> AGP_AD0 DVOBHSYNC/(NC) IYAM1 GMCH_TXOUT1- <20>
33_0402_5% AGP_AD1 T5 C15 22P_0402_50V8J 22P_0402_50V8J T5 DVOBVSYNC GAD1
<13> AGP_AD1 DVOBVSYNC/(NC) IYAM2 GMCH_TXOUT2- <20> 1 1
AGP_CBE#1 L2 C13 L2 DVOBBLANK GCBE#1
<13> AGP_CBE#1
2

AGP_AD14 DVOBBLANK#/(NC) IYAM3

<13> AGP_AD14 M2 F14 GMCH_TXOUT0+ <20> M2 DVOBFLDSTL GAD14
DVOBFLDSTL/(NC) IYAP0
1 E14 GMCH_TXOUT1+ <20> G2 DVOBCINTR# GAD30
@ AGP_AD30 IYAP1
<13> AGP_AD30 G2 C14 GMCH_TXOUT2+ <20> M3 DVOBCCLKINT GAD13
C565 DVOBC_CLKINT M3 DVOBCINTR# IYAP2
<13,19> DVOBC_CLKINT B13 J3 DVOCCLK GADSTB1
22P_0402_50V8J DVOBCCLKINT IYAP3
H12 GMCH_TZOUT0- <20> J2 DVOCCLK# GADSTB1#
2 DVOC_CLK IYBM0
<13,19> DVOC_CLK J3 E12 GMCH_TZOUT1- <20> K6 DVOCHSYNC GAD17
DVOC_CL K# DVOCCLK IYBM1
<13,19> DVOC_CLK# J2 C12 GMCH_TZOUT2- <20> L5 DVOCVSYNC GAD16
DVOC_HS YNC DVOCCLK# IYBM2
K6 G11 L3 DVOCBLANK GAD18
<13,19> DVOC_HS YNC DVO C_ VSYNC DVOCHSYNC IYBM3
L5 G12 GMCH_TZOUT0+ <20> H5 DVOCFLDSTL GAD31
<13,19> DVO C_ VSYNC AGP_AD18 DVOCVSYNC IYBP0
<13> AGP_AD18 L3 E11 GMCH_TZOUT1+ <20> K7 MI2CCLK GIRDY#
AGP_AD31 DVOCBLANK# IYBP1
<13> AGP_AD31 H5 C11 GMCH_TZOUT2+ <20> N6 MI2CDATA GDEVSEL#
DVOCFLDSTL IYBP2
G10 N7 MDVICLK GTRDY#
IYBP3
D14 GMCH_TXCLK- <20> M6 MDVIDATA GFRAME#
MI2CCLK ICLKAM
<13,19> MI2CCLK K7 E13 GMCH_TXCLK+ <20> P7 MDDCCLK GSTOP#
MI2CDATA MI2CCLK ICLKAP
N6 E10 T7 MDDCDATA GAD15

DVO
LVDS
<13,19> MI2CDATA MI2CDATA ICLKBM GMCH_TZCLK- <20>
MDVICLK N7 F10 K5 DVOCD0 GAD19
<13> MDVICLK MDVICLK ICLKBP GMCH_TZCLK+ <20>
MDVIDATA M6 K1 DVOCD1 GAD20
<13> MDVIDATA MDVIDATA
2 1 AGP_AD14 <13> MD DCCLK
MD DCCLK P7 B4 GMCH_LCD_ CLK
GMCH_LCD_CLK <20> K3 DVOCD2 GAD21
R451 100K_0402_5% MDDCDATA MDDCCLK DDCPCLK GMCH_LCD_DATA
<13> M DDCDATA T7 C5 GMCH_LCD_DATA <20> K2 DVOCD3 GAD22
MDDCDATA DDCPDATA
1 2 AGP_AD31 J6 DVOCD4 GAD23
R434 100K_0402_5% G8 J5 DVOCD5 GCBE#3
PANELBKLTCTL
1 2 DVOBC_CLKINT D VOC_D0 K5 F8 GMCH_ENBKL <34> H2 DVOCD6 GAD25
R445 100K_0402_5% D VOC_D1 DVOCD0 PANELBKLTEN
K1 A5 G M CH_ENVDD <20> H1 DVOCD7 GAD24
C D VOC_D2 DVOCD1 PANELVDDEN C
K3 1 2 H3 DVOCD8 GAD27
D VOC_D3 DVOCD2 C507 22P_0402_50V8J
K2 D12 H4 DVOCD9 GAD26
D VOC_D4 DVOCD3 LVREFH
J6 F12 H6 DVOCD10 GAD29
DVOCD4 LVREFL
+1.5VS 2 1 AGP_AD30 D VOC_D5 J5 G3 DVOCD11 GAD28
R437 100K_0402_5% D VOC_D6 DVOCD5 +3VS
H2 B12 E5 ADDID0 GSBA0
D VOC_D7 DVOCD6 LVBG LIBG
H1 A10 2 1 F5 ADDID1 GSBA1
D VOC_D8 DVOCD7 LIBG R409 1.5K_0603_1%
H3 E3 ADDID2 GSBA2

2
D VOC_D9 DVOCD8
H4 E2 ADDID3 GSBA3
DVOC_D10 DVOCD9 R421
H6 G5 ADDID4 GSBA4
DVOC_D11 DVOCD10 CLK_ MCH_48M
G3 B7 CLK_MCH_48M <12> 510_0402_5% F4 ADDID5 GSBA5
DVOCD11 DREFCLK
1 2 A GPBUSY# B17 CLK_SSC_66M
CLK_SSC_66M <12>
@ G6 ADDID6 GSBA6
<13,23> AGP_BUSY# DREFSSCLK

CLKS
R422 UMA@ 0_0402_5% H9 F6 ADDID7 GSBA7

1
LCLKCTLA LCL KCTLB
C6 L7 DVODETECT GPAR
LCLKCTLB
reserved for DVO mode unpoped for 1.05V FSB D5 DPMS GPIPE#
AG P_SBA0 E5 F2 RVSD1 GSBSTB
AG P_SBA1 ADDID0
F5 LCLKCTLB: High for P4, NC for Banias F3 RVSD2 GSBSTB#
+1.5VS AG P_SBA2 ADDID1
E3 AA22 H_D PWR# <4> B2 RVSD3 GGNT#
AG P_SBA3 ADDID2 DPWR#/(NC)
E2 Y23 H_DPSLP# <4,22> B3 RVSD4 GREQ#
AG P_SBA4 ADDID3 DPSLP# PCIRST#
G5 AD28 PCIRST# <13,19,22,25,27,28,30> C2 RVSD5 GST2
2

ADDID4 RSTIN#
R419
AG P_SBA5
AG P_SBA6
F4
ADDID5 MISC C3
C4
GST1
GST0
GST1
GST0
G6 J11 VGATE <12,23,45>
10K_0603_5% AG P_SBA7 ADDID6 PWROK
1 2 F6 D2 RVSD8 GWBF#
UMA@ R426 1K_0402_5% ADDID7 EXTTS
D6 1 2 +3VS D3 RVSD9 GRBF#
AGP_ PAR EXTTS0 R423 10K_0402_5%
L7 AJ1 L4 RVSD11 GCBE#2
1

<13> AGP_PAR DVODETECT MCHDETECTVSS

Q35 D5
BSN20_SOT23 +AGP_ VREF DPMS
+AGP_VREF F1
1

D A GPBUSY# GVREF
F7
DVORCOMP AGPBUSY#
<23> R TCCLK 2 D1 B1
G CLK_ MCH_66M DVORCOMP NC0
Y3 AH1
UMA@ S
<12> CLK_MCH_66M
W=10mil
GCLKIN NC1
A2 Isolating AGP singals Starp Pin:
3

NC2
AA5 AJ2
(For M11P) (For UMA)
2

B AGP_SBSTB RVSD0 NC3 B

<13> AGP_SBSTB F2 A28
AGP_SBSTB# RVSD1 NC4 +5VS
reserved for DVO mode <13> AGP_SBSTB# F3
RVSD2 NC5
AJ28 *
R432 AG P_GNT# B2 A29 U39 M11@ +1.5VS
<13> AGP_GNT# RVSD3 NC6
NC

40.2_0603_1% AGP_REQ# B3 B29 PCIRST# 1 14 *

<13> AGP_REQ# RVSD4 NC7 OE1# VCC
AGP_ST2 C2 AH29 AGP_ST0 2 13 PCIRST# AGP_ST0 R413 1 UMA@ 2 1K_0402_5%
1

<13> AGP_ST2 RVSD5 NC8 1A OE4#

AGP_ST1 C3 AJ29 GST0 3 12 AGP_ST1 *
<13> AGP_ST1 GST[1] NC9 1B 4A
AGP_ST0 C4 AA9 4 11 GST1 AGP_ST1 R405 1 UMA@ 2 1K_0402_5%
<13> AGP_ST0 GST[0] NC10 OE2# 4B
AGP_WBF# D2 AJ4 AGP_ST2 5 10 *
<13> AGP_WBF# RVSD8 NC11 2A OE3#
AGP_RBF# D3 GST2 6 9 AGP_ PAR AGP_ST2 R430 1 UMA@ 2 1K_0402_5%
<13> AGP_RBF# RVSD9 2B 3A
D7 7 8 G PAR *
AGP_CBE#2 RVSD10 GND 3B R412 1 @
<13> AGP_CBE#2 L4 2 1K_0402_5%
RVSD11 FST3125MTCX_SSOP14 +1.5VS
RG82855GME_uFCBGA732 AGP_PAR R411 1 UMA@ 2 1K_0402_5%
GST0 1 2
R414 M11@ 1K_0402_5%
GST1 1 2
+1.5VS R406 M11@ 1K_0402_5% DVODETECT(AGP_PAR):
I2C BUS PULL UP +1.5VS DVO/AGP REF Voltage GST2 1 2
R415 M11@ 1K_0402_5% HIGH for AGP, LOW for DVO
2

RP50 1 2
MDVICLK 1 8 R439 R407 M11@ 1K_0402_5%
MD DCCLK 2 7 1K_0603_1% G PAR 2 1
MDVIDATA 3 6 R401 @ 1K_0402_5%
MDDCDATA 4 5 +AGP_ VREF +AGP_VREF
2 1

2.2K_1206_8P4R_5% 2
R442
MI2CCLK 2 1 C533
R429 2.2K_0402_5% 0.1U_0402_16V4Z Starp pin list
MI2CDATA 1K_0603_1% 1
2 1
1

R441 2.2K_0402_5%
A
ST2 ST1 ST0 PSB/Mem/GFX A
0 0 0 400 / 266 / 200
0 0 1 400 / 200 / 200
0 1 0 400 / 200 / 133
1 1 1 400 / 333 / 250 * Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
INTEL 855GME-AGP&LVDS(2/4)
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
Date: Friday, September 17, 2004 Sheet 7 of 47
5 4 3 2 1
 5 4 3 2 1

DDR_SDQ[0..63] DDR_SMA[6..12] U 14D

DDR_SDQ[0..63] <10> DDR_SMA[6..12] <10,11>
C1 R17
DDR_SDQS[0..7] DDR_SDM[0..7] VSS0 VSS91
D DR_SDQS[0..7] <10> DDR_SDM[0..7] <10> G1 U17
VSS1 VSS92
L1 AB17
VSS2 VSS93
U1 AC17
VSS3 VSS94
AA1 F18
VSS4 VSS95
AE1 J18
U1 4C VSS5 VSS96
R2 AA18
VSS6 VSS97
AG3 AG18
VSS7 VSS98
AJ3 A19
Montara-GM(L) D4
VSS8
VSS9
VSS99
VSS100
D19
DDR_SMA0 AC18 AF2 DD R_SDQ0 G4 H19
<10,11> DDR_SMA0 SMA0 SDQ0 VSS10 VSS101
DDR_SMA1 AD14 AE3 DD R_SDQ1 K4 AB19
<10,11> DDR_SMA1 SMA1 SDQ1 VSS11 VSS102
DDR_SMA2 AD13 AF4 DD R_SDQ2 N4 AE19
D <10,11> DDR_SMA2 SMA2 SDQ2 VSS12 VSS103 D
DDR_SMA3 AD17 AH2 DD R_SDQ3 T4 F20
<10,11> DDR_SMA3 SMA3 SDQ3 VSS13 VSS105
DDR_SMA4 AD11 AD3 DD R_SDQ4 W4 J20
<10,11> DDR_SMA4 SMA4 SDQ4 VSS14 VSS106
DDR_SMA5 AC13 AE2 DD R_SDQ5 AA4 AA20
<10,11> DDR_SMA5 SMA5 SDQ5 VSS15 VSS107
DDR_SMA6 AD8 AG4 DD R_SDQ6 AC4 AC20
DDR_SMA7 SMA6 SDQ6 DD R_SDQ7 VSS16 VSS108
AD7 AH3 AE4 A21
DDR_SMA8 SMA7 SDQ7 DD R_SDQ8 VSS17 VSS109
AC6 AD6 B5 D21
DDR_SMA9 SMA8 SDQ8 DD R_SDQ9 VSS18 VSS110
AC5 AG5 U5 H21
DDR_SMA10 SMA9 SDQ9 DDR_SDQ10 VSS19 VSS111
AC19 AG7 Y5 M21
DDR_SMA11 SMA10 SDQ10 DDR_SDQ11 VSS20 VSS112
AD5 AE8 Y6 P21
DDR_SMA12 SMA11 SDQ11 DDR_SDQ12 VSS21 VSS113
AB5 AF5 AG6 T21
SMA12 SDQ12 DDR_SDQ13 VSS22 VSS114
AH4 C7 V21
SDQ13 DDR_SDQ14 VSS23 VSS115
AF7 E7 Y21
SDQ14 VSS24 VSS116

Montara-GM(L)
AH6 DDR_SDQ15 G7 AA21
D DR_SDQS0 SDQ15 DDR_SDQ16 VSS25 VSS117
D DR_SDQS1
AG2
AH5
SDQS0
SDQS1
MEMORY SDQ16
SDQ17
AF8
AG8 DDR_SDQ17
J7
M7
VSS26
VSS27
VSS118
VSS119
AB21
AG21
D DR_SDQS2 AH8 AH9 DDR_SDQ18 R7 B24
D DR_SDQS3 SDQS2 SDQ18 DDR_SDQ19 VSS28 VSS120
AE12 AG10 AA7 F22
D DR_SDQS4 SDQS3 SDQ19 DDR_SDQ20 VSS29 VSS121
AH17 AH7 AE7 J22
D DR_SDQS5 SDQS4 SDQ20 DDR_SDQ21 VSS30 VSS122
AE21 AD9 AJ7 L22
D DR_SDQS6 SDQS5 SDQ21 DDR_SDQ22 VSS31 VSS123
AH24 AF10 H8 N22
D DR_SDQS7 SDQS6 SDQ22 DDR_SDQ23 VSS32 VSS124
AH27 AE11 K8 R22
SDQS7 SDQ23 DDR_SDQ24 VSS33 VSS125
AD15 AH10 P8 U22
SDQS8 SDQ24 DDR_SDQ25 VSS34 VSS126
AH11 T8 W22
SDQ25 DDR_SDQ26 VSS35 VSS127
AG13 V8 AE22
DD R_SWE# SDQ26 DDR_SDQ27 VSS36 VSS128
<10,11> DDR _SWE# AD25 AF14 Y8 A23
D DR_SRAS# SWE# SDQ27 DDR_SDQ28 VSS37 VSS129
<10,11> DD R_SRAS# AC21 AG11 AC8 D23
D DR_SCAS# SRAS# SDQ28 DDR_SDQ29 VSS38 VSS130
<10,11> DD R_SCAS# AC24 AD12 E9 AA23
SCAS# SDQ29 DDR_SDQ30 VSS39 VSS131
AF13 L9 AC23
SDQ30 DDR_SDQ31 VSS40 VSS132
AH13 N9 AJ23
SDQ31 DDR_SDQ32 VSS41 VSS133
<10> D DR_CLK0 AB2 AH16 R9 F24
SCK0 SDQ32 DDR_SDQ33 VSS42 VSS134
<10> DDR_CLK0# AA2 AG17 U9 H24
C SCK0# SDQ33 DDR_SDQ34 VSS43 VSS135 C
<10> D DR_CLK1 AC26 AF19 W9 K24
SCK1 SDQ34 DDR_SDQ35 VSS44 VSS136
<10> DDR_CLK1# AB25 AE20 AB9 M24
SCK1# SDQ35 DDR_SDQ36 VSS45 VSS137
AC3 AD18 AG9 P24
SCK2 SDQ36 DDR_SDQ37 VSS46 VSS138
AD4 AE18 C10 T24
SCK2# SDQ37 DDR_SDQ38 VSS47 VSS139
<10> D DR_CLK3 AC2 AH18 J10 V24
SCK3 SDQ38 DDR_SDQ39 VSS48 VSS140
<10> DDR_CLK3# AD2 AG19 AA10 AA24
SCK3# SDQ39 DDR_SDQ40 VSS49 VSS141
<10> D DR_CLK4 AB23 AH20 AE10 AG24
SCK4 SDQ40 DDR_SDQ41 VSS50 VSS142
<10> DDR_CLK4# AB24 AG20 D11 A25
SCK4# SDQ41 DDR_SDQ42 VSS51 VSS143
AA3 AF22 F11 D25
SCK5 SDQ42 DDR_SDQ43 VSS52 VSS144
AB4 AH22 H11 AA25
SCK5# SDQ43 DDR_SDQ44 VSS53 VSS145
AF20 AB11 AE25
SDQ44 DDR_SDQ45 VSS54 VSS146
AH19 AC11 G26
SDQ45 DDR_SDQ46 VSS55 VSS147
<10,11> DD R_CKE0 AC7 AH21 AJ11 J26
SCKE0 SDQ46 DDR_SDQ47 VSS56 VSS148
<10,11> DD R_CKE1 AB7 AG22 J12 L26
SCKE1 SDQ47 DDR_SDQ48 VSS57 VSS149
<10,11> DD R_CKE2 AC9 AE23 AA12 N26
SCKE2 SDQ48 DDR_SDQ49 VSS58 VSS150
<10,11> DD R_CKE3 AC10 AH23 AG12 R26
SCKE3 SDQ49 DDR_SDQ50 VSS59 VSS151
<10,11> D DR_SCS#0 AD23 AE24 A13 U26
SCS#0 SDQ50 DDR_SDQ51 VSS60 VSS152
<10,11> D DR_SCS#1 AD26 AH25 D13 W26
SCS#1 SDQ51 DDR_SDQ52 VSS61 VSS153
<10,11> D DR_SCS#2 AC22 AG23 F13 AB26
SCS#2 SDQ52 DDR_SDQ53 VSS62 VSS154
AC25 AF23 H13 A27
DDR REF & SWING VOLTAGE <10,11> D DR_SCS#3 SCS#3 SDQ53
AF25 DDR_SDQ54 N13
VSS63 VSS155
F27
SDQ54 DDR_SDQ55 VSS64 VSS156
AG25 R13 AC27
+2.5V DDR_SBS0 SDQ55 DDR_SDQ56 VSS65 VSS157
<10,11> D DR_SBS0 AD22 AH26 U13 AG27
DDR_SBS1 SBA0 SDQ56 DDR_SDQ57 VSS66 VSS158
<10,11> D DR_SBS1 AD20 AE26 AB13 AJ27
SBA1 SDQ57 DDR_SDQ58 VSS67 VSS159
AG28 AE13 AC28
SDQ58 DDR_SDQ59 VSS68 VSS160
AF28 J14 AE28
1

D DR_SDM0 SDQ59 DDR_SDQ60 VSS69 VSS161

2 AE5 AG26 P14 C29
C577 R482 D DR_SDM1 SDM0 SDQ60 DDR_SDQ61 VSS70 VSS162
AE6 AF26 T14 E29
60.4_0603_1% D DR_SDM2 SDM1 SDQ61 DDR_SDQ62 VSS71 VSS163
AE9 AE27 AA14 G29
0.1U_0402_16V4Z D DR_SDM3 SDM2 SDQ62 DDR_SDQ63 VSS72 VSS164
AH12 AD27 AC14 J29
1 D DR_SDM4 SDM3 SDQ63 VSS73 VSS165
W=10mil AD19 D15 L29
2

B SMRCOMP D DR_SDM5 SDM4 VSS74 VSS166 B

AD21 H15 N29
D DR_SDM6 SDM5 VSS75 VSS167
(1.25V) AD24 N15 U29
1

D DR_SDM7 SDM6 VSS76 VSS168

AH28 AG14 R15 W29
R478 SDM7 SDQ64 VSS77 VSS169
AH15 AE14 U15 AA29
60.4_0603_1% SDM8 SDQ65 VSS78 VSS170
AE17 AB15 AJ10
SDQ66 +2.5V VSS79 VSS171
AG16 AG15 AJ12
DDR_SMA_B1 AD16 SDQ67 VSS80 VSS172
<10,11> DDR_SMA_B1 AH14 F16 AJ18
2

DDR_SMA_B2 AC12 SMA_B1 SDQ68 VSS81 VSS173

<10,11> DDR_SMA_B2 AE15 J16 AJ20
DDR_SMA_B4 AF11 SMA_B2 SDQ69 VSS82 VSS174
<10,11> DDR_SMA_B4 AF16 P16 C22
SMA_B4 SDQ70 VSS83 VSS176

1
DDR_SMA_B5 AD10 AF17 2 T16 D28
<10,11> DDR_SMA_B5 SMA_B5 SDQ71 VSS84 VSS177
+2.5V R166 AA16 E28
C142 75_0603_1% VSS85 VSS178
AC15 AE16 L6
RCVENOUT# 0.1U_0402_16V4Z VSS86 VSS179
AC16 A17 RG82855GME_uFCBGA732 T9
1

RCVENIN# 1 VSS87 VSS180

D17 AJ26

2
R174 SMRCOMP SMVREF0 VSS88 VSS181
AB1 AJ24 H17
SMRCOMP SMVREF0 VSS89
604_0603_1% W=20mil N17

1
SMVSWINGL VSS90
W=10mil AJ22
SMVSWINGL 2 2
S MVSWINGH AJ19 R168
2

SMVSWINGL SMVSWINGH C148 C149 75_0603_1%

(0.497V) RG82855GME_uFCBGA732 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1

1 1
2

2
R175
150_0603_1% C154
1
0.1U_0402_16V4Z
2

+2.5V

A A
1

R181
150_0603_1%
W=10mil
2

S MVSWINGH
(2.002V) Compal Electronics, Inc.
1

2
R185 Title
C171
604_0603_1% 0.1U_0402_16V4Z
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
INTEL 855GME DDR(3/4)
1 Size Document Number R ev
2

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
Date: Friday, September 17, 2004 Sheet 8 of 47
5 4 3 2 1
 5 4 3 2 1

U14E
+1.35VS + VCCP +1.35VS
Montara-GM(L) (1.8A) For VCC
J15 G15
VCC0 VTTLF0
P13 H16
VCC1 VTTLF1
T13 H18 1
VCC2 VTTLF2 C569
N14
VCC3 VTTLF3
J19 1 C539 2 2 2 2 2 2 2 2
R14 H20 + C509 C496 C527 C538 C517 C524 C512 C553
VCC4 VTTLF4
U14 L21
VCC5 VTTLF5 150U_D2_6.3VM 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
P15 N21
VCC6 VTTLF6 2 2
10U_0805_10V4Z 1 1
0.1U_0402_16V4Z 1 1
0.1U_0402_16V4Z 1 1
0.1U_0402_16V4Z 1 1
0.1U_0402_16V4Z
T15 R21
VCC7 VTTLF7
AA15 U21
VCC8 VTTLF8
N16 H22
VCC9 VTTLF9
D R16 M22 D
VCC10 VTTLF10
U16 P22
VCC11 VTTLF11
P17 T22
VCC12 VTTLF12
T17 V22
VCC13 VTTLF13 +1.35VS +1.35VS_PLLA +1.35VS +1.35VS_PLLB +1.35VS
AA17 Y29
VCC14 VTTLF14
AA19
VCC15 VTTLF15
K29 W=20mil (90mA) For VCCHL W=20mil (0.4A) W=20mil (0.4A)
W21 F29 1 2 1 2
VCC16 VTTLF16 R159 1_0805_5% UMA@ R143 1_0805_5% UMA@
H14 AB29
+1.35VS VCC17 VTTLF17
A26 1 1
VTTLF18
VTTLF19
A20 1 2 2 2 2
+
2 For VCCADPLLA +
2 For VCCADPLLB
V1 A18 C526 C547 C544 C564 C92 C116 C115 C111 C112
VCCHL0 VTTLF20
Y1
VCCHL1
W5 A22 2 1 C103 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z UMA@ 220U_D2_4VM_R12
VCCHL2 VTTHF0 2 1 1 1 1 2 1 2 1
U6 A24 2 1 C 96 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z UMA@ 0.1U_0402_16V4Z UMA@
VCCHL3 VTTHF1
U8 H29 2 1 C476 0.1U_0402_16V4Z 220U_D2_4VM_R12 UMA@
VCCHL4 VTTHF2
W8 M29 2 1 C481 0.1U_0402_16V4Z
VCCHL5 VTTHF3
V7 V29 2 1 C489 0.1U_0402_16V4Z Close to ball D29, Y2
VCCHL6 VTTHF4
V9
VCCHL7
AC1
VCCSM0
D29 AG1
+1.35VS_PLLA VCCAHPLL VCCSM1 +1.5VS +1.5VS +1.5VS
Y2 AB3
+1.35VS_PLLB VCCAGPLL VCCSM2
AF3 W=40mil (90mA) For VCCDVO W=20mil (70mA) W=20mil (90mA)
POWER
VCCSM3
A6 Y4
VCCADPLLA VCCSM4 +2.5V
B16
VCCADPLLB VCCSM5
AJ5 For VCCADAC For VCCALVDS
AA6 1
+1.5VS VCCSM6
AB6 1 2 2 2 2 2 2
VCCSM7 C550 + C531 C532 C500 C114
E1 AF6
VCCDVO_0 VCCSM8 C492 C513 C551
J1 Y7
VCCDVO_1 VCCSM9 10U_0805_10V4Z 0.1U_0402_16V4Z UMA@ 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.01U_0402_16V7K
N1 AA8
VCCDVO_2 VCCSM10 2
150U_D2_6.3VM 2 1
0.1U_0402_16V4Z 1 1 1 UMA@ UMA@ 1 1 UMA@
E4 AB8
VCCDVO_3 VCCSM11 0.1U_0402_16V4Z
J4 Y9
VCCDVO_4 VCCSM12
M4 AF9
C VCCDVO_5 VCCSM13 C
E6 AJ9
VCCDVO_6 VCCSM14
H7 AB10
VCCDVO_7 VCCSM15
J8 AA11
VCCDVO_8 VCCSM16
L8 AB12
VCCDVO_9 VCCSM17 +2.5V
M8 AF12
VCCDVO_10 VCCSM18
N8
VCCDVO_11 VCCSM19
AA13
+1.5VS
W=20mil (90mA) For VCCTXLVDS
R8 AJ13
VCCDVO_12 VCCSM20
K9
VCCDVO_13 VCCSM21
AB14 W=20mil (70mA)
M9 AF15
VCCDVO_14 VCCSM22
+1.5VS
P9
VCCDVO_15 VCCSM23
AB16 For VCCDLVDS 1 2 2 2
AJ17 C542 C523 C545 C515
VCCSM24
AB18 1 2
VCCSM25 C503 0.1U_0402_16V4Z UMA@ 0.1U_0402_16V4Z
A9 AF18
VCCADAC0 VCCSM26 C529 UMA@ 2 UMA@ 1 1 1 UMA@
B9 AB20
VCCADAC1 VCCSM27 22U_1206_16V4Z_V1 22U_1206_16V4Z_V1 0.1U_0402_16V4Z
B8 AF21
+1.5VS VSSADAC VCCSM28 2 1
0.1U_0402_16V4Z
AJ21
VCCSM29
AB22
VCCSM30
A11 AF24
B11
VCCALVDS VCCSM31
AJ25 reserved for GMCH, no need when use external VGA
+1.5VS VSSALVDS VCCSM32
AF27
VCCSM33
AC29
VCCSM34
G13 AF29
VCCDLVDS0 VCCSM35
B14 AG29
VCCDLVDS1 VCCSM36 +2.5V
J13
VCCDLVDS2
B15
VCCDLVDS3 (1.9A)
+2.5V
+2.5V_QSM
F9 1
VCCTXLVDS0
B10 AJ6 2 2 2 2 2 2 2 2 2 2 2 2
VCCTXLVDS1 VCCQSM0 + C558 C581 C573 C546 C566 C562 C534 C528 C508 C563 C543 C510
D10 AJ8
+3VS VCCTXLVDS2 VCCQSM1 +1.35VS_ASM C189
A12
B VCCTXLVDS3 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z B
AD1 2
150U_D2_6.3VM 1 1
0.1U_0402_16V4Z 1 1
0.1U_0402_16V4Z 1 1
0.1U_0402_16V4Z 1 1
0.1U_0402_16V4Z 1 1
0.1U_0402_16V4Z 1 1
0.1U_0402_16V4Z
VCCASM0
A3 AF1
VCCGPIO_0 VCCASM1
A4
VCCGPIO_1

+3VS +VCCP +2.5V_QSM +2.5V +1.35VS_ASM +1.35VS

For VCCGPIO (72mA) W=20mil W=20mil For VCCASM
RG82855GME_uFCBGA732 1 2 1 2
R483 0_0603_5% R506 0_0603_5%
1 For VCCQSM
1 2 2 2 2 2 1 1 1 2
C495 + C499 C493 C497
C501 C505 C584 C575 C591 C582 C590
10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z
2 1
0.1U_0402_16V4Z 2
150U_D2_6.3VM 1 1
0.1U_0402_16V4Z 1 1
0.1U_0402_16V4Z 2 2
10U_0805_10V4Z 2 0.1U_0402_16V4Z
1
R499 1 2 1_0603_1% 10U_0805_10V4Z

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
INTEL 855GME GMCH(4/4)
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
Date: Friday, September 17, 2004 Sheet 9 of 47
5 4 3 2 1
 5 4 3 2 1

1 R589 2 10_0804_8P4R_5% RP44

+2.5V
75_0603_1% DDR_SDQ62 4 5 D DR_DQ62 D DR_DQ60 8 1 DDR_SDQ60
DDR_SDQ56 3 6 D DR_DQ56 D DR_DQ61 7 2 DDR_SDQ61
+2.5V +2.5V +1.25VS_SDREF D DR_SDQS7 2 7 DD R_DQS7 D DR_DM7 6 3 D DR_SDM7
JP24 DDR_SDQ58 1 8 D DR_DQ58 D DR_DQ57 5 4 DDR_SDQ57
1 2
VREF VREF RP45 10_0804_8P4R_5%
3 4

1
VSS VSS 10_0804_8P4R_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DD R_DQ0 5 6 DD R_DQ2 1 1 RP46
DD R_DQ3 DQ0 DQ4 DD R_DQ7 DDR_SDQ63
7 8 C654 C655 R580 4 5 D DR_DQ63 D DR_DQ59 8 1 DDR_SDQ59
DQ1 DQ5 DDR_SDQ50
9 10 75_0603_1% 3 6 D DR_DQ50 D DR_DQ51 7 2 DDR_SDQ51
DD R_DQS0 VDD VDD D DR_DM0 DDR_SDQ55
11 12 2 7 D DR_DQ55 D DR_DQ54 6 3 DDR_SDQ54
DD R_DQ5 DQS0 DM0 DD R_DQ4 2 2 D DR_SDQS6
13 14 1 8 DD R_DQS6 D DR_DM6 5 4 D DR_SDM6

2
DQ2 DQ6
15 16
DD R_DQ1 VSS VSS DD R_DQ6 RP47 10_0804_8P4R_5%
17 18
DD R_DQ8 DQ3 DQ7 DD R_DQ9 10_0804_8P4R_5% RP48
D 19 20 D
DQ8 DQ12 DDR_SDQ49
21 22 4 5 D DR_DQ49 D DR_DQ53 8 1 DDR_SDQ53
D DR_DQ13 VDD VDD D DR_DQ12 DDR_SDQ52
23 24 3 6 D DR_DQ52 D DR_DQ48 7 2 DDR_SDQ48
DD R_DQS1 DQ9 DQ13 D DR_DM1 DDR_SDQ43
25 26 2 7 D DR_DQ43 D DR_DQ46 6 3 DDR_SDQ46
DQS1 DM1 DDR_SDQ42
27 28 1 8 D DR_DQ42 D DR_DQ47 5 4 DDR_SDQ47
D DR_DQ14 VSS VSS D DR_DQ11
29 30
D DR_DQ15 DQ10 DQ14 D DR_DQ10 RP49 10_0804_8P4R_5%
31 32
DQ11 DQ15 10_0804_8P4R_5% RP51
33 34
VDD VDD D DR_SDQS5
<8> D DR_CLK0 A35 36 4 5 DD R_DQS5 D DR_DM5 8 1 D DR_SDM5
CK0_A VDD DDR_SDQ40
<8> DDR_CLK0# A37 38 3 6 D DR_DQ40 D DR_DQ45 7 2 DDR_SDQ45
CK0#_A VSS DDR_SDQ44
39 40 2 7 D DR_DQ44 D DR_DQ41 6 3 DDR_SDQ41
VSS VSS DDR_SDQ34 1 8 D DR_DQ34 D DR_DQ35 5 4 DDR_SDQ35

D DR_DQ16 41 42 D DR_DQ17 RP52 10_0804_8P4R_5%

D DR_DQ20 DQ16 DQ20 D DR_DQ21 10_0804_8P4R_5% RP53
43 44
DQ17 DQ21 DDR_SDQ38
45 46 4 5 D DR_DQ38 D DR_DQ39 8 1 DDR_SDQ39
DD R_DQS2 VDD VDD D DR_DM2 D DR_SDQS4
47 48 3 6 DD R_DQS4 D DR_DM4 7 2 D DR_SDM4
D DR_DQ22 DQS2 DM2 D DR_DQ19 DDR_SDQ37
49 50 2 7 D DR_DQ37 D DR_DQ33 6 3 DDR_SDQ33
DQ18 DQ22 DDR_SDQ32
51 52 1 8 D DR_DQ32 D DR_DQ36 5 4 DDR_SDQ36
D DR_DQ18 VSS VSS D DR_DQ23
53 54
D DR_DQ24 DQ19 DQ23 D DR_DQ28 RP54 10_0804_8P4R_5%
55 56
DQ24 DQ28
57 58
D DR_DQ25 VDD VDD D DR_DQ29
59 60
DD R_DQS3 DQ25 DQ29 D DR_DM3
61 62
DQS3 DM3
63 64
D DR_DQ26 VSS VSS D DR_DQ30 RP16 RP55
65 66
D DR_DQ27 DQ26 DQ30 D DR_DQ31 DD R_SWE# DD R_F_SWE# D DR_SCAS#
67 68 1 8 1 8 D DR_F_SCAS#
DQ27 DQ31 DDR_SMA10 DDR_F_SMA10 D DR_SRAS#
69 70 2 7 2 7 D DR_F_SRAS#
VDD VDD DDR_SBS1 DDR_F_SBS1
3 6 3 6
DDR_SBS0 4 5 DDR_F_SBS0 DDR_SMA0 4 5 DDR_F_SMA0

85 86 10_0804_8P4R_5% 10_0804_8P4R_5%
C DU DU/RESET# C
87 88
VSS VSS
A89 90
CK2_A VSS
A91 92
CK2#_A VDD
93 94
DD R_CKE1 VDD VDD DD R_CKE0 RP19 RP56
<8,11> DD R_CKE1 A95 A96 DD R_CKE0 <8,11>
CKE1_A CKE0_A DDR_SMA3 DDR_F_SMA3 DDR_SMA6 DDR_F_SMA6
A97 98 1 8 1 8
DDR_F_SMA12 DU/A13_A DU/BA2 DDR_F_SMA11 DDR_SMA7 DDR_F_SMA7
A99 A100 2 7 2 7
DDR_F_SMA9 A12_A A11_A DDR_F_SMA8 DDR_SMA9 DDR_F_SMA9 DDR_SMA8 DDR_F_SMA8
A101 A102 3 6 3 6
A9_A A8_A DDR_SMA12 DDR_F_SMA12 DDR_SMA11 DDR_F_SMA11
103 104 4 5 4 5
DDR_F_SMA7 VSS VSS DDR_F_SMA6
A105 A106
DDR_SMA5 A7_A A6_A DDR_SMA4 10_0804_8P4R_5% 10_0804_8P4R_5%
<8,11> DDR_SMA5 A107 A108 DDR_SMA4 <8,11>
DDR_F_SMA3 A5_A A4_A DDR_SMA2
A109 A110 DDR_SMA2 <8,11>
DDR_SMA1 A3_A A2_A DDR_F_SMA0 10_0804_8P4R_5% RP57
<8,11> DDR_SMA1 A111 A112
A1_A A0_A DDR_SDQ27
113 114 4 5 D DR_DQ27 D DR_DQ31 8 1 DDR_SDQ31
DDR_F_SMA10 VDD VDD DDR_F_SBS1 DDR_SDQ26
A115 A116 3 6 D DR_DQ26 D DR_DQ30 7 2 DDR_SDQ30
DDR_F_SBS0 A10/AP_A BA1_A D DR_F_SRAS# D DR_SDQS3
A117 A118 2 7 DD R_DQS3 D DR_DM3 6 3 D DR_SDM3
DD R_F_SWE# BA0_A RAS#_A D DR_F_SCAS# DDR_SDQ25
A119 A120 1 8 D DR_DQ25 D DR_DQ29 5 4 DDR_SDQ29
D DR_SCS#0 WE#_A CAS#_A D DR_SCS#1
<8,11> D DR_SCS#0 A121 A122 D DR_SCS#1 <8,11>
S0#_A S1#_A RP58 10_0804_8P4R_5%
123 124
DU DU 10_0804_8P4R_5% RP59
125 126
D DR_DQ32 VSS VSS D DR_DQ36 DDR_SDQ24
127 128 4 5 D DR_DQ24 D DR_DQ28 8 1 DDR_SDQ28
D DR_DQ37 DQ32 DQ36 D DR_DQ33 DDR_SDQ18
129 130 3 6 D DR_DQ18 D DR_DQ23 7 2 DDR_SDQ23
DQ33 DQ37 DDR_SDQ22
131 132 2 7 D DR_DQ22 D DR_DQ19 6 3 DDR_SDQ19
DD R_DQS4 VDD VDD D DR_DM4 D DR_SDQS2
133 134 1 8 DD R_DQS2 D DR_DM2 5 4 D DR_SDM2
D DR_DQ38 DQS4 DM4 D DR_DQ39
135 136
DQ34 DQ38 RP60 10_0804_8P4R_5%
137 138
D DR_DQ34 VSS VSS D DR_DQ35
139 140
D DR_DQ44 DQ35 DQ39 D DR_DQ41 DDR_SDQ20
141 142 1 2 D DR_DQ20 D DR_DQ21 2 1 DDR_SDQ21
DQ40 DQ44 R537 10_0402_5% 10_0402_5% R536
143 144
D DR_DQ40 VDD VDD D DR_DQ45 DDR_SDQ16 1
145 146 2 D DR_DQ16 D DR_DQ17 2 1 DDR_SDQ17
DD R_DQS5 DQ41 DQ45 D DR_DM5 R545 10_0402_5% 10_0402_5% R542
147 148
DQS5 DM5 DDR_SDQ15 1
B 149 150 2 D DR_DQ15 D DR_DQ10 2 1 DDR_SDQ10 B
D DR_DQ42 VSS VSS D DR_DQ47 R559 10_0402_5% 10_0402_5% R558
151 152
D DR_DQ43 DQ42 DQ46 D DR_DQ46 DDR_SDQ14 1
153 154 2 D DR_DQ14 D DR_DQ11 2 1 DDR_SDQ11
DQ43 DQ47 R565 10_0402_5% 10_0402_5% R564
155 156
VDD VDD
157 A158 DDR_CLK1# <8>
VDD CK1#_A
159 A160 DD R_CLK1 <8>
VSS CK1_A
161 162
D DR_DQ52 VSS VSS D DR_DQ48
163 164
D DR_DQ49 DQ48 DQ52 D DR_DQ53
165 166
DQ49 DQ53
167 168
DD R_DQS6 VDD VDD D DR_DM6
169 170
D DR_DQ55 DQS6 DM6 D DR_DQ54
171 172
DQ50 DQ54 10_0804_8P4R_5% RP61
173 174
D DR_DQ50 VSS VSS D DR_DQ51 D DR_SDQS1
175 176 4 5 DD R_DQS1 D DR_DM1 8 1 D DR_SDM1
D DR_DQ63 DQ51 DQ55 D DR_DQ59 DDR_SDQ13
177 178 3 6 D DR_DQ13 D DR_DQ12 7 2 DDR_SDQ12
DQ56 DQ60 DD R_SDQ8
179 180 2 7 DD R_DQ8 DD R_DQ9 6 3 DD R_SDQ9
D DR_DQ58 VDD VDD D DR_DQ57 DD R_SDQ1
181 182 1 8 DD R_DQ1 DD R_DQ6 5 4 DD R_SDQ6
DD R_DQS7 DQ57 DQ61 D DR_DM7
183 184
DQS7 DM7 RP62 10_0804_8P4R_5%
185 186
D DR_DQ56 VSS VSS D DR_DQ61 10_0804_8P4R_5%
187 188
D DR_DQ62 DQ58 DQ62 D DR_DQ60 DD R_SDQ5
189 190 4 5 DD R_DQ5 RP63
DQ59 DQ63 D DR_SDQS0
191 192 3 6 DD R_DQS0 DD R_DQ4 8 1 DD R_SDQ4
VDD VDD DD R_SDQ3
<12,22> SMB_DATA 193 A194 2 7 DD R_DQ3 D DR_DM0 7 2 D DR_SDM0
SDA SA0_A DD R_SDQ0
<12,22> SMB_CLK 195 A196 1 8 DD R_DQ0 DD R_DQ7 6 3 DD R_SDQ7
SCL SA1_A DD R_DQ2 DD R_SDQ2
197 A198 5 4
+3VS VDD_SPD SA2_A RP64
199 200
VDD_ID DU 10_0804_8P4R_5%
<8> D DR_CLK3 B35 B89
CK0_B CK2_B
<8> DDR_CLK3# B37 B91
DD R_CKE3 CK0#_B CK2#_B DD R_CKE2
<8,11> DD R_CKE3 B95 B96 DD R_CKE2 <8,11>
CKE1_B CKE0_B DDR_SMA11
B97 B100 DDR_SMA11 <8,11>
DDR_SMA12 DU(A13)_B A11_B DDR_SMA8
<8,11> DDR_SMA12 B99 B102 DDR_SMA8 <8,11>
DDR_SMA9 A12_B A8_B DDR_SMA6
A <8,11> DDR_SMA9 B101 B106 DDR_SMA6 <8,11> A
DDR_SMA7 A9_B A6_B DDR_SDQ[0..63] DDR_DQ[0..63]
<8,11> DDR_SMA7 B105 B108 DDR_SMA_B4 <8,11> <8> DDR_SDQ[0..63] DDR_DQ[0..63] <11>
A7_B A4_B
<8,11> DDR_SMA_B5 B107 B110 DDR_SMA_B2 <8,11>
DDR_SMA3 A5_B A2_B DDR_SMA0 DDR_SDM[0..7] D DR_DM[0..7]
<8,11> DDR_SMA3 B109 B112 DDR_SMA0 <8,11> <8> DDR_SDM[0..7] D DR_DM[0..7] <11>
A3_B A0_B DDR_SBS1
<8,11> DDR_SMA_B1 B111 B116 DDR_SBS1 <8,11>
DDR_SMA10 A1_B BA1_B D DR_SRAS# DDR_SDQS[0..7] D DR_DQS[0..7]
<8,11> DDR_SMA10 B115 B118 D DR_SRAS# <8,11> <8> D DR_SDQS[0..7] D DR_DQS[0..7] <11>
DDR_SBS0 A10/AP_B RAS#_B D DR_SCAS#
<8,11> DDR_SBS0 B117 B120 D DR_SCAS# <8,11>
DD R_SWE# BA0_B CAS#_B D DR_SCS#3
B119 B122
<8,11> DD R_SWE#
<8,11> DDR_SCS#2
D DR_SCS#2 B121
WE#_B S1#_B
B194
D DR_SCS#3 <8,11> Compal Electronics, Inc.
S0#_B SA0_B +3VS Title
<8> DDR_CLK4# B158 B196
CK1#_B SA1_B
<8> DD R_CLK4 B160
CK1_B SA2_B
B198
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR-SODIMM
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
QUASA_CA0184-218Y61 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS EAL20 LA-2462
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Friday, September 17, 2004 Sheet 10 of 47
5 4 3 2 1
 A B C D E

+1.25VS
RP5 RP4 DDR_SMA[6..12]
DDR_SMA[6..12] <8,10>
Layout note : DDR_DQ62 1 8 1 8 DDR_DQ60
DDR_DQ56 2 7 2 7 DDR_DQ61 DDR_DQ[0..63]
DDR_DQ[0..63] <10>
Distribute as close as possible DDR_DQS7 3 6 3 6 DDR_DM7
DDR_DQ58 4 5 4 5 DDR_DQ57 DDR_DQS[0..7]
to DDR-SODIMM. DDR_DQS[0..7] <10>
56_0804_8P4R_5% 56_0804_8P4R_5% DDR_DM[0..7]
DDR_DM[0..7] <10>
RP7 RP6
DDR_DQ63 1 8 1 8 DDR_DQ59
+2.5V DDR_DQ50 2 7 2 7 DDR_DQ51
DDR_DQ55 3 6 3 6 DDR_DQ54
DDR_DQS6 4 5 4 5 DDR_DM6
1 1 1 1 1 1 1 1 1
1 56_0804_8P4R_5% 56_0804_8P4R_5% 1
C608 C633 C634 C570 C519 C502 C557 C574 C572
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z RP9 RP8
2 2 2 2 2 2 2 2 2 DDR_DQ49 1 8 1 8 DDR_DQ53
DDR_DQ52 2 7 2 7 DDR_DQ48
DDR_DQ43 3 6 3 6 DDR_DQ46
DDR_DQ42 4 5 4 5 DDR_DQ47

56_0804_8P4R_5% 56_0804_8P4R_5%
+2.5V +2.5V
RP11 RP10
DDR_DQS5 1 8 1 8 DDR_DM5
1 1 1 1 1 1 DDR_DQ40 2 7 2 7 DDR_DQ45
DDR_DQ44 3 6 3 6 DDR_DQ41
C593 C556 C594 C607 + + DDR_DQ34 4 5 4 5 DDR_DQ35
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C118 C215
2 2 2 2 150U_D2_6.3VM 150U_D2_6.3VM 56_0804_8P4R_5% 56_0804_8P4R_5%
2 2
RP13 RP12
DDR_DQ38 1 8 1 8 DDR_DQ39
DDR_DQS4 2 7 2 7 DDR_DM4
DDR_DQ37 3 6 3 6 DDR_DQ33
DDR_DQ32 4 5 4 5 DDR_DQ36

56_0804_8P4R_5% 56_0804_8P4R_5%
Layout note :
Place one cap close to every 2 pull up resistors termination to
+1.25V DDR_SCS#2
<8,10> DDR_SCS#2 1 2 1 2 DDR_SCS#1 DDR_SCS#1 <8,10>
R173 56_0402_5% R169 56_0402_5%
RP15 RP14
2 DDR_ SWE# 8 1 8 1 DDR_SCS#0 2
<8,10> DDR_SWE# DDR_SCS#0 <8,10>
D DR_SMA10 7 2 7 2 DDR_SC AS#
+1.25VS DDR_SCAS# <8,10>
DDR_ SBS0 6 3 6 3 DDR_SCS#3
<8,10> DDR_SBS0 DDR_SCS#3 <8,10>
DDR_SMA_B1 5 4 5 4 DDR_SRAS#
<8,10> DDR_SMA_B1 DDR_SRAS# <8,10>

1 1 1 1 1 1 1 1 56_0804_8P4R_5% 56_0804_8P4R_5%

C185 C202 C144 C141 C136 C200 C199 C175 RP18 RP17
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z DD R_SMA3 8 1 8 1 DDR_SBS1
2 2 2 2 2 2 2 2 <8,10> DDR_SMA3 DDR_SBS1 <8,10>
DDR_SMA_B5 7 2 7 2 DDR_SMA1
<8,10> DDR_SMA_B5 DDR_SMA1 <8,10>
DDR_SMA7 6 3 6 3 DDR_SMA0
DDR_SMA0 <8,10>
DDR_SMA9 5 4 5 4 DDR_SMA2
DDR_SMA2 <8,10>
56_0804_8P4R_5% 56_0804_8P4R_5%
+1.25VS
RP21 RP20
DDR_SMA12 8 1 8 1 DDR_SMA4
DDR_SMA4 <8,10>
1 1 1 1 1 1 1 1 DDR_CKE3 7 2 7 2 DDR_SMA_B4
<8,10> DDR_CKE3 DDR_SMA_B4 <8,10>
DDR_CKE1 6 3 6 3 DDR_SMA6
<8,10> DDR_CKE1
C131 C157 C182 C128 C203 C201 C208 C220 DD R_SMA5 5 4 5 4 DDR_SMA_B2
0.1U_0402_16V4Z <8,10> DDR_SMA5 DDR_SMA_B2 <8,10>
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 56_0804_8P4R_5% 56_0804_8P4R_5%
RP22
8 1 DDR_SMA8
7 2 DDR_SMA11
6 3 DDR_CKE0
+1.25VS DDR_CKE0 <8,10>
5 4 DDR_CKE2
DDR_CKE2 <8,10>
56_0804_8P4R_5%
1 1 1 1 1 1 1 1
C213 C133 C198 C173 C223 C127 C155 C140 RP24 RP23
3 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_DQ27 1 8 1 8 DDR_DQ31 3
2 2 2 2 2 2 2 2 DDR_DQ26 2 7 2 7 DDR_DQ30
DDR_DQS3 3 6 3 6 DDR_DM3
DDR_DQ25 4 5 4 5 DDR_DQ29

56_0804_8P4R_5% 56_0804_8P4R_5%
+1.25VS RP26 RP25
DDR_DQ24 1 8 1 8 DDR_DQ28
DDR_DQ18 2 7 2 7 DDR_DQ23
1 1 1 1 1 1 1 1 DDR_DQ22 3 6 3 6 DDR_DQ19
DDR_DQS2 4 5 4 5 DDR_DM2
C186 C219 C143 C137 C165 C120 C166 C225
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 56_0804_8P4R_5% 56_0804_8P4R_5%
2 2 2 2 2 2 2 2 DDR_DQ20 1 2 1 2 DDR_DQ21
R197 56_0402_5% R196 56_0402_5%
DDR_DQ16 1 2 1 2 DDR_DQ17
R199 56_0402_5% R198 56_0402_5%
DDR_DQ15 1 2 1 2 DDR_DQ10
+1.25VS R206 56_0402_5% R205 56_0402_5%
DDR_DQ14 1 2 1 2 DDR_DQ11
R209 56_0402_5% R207 56_0402_5%
1 1 1 1 1 1 1 1 RP28 RP27
DDR_DQS1 1 8 1 8 DDR_DM1
C150 C207 C178 C159 C123 C124 C121 C134 DDR_DQ13 2 7 2 7 DDR_DQ12
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_DQ8 3 6 3 6 DDR_DQ9
2 2 2 2 2 2 2 2 DDR_DQ1 4 5 4 5 DDR_DQ6

56_0804_8P4R_5% 56_0804_8P4R_5%
RP30 RP29
DDR_DQ5 1 8 1 8 DDR_DQ4
+1.25VS DDR_DQS0 2 7 2 7 DDR_DM0
DDR_DQ3 3 6 3 6 DDR_DQ7
4 DDR_DQ0 DDR_DQ2 4
4 5 4 5
1 1 1 1
56_0804_8P4R_5% 56_0804_8P4R_5%
C227 C230 C224 C228
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR SODIMM Decoupling
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
D ate: Friday, September 17, 2004 Sheet 11 of 47
A B C D E
 A B C D E F G H

Clock Generator
+3VS_CLK
SEL2 SEL1 SEL0 CPUCLKC[0..2] CPUCLKT[0..2]
Width=40 mils 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0 0 0 166.67 166.67 +3VS 2
0_0805_5%
1
L10
0 0 1 100.00 100.00 * 2
0_0805_5%
1
L35
1 1 1 1 1 1 1 1 1 1 1

0 1 0 200.00 200.00 C640 C625 C614 C605 C600 C602 C620 C627 C639 C205 C603
10U_0805_10V4Z
2 2 2 2 2 2 2 2 2 2 2
0 1 1 133.33 133.33 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1

14
19
32
37
46
50
1
8
U46

VDD_PCI_0
VDD_PCI_1

VDD_CPU_0
VDD_CPU_1
VDD_3V66_0
VDD_3V66_1
VDD_REF

VDD_48MHZ
C637 +3VS
10P_0402_50V8K
+3VS +3VS 1 2 XTALIN 2 26 +3V_VDD 1 2
XTAL_IN VDDA L25 0_0805_5%

1
1 1
Y5

1
C599 C595
R571 R573 10U_0805_10V4Z

2
1K_0402_5% 1K_0402_5% 14.318MHZ_16PF_DSX840GA 2 2
@ 1 2 XTALOUT 3 27
C631 XTAL_OUT VSSA 0.1U_0402_16V4Z

2
10P_0402_50V8K 45 CLK_MCH 1 2
CPUCLKT2 CLK_MCH_BCLK <6>
54 R548
SEL0 33_0402_5% R547
55
SEL1 49.9_0402_1%
40 1 2

2
SEL2
1 2

2
R570 R572 R532 R539 R538 49.9_0402_1%
@ 1K_0402_5% 33_0402_5%
1K_0402_5% 25 44 CLK_MCH# 1 2
+3VS <23,34> SLP_S1# PWR_DWN# CPU_CLKC2 CLK_MCH_BCLK# <6>
34
1

1
1K_0402_5% <23> STP_PCI# PCI_STOP# CLK_BCLK
53 49 1 2

1
<23,45> STP_CPU# CPU_STOP# CPUCLKT1 CLK_CPU_BCLK <4>
R557
33_0402_5% R556
2

49.9_0402_1%
1 2
1 2 28 1 2
R498 +3VS R505 10K_0402_5% VTT_PWRGD# R554 R553 49.9_0402_1%
10K_0402_5% 33_0402_5%
2 CLK_ BCLK# 2
48 1 2
1

CLK_CPU_BCLK# <4>
1

D CPUCLKC1
1 2 43
Q38 +3VS R530 10K_0402_5% MULT0 CLK_ITP
1 2 2 52 1 2 CLK_CPU_ITP <4>
<7,23,45> VGATE R496 0_0402_5% G 2N7002_SOT23 CPUCLKT0
R569 R568
S
3

49.9_0402_1%
+VCCP 1 2 29 33_0402_5% 1 2
<10,22> SMB_DATA SDATA
R497 30 1 2
<10,22> SMB_CLK SCLK
@ 56_0402_5% 1 R563 R562 49.9_0402_1%
0.1U_0402_16V4Z

if pull high to +VCCP 33_0402_5%

51 CL K_ITP# 1 2
CPUCLKC0 CLK_CPU_ITP# <4>
Change to DTC124EK C671 33
3V66_0
@ 2 1 2 SSC_66M 35 24
<7> CLK_SSC_66M 3V66_1/VCH_CLK 3V66_5
R508 33_0402_5%

23 MCH_66M 1 2 R509 33_0402_5%

3V66_4 CLK_MCH_66M <7>
R531 1 2 475_0402_1% 42 22 AGP_66M 1 2 R514 33_0402_5% M11@
IREF 3V66_3 CLK_AGP_66M <13>
21 ICH_66M 1 2 R515 33_0402_5%
3V66_2 CLK_ICH_66M <22>

R525 1 2 10_0402_5% CLK_ICH48M 39 7 PCI _ICH 1 2 R560 33_0402_5%

<23> CLK_ICH_48M 48MHZ_USB PCICLK_F2 C LK_PCI_ICH <22>
R524 1 2 10_0402_5% 6
<28> CLK_EXT_SD48 5IN1@ PCICLK_F1
5
PCICLK_F0
1 2 CLK_ MCH48M 38
<7> CLK_MCH_48M R526 33_0402_5% 48MHZ_DOT P CI_MINI
18 1 2 R529 33_0402_5% KS@ CLK_PCI_MINI <30>
PCICLK6
17
PCICLK5 PCI_LPC R534 33_0402_5%
16 1 2 CLK_PCI_LPC <34>
PCICLK4
<23> CLK_ICH_14M
R576 1 2 10_0402_5% CLK_ICH14M 56 13 PCI_SIO 1 2 R543 33_0402_5% SIO@
CLK_PCI_SIO <33>
R575 1 REF PCICLK3 PCI_LAN
2 10_0402_5% SIO@ 12 1 2 R544 33_0402_5%
CLK_PCI_LAN <26>

GND_3V66_0
GND_3V66_1
<33> CLK_14M_SIO PCICLK2

GND_48MHZ
R574 1 2 10_0402_5% @ 11 PCI_1394 1 2 R551 33_0402_5%
GND_PCI_0
GND_PCI_1
PCICLK1 CLK_PCI_1394 <27>

GND_IREF
<31> CLK_14M_CODEC

GND_CPU
GND_REF
10 PCI_PCM 1 2 R552 33_0402_5%
3 PCICLK0 CLK_PCI_PCM <28> 3
4
9
15
20
31
36
41
47
CY28346ZCT-2_TSSOP56

4 4

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock Generator
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
Date: Friday, September 17, 2004 Sheet 12 of 47
A B C D E F G H
 5 4 3 2 1

U 7A

AGP_AD0 H29
M10-P/(M9+X) AJ5 STRAP_G 4M32
<7> AGP_AD0 AD0 GPIO0
<7> AGP_AD1
AGP_AD1
DVOB_D1
H28
AD1 (1/6) GPIO1
AH5 STRAP_H
Samsung: K4D263238E-GC33
J29 AJ4
AD2 GPIO2
<7,19> DVOC_D[0..11]
DVOC_D[0..11] DVOB_D0 J28
AD3 GPIO3
AK4 Hynix: HY5DU283222AF-33
DVOB_D3 K29 AH4
DVOB_D[0..11] DVOB_D2 AD4 GPIO4
<7> DVOB_D[0..11] K28
AD5 GPIO5
AF4 8M32
DVOB_D5 L29 AJ3
AGP_SBA[0..7] DVOB_D4 L28
AD6 GPIO6
AK3
Samsung: K4D553238E-JC33
<7> AGP_SBA[0..7] AD7 GPIO7
DVOB_D6 N28
AD8 GPIO8
AH3 Hynix: HY5DU573222AFM-33
DVOB_D9 P29 AJ2
DVOB_D8 AD9 GPIO9 GPIO10 +3VS
P28 AH2
DVOB_D11 AD10 GPIO10
R29
AD11 GPIO11
AH1 POWER_SEL
CLK_AGP_66M DVOB_D10 R28 AG3
D
<7,19> DVOBC_CLKINT
DVOBC_CLKINT T29 AD12
AD13
GPIO12
GPIO13
AG1
High for 1.0V STRAP_G * R46 1 2 10K_0402_5% M11@
D

AGP_AD14 T28 AG2 Low for 1.2V R42 1 2 10K_0402_5% @

<7> AGP_AD14 * POWER_SEL
1

MDDCDATA AD14 GPIO14 POWER_ SEL

U29 AF3
R383
<7> MDDCDATA
DVO C_ VSYNC N25 AD15 GPIO15
AF2 MCLK_SPREAD
<43>
STRAP_H * R35 1 2 10K_0402_5% M11@

1
10_0402_5% <7,19> DVO C_ VSYNC DVOC_HS YNC R26 AD16 GPIO16 R323 M11@ R41 1 2 10K_0402_5% @
@ <7,19> DVOC_HS YNC AGP_AD18 AD17 VR EFG R317
15mil

ZV PORT / EXT TMDS / GPIO / ROM

<7> AGP_AD18 P25 AG4 2 1 +3VS
D VOC_D0 AD18 VREFG/(NC) 1K_0402_1% 100K_0402_5%
R27
2

1
D VOC_D1 AD19 M11@
1 R25 AF5
D VOC_D2 AD20 ROMCS# R327
T25 Memory Config.

2
C465 D VOC_D3 AD21 STRAP_R 1K_0402_1%
T26 AH6
18P_0402_50V8K D VOC_D4 U25
AD22 ZV_LCDDATA0
AJ6 STRAP_S M11@ GPIO10=High, 128MB
2 @ AD23 ZV_LCDDATA1
D VOC_D7 V27 AK6 STRAP_T GPIO10=Low, 64MB GPIO10 R34 1 2 10K_0402_5% 128M@

2
D VOC_D6 AD24 ZV_LCDDATA2 R36
W26 AH7 1 2 10K_0402_5% 64M@
D VOC_D9 AD25 ZV_LCDDATA3
W25 AK7
D VOC_D8 AD26 ZV_LCDDATA4
Y26 AJ7
R120 2 STP_AGP# DVOC_D11 AD27 ZV_LCDDATA5 STRAP_R
+3VS 1 10K_0402_5% Y25 AH8 R320 1 2 10K_0402_5% 128M@
M11@ DVOC_D10 AD28 ZV_LCDDATA6 R324 1
AA26 AJ8 2 10K_0402_5% 64M@
AGP_AD30 AD29 ZV_LCDDATA7
<7> AGP_AD30 AA25 AH9
AGP_AD31 AD30 ZV_LCDDATA8 STRAP_S R48
<7> AGP_AD31 AA27 AJ9 1 2 10K_0402_5% M11@
AD31 ZV_LCDDATA9 R49
AK9 1 2 10K_0402_5% @
ZV_LCDDATA10
AH10
DVOB_D7 ZV_LCDDATA11 STRAP_T R330 1
N29 AE6 2 10K_0402_5% @
AGP_CBE#1 C/BE#0 ZV_LCDDATA12 R328 1
<7> AGP_CBE#1 U28 AG6 2 10K_0402_5% M11@
AGP_CBE#2 C/BE#1 ZV_LCDDATA13
<7> AGP_CBE#2 P26 AF6
D VOC_D5 C/BE#2 ZV_LCDDATA14
U26 AE7
C/BE#3 ZV_LCDDATA15
<12> CLK_AGP_66M AF7
CLK_AGP_66M ZV_LCDDATA16
AG30 AE8
PCICLK ZV_LCDDATA17
<7,19,22,25,27,28,30> PCIRST#
R382 1 2 0_0805_5% (20mils) NB_PCIRST# AG28 AG8 M11_LCD_DATA <20>
M11@ AGP_REQ# RST# ZV_LCDDATA18
AF28 AF8
<7>
<7>
AGP_REQ#
AGP_GNT#
AG P_GNT# AD26
REQ# ZV_LCDDATA19
AE9
M11_LCD_CLK <20> GPIO10 R S T
AGP_PAR GNT# ZV_LCDDATA20
C <7> AGP_PAR M25
PAR ZV_LCDDATA21
AF9
0 0 0 0 4Mx32 Samsung x4 C
MD DCCLK N26 AG10
<7> MD DCCLK STOP# ZV_LCDDATA22
MI2CDATA V29 AF10 +3VS 4Mx32 Hynix x4
<7,19>
<7>
MI2CDATA
MDVICLK
MDVICLK V28
DEVSEL# ZV_LCDDATA23 * 0 0 1 0
TRDY#

PCI/AGP
MI2CCLK W29 AJ10 ZV_LCDCNTL0 R50 1 2 10K_0402_5% @ 8Mx32 Samsung x4
<7,19>
<7>
MI2CCLK
MDVIDATA
MDVIDATA W28
IRDY#
FRAME#
ZV_LCDCNTL0
ZV_LCDCNTL1
AK10 ZV_LCDCNTL1 R52 1 2 10K_0402_5% @ 1 1 0 0
PCI_PIRQA# AE26 AJ11 ZV_LCDCNTL2 R53 1 2 10K_0402_5% @ 8Mx32 Hynix x4
<22,28> PCI_PIRQA# INTA# ZV_LCDCNTL2
ZV_LCDCNTL3
AH11 ZV_LCDCNTL3 R54 1 2 10K_0402_5% @ 1 1 1 0
AGP_WBF# AC26 4Mx32 Samsung x2 Ch. A
<7> AGP_WBF# WBF#
DVOMODE
AE10 0 0 0 1
STP_AGP# AH30 4Mx32 Hynix x2 Ch. A
<23>
<7,23>
STP_AGP#
AGP_BUSY#
AGP_BUSY# AH29
STP_AGP#
AGP_BUSY#
0 0 1 1
AGP_RBF# AE29
<7> AGP_RBF# RBF#
AG P_ADSTB0 M28 AK16 M11_TXOUT0-
<7> AGP_ADSTB0 AD_STBF_0 TXOUT_L0N M11_TXOUT0- <20>
DVOC_CLK V25 AH16 M11_TXOUT0+
<7,19> DVOC_CLK AD_STBF_1 TXOUT_L0P M11_TXOUT0+ <20>
AG P_ADSTB0# M29 AH17 M11_TXOUT1-
<7> AGP_ADSTB0# AD_STBS_0 TXOUT_L1N M11_TXOUT1- <20>
DVOC_CLK# V26 AJ16 M11_TXOUT1+
<7,19> DVOC_CLK# AD_STBS_1 LVDS TXOUT_L1P
TXOUT_L2N
AH18 M11_TXOUT2- M11_TXOUT1+
M11_TXOUT2-
<20>
<20>
AG P_SBA0 AD28 AJ17 M11_TXOUT2+
AG P_SBA1 SBA0 TXOUT_L2P M11_TXOUT2+ <20>
AD29 AK19
SBA1 TXOUT_L3N +3VS
AGP8X

AG P_SBA2 AC28 AH19

AG P_SBA3 SBA2 TXOUT_L3P M11_TXCLK- X1 M11@
AC29 AK18
AG P_SBA4 SBA3 TXCLK_LN M11_TXCLK+ M11_TXCLK- <20> FREQOUT 1 VGA_XTALIN
AA28 AJ18 4 3 2
AG P_SBA5 SBA4 TXCLK_LP M11_TZOUT0- M11_TXCLK+ <20> R 99 M11@ VDD OUT R119 261_0603_1%
AA29 AG16

1
AG P_SBA6 SBA5 TXOUT_U0N M11_TZOUT0+ M11_TZOUT0- <20>
Y28 AF16 1 2 1 2
AG P_SBA7 SBA6 TXOUT_U0P M11_TZOUT1- M11_TZOUT0+ <20> 10K_0402_5% OE GND
Y29 AG17 1
SBA7 TXOUT_U1N M11_TZOUT1+ M11_TZOUT1- <20> 27MHZ_15P M11@ R118 C87
AF17
AGP_ST0 TXOUT_U1P M11_TZOUT2- M11_TZOUT1+ <20> C61 150_0402_1% @
<7> AGP_ST0 AF29 AF18
AGP_ST1 ST0 TXOUT_U2N M11_TZOUT2+ M11_TZOUT2- <20> 0.1U_0402_16V4Z M11@ 15P_0402_50V8J
<7> AGP_ST1 AD27 AE18

2
AGP_ST2 ST1 TXOUT_U2P M11_TZOUT2+ <20> 2 M11@
<7> AGP_ST2 AE28 AH20
ST2 TXOUT_U3N
AG20
AGP_SBSTB TXOUT_U3P M11_TZCLK-
<7> AGP_SBSTB AB29 AF19
B AGP_SBSTB# SB_STBF TXCLK_UN M11_TZCLK+ M11_TZCLK- <20> B
<7> AGP_SBSTB# AB28 AG19
SB_STBS TXCLK_UP M11_TZCLK+ <20>

+AGP_VREF M26 AE12 ENVDD

AGPREF DIGON ENV DD <20>
1 +1.5VS 1 2 AGPTEST15mil M27 AG12 ENBKL
C440 R380 M11@ 47_0402_1% AGPTEST BLON/(BLON#) ENBKL <34>
M11@ AGP_DBIHI AB25
0.1U_0402_16V4Z AGP_DBILO DBI_HI
AB26 AJ13
2 DBI_LO TX0M
AH14
R369 2 M11@ TX0P
+3VS 1 10K_0402_5% AC25 AJ14
AGP8X_DET# TX1M
AH15
TX1P
AJ15
TX2M
AE11 AK15
R368 1 M11@ AGP_DBIHI DMINUS TX2P
2 1K_0402_5% AF11 AH13
+1.5VS
R377 1 M11@ 2 1K_0402_5% AGP_ DBILO DPLUS THRM TXCM
AK13
TXCP
TMDS

AE13
R2 SET15mil DDC2CLK
1 M11@ 2 AK21 AE14
R359 715_0603_1% R2SET DDC2DATA
R345 1 M11@ 2 100K_0402_5% +3VS
<21> M11_TV_CRMA
AJ23
C_R HPD1
AF12 DDR SPREAD SPECTRUM
AJ22
<21> M11_TV_LUMA Y_G C358 1
AK22 2 0.1U_0402_16V4Z M11@
75_0402_1% R603 COMP_B
AJ24
M11P H2SYNC U 33
AK24 AK27
75_0402_1% R604 V2SYNC R M11_CRT_R <21>
AJ27 7 5
G M11_CRT_G <21> VDD REF
SSC DAC2

M11P AG23 AJ26

75_0402_1% R365 DDC3CLK B M11_CRT_B <21> FREQOUT MCLK_SPREAD
AG24 AG25 1 1 4 2
M11P DDC3DATA HSYNC M11_CRT_HSYNC <21> XIN MODOUT R321 22_0402_5% M11@
AH25
VSYNC M11_CRT_VSYNC <21>
8 1 3 2
RSET XOUT NC
AK25 AH26 1 2 R370 R325 10K_0402_5% @
SSIN RSET M11@ 499_0603_1%
15mil 2
VSS PD#
6 1 2 +3VS
AJ25 AF25 R343 10K_0402_5% @
SSOUT DDC1DATA M11_CRT_DDC_DATA <21> ASM3P1819-SR_SO8 M11@
AF24
DAC1

A A
DDC1CLK M11_CRT_DDC_CLK <21>
Pin3 : Reserved for P1819 Spread Rate selection.
AF26 R372 1 2 10K_0402_5% +3VS
VGA_XTALIN AUXWIN M11@
AH28
XTALIN
CLK

AJ29 B6
XTALOUT TEST_MCLK/(NC)
E8
TEST_YCLK/(NC)
15mil
1 2 TESTEN AH27
TESTEN PLLTEST/(NC)
AE25 Title Compal Electronics, Inc.
R379 M11@ 1K_0402_5%
<23,35> SUS_STAT#
SUS_STAT# AG26 AG29 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI M10-P/M11-AGP/DISPLAY(1/4)
SUS_STAT# RSTB_MSK/(NC) Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Cus tom 0.1
+3VS 2
R373
1
M11@ 10K_0402_5% M11P_BGA708 M11@ R381 2 1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
1K_0402_5% M11@ Date: Friday, September 17, 2004 Sheet 13 of 47
5 4 3 2 1
 5 4 3 2 1

NMDA[0..63] NMDB[0..63]
<17> NMDA[0..63] <18> NMDB[0..63]
NMAA[0 ..13] NMAB[0 ..13]
<17> NMAA[0..13] <18> NMAB[0..13]
NDQMA[0..7] NDQMB[0..7]
<17> NDQMA[0..7] <18> NDQMB[0..7]
NDQSA[0..7] NDQSB[0..7]
<17> NDQSA[0..7] <18> NDQSB[0..7]

D D

U 7B U7C

NMDA0 L25
M10-P/(M9+X) E22 NMAA0 NMDB0 D7
M10-P/(M9+X) N5 NMAB0
DQA0 AA0 DQB0 AB0
NMDA1
NMDA2
L26
DQA1 (2/6) AA1
B22 NMAA1
NMAA2
NMDB1
NMDB2
F7
DQB1 (3/6) AB1
M1 NMAB1
NMAB2
K25 B23 E7 M3
NMDA3 DQA2 AA2 NMAA3 NMDB3 DQB2 AB2 NMAB3
K26 B24 G6 L3
NMDA4 DQA3 AA3 NMAA4 NMDB4 DQB3 AB3 NMAB4
J26 C23 G5 L2
NMDA5 DQA4 AA4 NMAA5 NMDB5 DQB4 AB4 NMAB5
H25 C22 F5 M2
NMDA6 DQA5 AA5 NMAA6 NMDB6 DQB5 AB5 NMAB6
H26 F22 E5 M5
NMDA7 DQA6 AA6 NMAA7 NMDB7 DQB6 AB6 NMAB7
G26 F21 C4 P6
NMDA8 DQA7 AA7 NMAA8 NMDB8 DQB7 AB7 NMAB8
G30 C21 B5 N3
NMDA9 DQA8 AA8 NMAA9 NMDB9 DQB8 AB8 NMAB9
D29 A24 C5 K2
NMDA10 DQA9 AA9 NMAA10 NMDB10 DQB9 AB9 NMAB10
D28 C24 A4 K3
NMDA11 DQA10 AA10 NMAA11 NMDB11 DQB10 AB10 NMAB11
E28 A25 B4 J2
NMDA12 DQA11 AA11 NMAA12 NMDB12 DQB11 AB11 NMAB12
E29 E21 C2 P5
NMDA13 DQA12 AA12/(AA13) NMAA13 NMDB13 DQB12 AB12/(AB13) NMAB13
G29 B20 D3 P3
NMDA14 DQA13 AA13/(AA12) NMDB14 DQB13 AB13/(AB12)
G28 C19 D1 P2
NMDA15 DQA14 AA14/(NC) NMDB15 DQB14 AB14/(NC)
F28 D2
NMDA16 DQA15 NDQMA0 NMDB16 DQB15 NDQMB0
G25 J25 G4 E6
NMDA17 DQA16 DQMA#0 NDQMA1 NMDB17 DQB16 DQMB#0 NDQMB1
F26 F29 H6 B2
DQA17 DQMA#1 DQB17 DQMB#1

MEMORY INTERFACE
NMDA18 E26 E25 NDQMA2 NMDB18 H5 J5 NDQMB2

MEMORY INTERFACE B
NMDA19 DQA18 DQMA#2 NDQMA3 NMDB19 DQB18 DQMB#2 NDQMB3
F25 A27 J6 G3
NMDA20 DQA19 DQMA#3 NDQMA4 NMDB20 DQB19 DQMB#3 NDQMB4
E24 F15 K5 W6
NMDA21 DQA20 DQMA#4 NDQMA5 NMDB21 DQB20 DQMB#4 NDQMB5
F23 C15 K4 W2
NMDA22 DQA21 DQMA#5 NDQMA6 NMDB22 DQB21 DQMB#5 NDQMB6
E23 C11 L6 AC6
NMDA23 DQA22 DQMA#6 NDQMA7 NMDB23 DQB22 DQMB#6 NDQMB7
D22 E11 L5 AD2
NMDA24 DQA23 DQMA#7 NMDB24 DQB23 DQMB#7
B29 G2
NMDA25 DQA24 NMDB25 DQB24 NDQSB0
C29 F3 F6
NMDA26 DQA25 NDQSA0 NMDB26 DQB25 QSB0 NDQSB1
C25 J27 H2 B3
C NMDA27 DQA26 QSA0 NDQSA1 NMDB27 DQB26 QSB1 NDQSB2 C
C27 F30 E2 K6
NMDA28 DQA27 QSA1 NDQSA2 NMDB28 DQB27 QSB2 NDQSB3
B28 F24 F2 G1
NMDA29 DQA28 QSA2 NDQSA3 NMDB29 DQB28 QSB3 NDQSB4
B25 B27 J3 V5
NMDA30 DQA29 QSA3 NDQSA4 NMDB30 DQB29 QSB4 NDQSB5
C26 E16 F1 W1
NMDA31 DQA30 QSA4 NDQSA5 NMDB31 DQB30 QSB5 NDQSB6
B26 B16 H3 AC5
NMDA32 DQA31 QSA5 NDQSA6 NMDB32 DQB31 QSB6 NDQSB7
F17 B11 U6 AD1
NMDA33 DQA32 QSA6 NDQSA7 NMDB33 DQB32 QSB7
E17 F10 U5
A

NMDA34 DQA33 QSA7 NMDB34 DQB33 NMRASB#

D16 U3 R2
NMDA35 DQA34 NMDB35 DQB34 RASB# NMRASB# <18>
F16 V6
NMDA36 DQA35 NMDB36 DQB35 NMCASB#
E15 W5 T5
NMDA37 DQA36 NMRASA# NMDB37 DQB36 CASB# NMCASB# <18>
F14 A19 W4
NMDA38 DQA37 RASA# NMRASA# <17> NMDB38 DQB37 NMWEB#
E14 Y6 T6
NMDA39 DQA38 NMCASA# NMDB39 DQB38 WEB# NMWEB# <18>
F13 E18 Y5
NMDA40 DQA39 CASA# NMCASA# <17> NMDB40 DQB39 NMCSB0#
C17 U2 R5
NMDA41 DQA40 NMWEA# NMDB41 DQB40 CSB0# NMCSB0# <18>
B18 E19 V2
NMDA42 DQA41 WEA# NMWEA# <17> NMDB42 DQB41 NMCSB1#
B17 V1 R6
NMDA43 DQA42 NMCSA0# NMDB43 DQB42 CSB1# NMCSB1# <18>
B15 E20 V3
NMDA44 DQA43 CSA0# NMCSA0# <17> NMDB44 DQB43 NMCKEB
C13 W3 R3
NMDA45 DQA44 NMCSA1# NMDB45 DQB44 CKEB NMCKEB <18>
B14 F20 Y2
NMDA46 DQA45 CSA1# NMCSA1# <17> NMDB46 DQB45 CLKB0 R39 NMCL KB0
C14 Y3 N1 1 M11@ 2 10_0402_5% NMCLKB0 <18>
NMDA47 DQA46 NMCKEA NMDB47 DQB46 CLKB0 CL KB0# R40
C16 B19 AA2 N2 1 M11@ 2 10_0402_5% NMCL KB0#
NMCLKB0# <18>
NMDA48 DQA47 CKEA NMCKEA <17> NMDB48 DQB47 CLKB0#
A13 AA6
NMDA49 DQA48 NMDB49 DQB48 CLKB1 R38 NMCL KB1
A12 AA5 T2 1 M11@ 2 10_0402_5% NMCLKB1 <18>
NMDA50 DQA49 DQB49 CLKB1
C12 B21 CLKA0 R 77 1 M11@ 2 10_0402_5% NMCL KA0 NMCLKA0 <17>
NMDB50 AB6 T3 CL KB1# R37 1 M11@ 2 10_0402_5% NMCL KB1#
NMCLKB1# <18>
NMDA51 DQA50 CLKA0 DQB50 CLKB1#
B12 C20 CL KA0# R 71 1 M11@ 2 10_0402_5% NMCL KA0# NMCLKA0# <17>
NMDB51 AB5
NMDA52 DQA51 CLKA0# NMDB52 DQB51
C10 AD6
NMDA53 DQA52 DQB52 +1.8VS
C9 C18 CLKA1 R 64 1 M11@ 2 10_0402_5% NMCL KA1 NMCLKA1 <17>
NMDB53 AD5
NMDA54 DQA53 CLKA1 DQB53
B9 A18 CL KA1# R 68 1 M11@ 2 10_0402_5% NMCL KA1# NMCLKA1# <17>
NMDB54 AE5 15mil
NMDA55 DQA54 CLKA1# NMDB55 DQB54 MEMVMODE0 R329 1 M11@
B10 AE4 C6 2 4.7K_0402_5%
NMDA56 DQA55 NMDB56 DQB55 MEMVMODE0 MEMVMODE1 R333 1 M11@
E13 D30 AB2 C7 2 4.7K_0402_5%
NMDA57 DQA56 DIMA0 NMDB57 DQB56 MEMVMODE1
E12
DQA57 DIMA1
B13 AB3
DQB57 15mil
B NMDA58 E10 NMDB58 AC2 E3 B
NMDA59 DQA58 NMDB59 DQB58 DIMB0
F12 AC3 AA3
NMDA60 DQA59 MV REFD NMDB60 DQB59 DIMB1
F11 B7 AD3
NMDA61 DQA60 MVREFD NMDB61 DQB60
E9 AE1
NMDA62 DQA61 MVREFS NMDB62 DQB61 MEMTEST R338 1 M11@
F9 B8 AE2 C8 2 47_0402_1%
NMDA63 DQA62 MVREFS/(NC) NMDB63 DQB62 MEMTEST
F8
DQA63
AE3
DQB63 15mil
M11P_BGA708 M11@
M11P_BGA708 M11@

+2.5VS +2.5VS
NMCKEA 1 M11@ 2
R352 10K_0402_5%
1

NMCKEB 1 M11@ 2
R341 R347 R315 10K_0402_5%
M11@ M11@
1K_0402_1% 1K_0402_1%
2

MV REFD MVREFS
20mil 20mil
1

1 1
C362 R339 C368 R349
M11@ M11@
M11@ 1K_0402_1% M11@ 1K_0402_1%
2 2
2

0.1U_0402_16V4Z 0.1U_0402_16V4Z

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI M10-P/M11-MEMORY(2/4)
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Cus tom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
Date: Friday, September 17, 2004 Sheet 14 of 47
5 4 3 2 1
 5 4 3 2 1

+2.5VS U7D +1.5VS

+2.5VS
B1
M10-P/(M9+X)
VDDR1
B30
VDDR1 (4/6)
A15 F18 1 1 1 1 1 1 1
VDDR1 VDDRH0 C418 C420 C431 C430 C459 C458 C461
A21 N6
VDDR1 VDDRH1 M11@ M11@ M11@ M11@ M11@ M11@ M11@
A28
VDDR1 22U_1206_16V4Z_V1 0.1U_0402_16V4Z 0.01U_0402_16V7K
A3
VDDR1 2 2 2 2 2 2 2
0.01U_0402_16V7K
A9 F19
VDDR1 VSSRH0 22U_1206_16V4Z_V1 0.1U_0402_16V4Z 0.01U_0402_16V7K
AA1 M6
VDDR1 VSSRH1
AA4
VDDR1
AA7
VDDR1
D AA8
VDDR1 ATI: 22Ux1, 0.1Ux2, 0.01Ux1, 1000Px1 D
AD4 A7 +VDD_MEMPLL1.8
VDDR1 MPVDD
D5 A6
VDDR1 MPVSS
D8
VDDR1 +3VS +2.5VS
D11
VDDR1
D13
VDDR1 PVDD
AK28 +VDD_PLL1.8 20mil
D14 AJ28
VDDR1 PVSS
D17
VDDR1
D20 1 1 1 1 1 1 1
VDDR1 C403 C421 C366 C357 C363 C355 C426
D23
VDDR1 M11@ M11@ M11@ M11@ M11@ M11@ M11@
D26 AC19 +3VS
VDDR1 VDDR3 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z
E27 AC21
VDDR1 VDDR3 2 2 2 2 2 2 2
F4 AC22
VDDR1 VDDR3 22U_1206_16V4Z_V1 0.1U_0402_16V4Z 0.01U_0402_16V7K 10U_0805_10V4Z
G7 AC8
VDDR1 VDDR3
G10 AD19
VDDR1 VDDR3
G13 AD21
VDDR1 VDDR3
G15 AD22
VDDR1 VDDR3
G19 AD7
VDDR1 VDDR3
G22
VDDR1 +VDD_DAC2.5
G27
VDDR1 L21
H10
VDDR1 20mil, 120mA
H13 AC10 1 2 +2.5VS
VDDR1 VDDR4

I/O POWER
H15 AC9 M11@ CHB1608B121_0603
VDDR1 VDDR4
H17 AD10 1 1
VDDR1 VDDR4 C429 C423
H19 AD9
VDDR1 VDDR4 M11@ M11@
H22 AG7
VDDR1 VDDR4 0.1U_0402_16V4Z
J1
VDDR1 2 2
J23
VDDR1 10U_0805_10V4Z
J24
VDDR1
J4 AA23 +1.5VS
VDDR1 VDDP
J7 AA24
VDDR1 VDDP
J8 AB30
C VDDR1 VDDP C
L27 AC23
VDDR1 VDDP
L8 AC27
VDDR1 VDDP +VDD_PNLIO1.8 +VDD_PLL1.8
M4 AE30
VDDR1 VDDP L19 L22
N4
VDDR1 VDDP
AF27 20mil, 30mA 20mil, 22mA
N7 J30 1 2 +1.8VS 1 2 +1.8VS
VDDR1 VDDP M11@ CHB1608B121_0603 M11@ CHB1608B121_0603
N8 M23
VDDR1 VDDP
R1 M24 1 1 1 1 1 1
VDDR1 VDDP C395 C379 C389 C422 C455 C452
T4 N30
VDDR1 VDDP M11@ M11@ M11@ M11@ M11@ M11@
T7 P23
VDDR1 VDDP 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
T8 P27
VDDR1 VDDP 2 2 2 2 2 2
V4 T23
VDDR1 VDDP 10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z
V7 T24
VDDR1 VDDP
V8 T30
VDDR1 VDDP
D19 U27
VDDR1/(CLKAFB) VDDP
R4 V23
VDDR1/(CLKBFB) VDDP
V24
VDDP
+1.5VS AC11 W30
VDDC15/(VDDC18) VDDP +VDD_PNLPLL1.8 +VDD_DAC1.8
AC20 Y27
VDDC15/(VDDC18) VDDP L7 L20
H11
VDDC15/(VDDC18) change to +2.8V (max:350mA) 20mil, 6mA 20mil, 74mA
H20 1 2 +1.8VS 1 2 +1.8VS
VDDC15/(VDDC18) M11@ CHB1608B121_0603 M11@ CHB1608B121_0603
L23 AE20 +LVDDR25
VDDC15/(VDDC18) LVDDR_25/(LVDDR_18_25)
P8 AE17 1 1 1 1 1
VDDC15/(VDDC18) LVDDR_25/(LVDDR_18_25) C33 C57 C36 C432 C435
Y23 AF21 +VDD_PNLIO1.8
VDDC15/(VDDC18) LVDDR_18 M11@ M11@ M11@ M11@ M11@
Y8 AE15
VDDC15/(VDDC18) LVDDR_18 0.1U_0402_16V4Z 0.1U_0402_16V4Z
AJ20 +VDD_PNLPLL1.8
LPVDD 2 2 2 2 2
10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z
+VDD_PNLPLL1.8 AK12 AF20
TPVDD LVSSR
AJ12 AF15
TPVSS LVSSR
AE19
LVSSR
AE16
B LVSSR B
AJ19
LPVSS +VDD_MEMPLL1.8
+VDD_DAC1.8 AH24
AVDD L6
+VDD_DAC2.5 AG21
A2VDD +LVDDR25
20mil, 6mA
AH21 AE24 +VDD_DAC1.8 1 2 +1.8VS
A2VDD VDD1DI
AF22
A2VDDQ VDD2DI
AE22 20mil, 83mAL18 M11@ CHB1608B121_0603
1 2 +2.5VS 1 1
@ CHB1608B121_0603 C28 C27
AE23 U36 M11@ M11@
VSS1DI 0.1U_0402_16V4Z
AH22 AE21
A2VSSN VSS2DI 2 2
AJ21 5 1 +3VS
A2VSSN VOUT VIN 10U_0805_10V4Z
AF23
A2VSSQ
AF13 1 1 4
TXVDDR C388 C396 PG
AF14
TXVDDR M11@ M11@ 2 3
10U_0805_10V4Z GND EN
AH23
AVSSN 2 2
0.1U_0402_16V4Z
AD24 AG13
AVSSQ TXVSSR MIC5205-2.8BM5_SOT23-5 M11@
AG14
TXVSSR
AH12
TXVSSR
SA052050010(MIC5205-2.8BM5), max:150mA

M11P_BGA708 M11@

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI M10-P/M11-POWER(3/4)
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Cus tom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
Date: Friday, September 17, 2004 Sheet 15 of 47
5 4 3 2 1
 5 4 3 2 1

U 7E U 7F
+VGA_CORE +VGA_CORE
M10-P/(M9+X) M10-P/(M9+X) (+VGA_CORE = 1.2V)
+VGA_CORE
(5/6) M12
VDDC (6/6) VDDC
AD15
A10 M13 AD13
VSS VDDC
A16
VSS VSS
H4 M14
VDDC
M10-P&M9+X VDDC
VDDC
AC17
A2 H8 M17 COMMON AC15
VSS VSS VDDC VDDC

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.01U_0402_16V7K

0.01U_0402_16V7K
+ V DDCI

22U_1206_16V4Z_V1

22U_1206_16V4Z_V1
D A22 H9 M18 AC13 1 1 1 1 1 1 1 1 D
VSS VSS VDDC VDDC L17 C405 C369 C377 C398 C378 C390 C407 C402
A29 H12 M19
VSS VSS VDDC M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@
AA30 H14 N12 T12 1 2 +VGA_CORE
VSS VSS VDDC VDDCI M11@ CHB1608B121_0603
AB1 H18 N13 M15
VSS VSS VDDC VDDCI 2 2 2 2 2 2 2 2
AB23 H21 N14 W16
VSS VSS VDDC VDDCI
AB24 H23 N17 R19

CORE POWER
VSS VSS VDDC VDDCI
AB27 H27 N18
VSS VSS VDDC
AB4 K1 N19
VSS VSS VDDC
AB7 K23 P12 R12
VSS VSS VDDC VSS
AB8 K24 P13 R13
VSS VSS VDDC VSS
AC12 K27 P14 T13
VSS VSS VDDC VSS
AC14 K30 P17 R14
VSS VSS VDDC VSS
AC16 K7 P18 T14
VSS VSS VDDC VSS
AC18 K8 P19 N15
VSS VSS VDDC VSS +VGA_CORE
AC4 L4 U12 P15
VSS VSS VDDC VSS + V DDCI
CORE POWER
AD12 M30 U13 R15
VSS VSS VDDC VSS
AD16
VSS VSS
M7 U14
VDDC VSS
T15 20mil
AD18 M8 U17 U15
VSS VSS VDDC VSS
AD25 N23 U18 V15 1 1
VSS VSS VDDC VSS

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
AD30 N24 U19 W15 1 1 1
VSS VSS VDDC VSS C370 C401 C394 C701 + + C321
AE27
AG11
VSS VSS
N27
P4
V12
V13
VDDC M10-P VSS
H16
M16 M11@ M11@ M11@ 470U_D2_2.5VM 470U_D2_2.5VM
VSS VSS VDDC VSS
AG15
VSS VSS
R23 V14
VDDC ONLY VSS
N16
2 2 2
@
2 2
M11@
AG18 R24 V17 P16
VSS VSS VDDC VSS
AG22 R30 V18 R16
VSS VSS VDDC VSS
AG27 R7 V19 T16
VSS VSS VDDC VSS
AG5 R8 W12 U16
VSS VSS VDDC VSS
AG9 T1 W13 V16
VSS VSS VDDC VSS
AJ1 T27 W14 R17
VSS VSS VDDC VSS
AJ30 U23 W17 T17
VSS VSS VDDC VSS
AK2 U4 W18 R18
VSS VSS VDDC VSS
AK29 U8 W19 T18
C VSS VSS VDDC VSS C
C1 V30 T19
VSS VSS VSS +2.5VS
C28 W23
VSS VSS
C3 W24
VSS VSS
C30 W27
VSS VSS
D10 W7
VSS VSS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.01U_0402_16V7K

0.01U_0402_16V7K
22U_1206_16V4Z_V1
D12 W8 AB22
VSS VSS VDDC
D15 Y4 AB9 1 1 1 1 1 1
VSS VSS VDDC C391 C349 C359 C380 C365 C450
D18 G9 J10
VSS VSS VDDC M11@ M11@ M11@ M11@ M11@
D21 G12 J12
VSS VSS VDDC M11@
D24 G16 J14
VSS VSS VDDC 2 2 2 2 2 2
D25 G18 J15
VSS VSS VDDC
D27 G21 J16 AA22
VSS VSS VDDC VSS
D4 G24 J17 AA9
VSS VSS VDDC VSS
D6
D9
VSS
J19
J21
VDDC M9+X VSS
J11
J13
VSS VDDC VSS
E4
VSS
K22
VDDC ONLY VSS
J18
F27 K9 J20
VSS VDDC VSS
M22 J22
VDDC VSS +2.5VS
M9 J9
VDDC VSS
P22 L22
M11P_BGA708 M11@ VDDC VSS
P9 L9
VDDC VSS
R22 N22
VDDC VSS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.01U_0402_16V7K

0.01U_0402_16V7K
22U_1206_16V4Z_V1
R9 N9
VDDC VSS
T22 W22 1 1 1 1 1 1
VDDC VSS C337 C453 C393 C451 C338 C406
T9 W9
VDDC VSS M11@ M11@ M11@ M11@ M11@ M11@
U22
VDDC
U9
VDDC 2 2 2 2 2 2
V22
VDDC
V9
VDDC
Y22
VDDC
Y9
B VDDC B

M11@ M11P_BGA708

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI M10-P/M11-POWER/GND(4/4)
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Cus tom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
Date: Friday, September 17, 2004 Sheet 16 of 47
5 4 3 2 1
 5 4 3 2 1

+2.5VS +2.5VS

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C436 C414 C416 C447 C438 C449 C428 C448 C415 C350 C343 C354 C340 C341 C361 C360 C351 C339
M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@
22U_1206_16V4Z_V1
22U_1206_16V4Z_V12 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

D
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z D

NMDA[0..63]
<14> NMDA[0..63]
NMAA[0 ..13]

G10

G10
D10
D11

H10

D10
D11

H10
B11

K10

B11

K10
<14> NMAA[0..13]

F10

F10
J10

J10
G5

G5
D4
D5
D6
D9

H5

D4
D5
D6
D9

H5
B4

E6
E9

K5

B4

E6
E9

K5
F5

F5
J5

J5
NDQMA[0..7] U10 U5
<14> NDQMA[0..7]

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
NDQSA[0..7]
<14> NDQSA[0..7]

NMAA0 N5 B7 NMDA9 NMAA0 N5 B7 NMDA39

NMAA1 A0 DQ0 NMDA10 NMAA1 A0 DQ0 NMDA38
N6 C6 N6 C6
NMAA2 A1 DQ1 NMDA12 NMAA2 A1 DQ1 NMDA37
M6 B6 M6 B6
NMAA3 A2 DQ2 NMDA11 NMAA3 A2 DQ2 NMDA36
N7 B5 N7 B5
NMAA4 A3 DQ3 NMDA15 NMAA4 A3 DQ3 NMDA35
N8 C2 N8 C2
NMAA5 A4 DQ4 NMDA8 NMAA5 A4 DQ4 NMDA34
M9 D3 M9 D3
NMAA6 A5 DQ5 NMDA13 NMAA6 A5 DQ5 NMDA33
N9 D2 N9 D2
NMAA7 A6 DQ6 NMDA14 NMAA7 A6 DQ6 NMDA32
N10 E2 N10 E2
NMAA8 A7 DQ7 NMDA22 NMAA8 A7 DQ7 NMDA51
N11 K13 N11 K13
NMAA9 A8/AP DQ8 NMDA23 NMAA9 A8/AP DQ8 NMDA49
M8 K12 M8 K12
NMAA10 A9 DQ9 NMDA21 NMAA10 A9 DQ9 NMDA50
L6 J13 L6 J13
NMAA11 A10 DQ10 NMDA20 NMAA11 A10 DQ10 NMDA48
M7 J12 M7 J12
NMAA12 A11 DQ11 NMDA18 NMAA12 A11 DQ11 NMDA54
N4 G13 N4 G13
NMAA13 BA0 DQ12 NMDA17 NMAA13 BA0 DQ12 NMDA55
M5 G12 M5 G12
BA1 DQ13 NMDA19 BA1 DQ13 NMDA53
F13 F13
NDQMA1 DQ14 NMDA16 NDQMA4 DQ14 NMDA52
B3 F12 B3 F12
C NDQMA2 DM0 DQ15 NMDA29 NDQMA6 DM0 DQ15 NMDA44 C
H12 F3 H12 F3
+2.5VS NDQMA3 DM1 DQ16 NMDA26 +2.5VS NDQMA5 DM1 DQ16 NMDA46
H3 F2 H3 F2
NDQMA0 DM2 DQ17 NMDA30 NDQMA7 DM2 DQ17 NMDA43
B12 G3 B12 G3
DM3 DQ18 NMDA31 DM3 DQ18 NMDA45
G2 G2
1

1
R80 NDQSA1 DQ19 NMDA27 NDQSA4 DQ19 NMDA42
B2 J3 B2 J3
NDQSA2 DQS0 DQ20 NMDA28 R43 NDQSA6 DQS0 DQ20 NMDA47
H13 J2 H13 J2
M11@ NDQSA3 DQS1 DQ21 NMDA24 M11@ NDQSA5 DQS1 DQ21 NMDA41
H2 K2 H2 K2
1K_0402_1% NDQSA0 DQS2 DQ22 NMDA25 1K_0402_1% NDQSA7 DQS2 DQ22 NMDA40
B13 K3 B13 K3
DQS3 DQ23 NMDA0 DQS3 DQ23 NMDA63
20mil E13 20mil E13
2

2
VR_VREF_1 DQ24 NMDA1 VR_VREF_2 DQ24 NMDA61
N13 D13 N13 D13
VREF DQ25 NMDA2 VREF DQ25 NMDA62
M13 D12 M13 D12
1

1
MCL DQ26 MCL DQ26
1K_0402_1%

1K_0402_1%
R74 2 L9 C13 NMDA3 R47 2 L9 C13 NMDA58
C50 RFU1 DQ27 NMDA5 C24 RFU1 DQ27 NMDA57
M10 B10 M10 B10
M11@ M11@ RFU2 DQ28 NMDA4 M11@ M11@ RFU2 DQ28 NMDA60
B9 B9
NMRASA# DQ29 NMDA6 NMRASA# DQ29 NMDA56
M2 C9 M2 C9
1 <14> NMRASA# NMCASA# RAS# DQ30 NMDA7 1 NMCASA# RAS# DQ30 NMDA59
L2 B8 L2 B8
2

2
<14> NMCASA# NMWEA# CAS# DQ31 NMWEA# CAS# DQ31
L3 L3
0.1U_0402_16V4Z <14> NMWEA# NMCSA0# WE# 0.1U_0402_16V4Z NMCSA0# WE#
N2 N2
<14> NMCSA0# CS# CS#
C3 +2.5VS C3 +2.5VS
NMCKEA VDDQ NMCKEA VDDQ
N12 C5 N12 C5
<14> NMCKEA CKE VDDQ CKE VDDQ
C7 C7
NMCL KA0 VDDQ NMCL KA1 VDDQ
<14> NMCLKA0 M11 C8 <14> NMCLKA1 M11 C8
CK VDDQ CK VDDQ
M12 C10 M12 C10
CK# VDDQ CK# VDDQ
C12 C12
C411 R360 1 M11@ VDDQ VDDQ
2 56.2_0402_1% C4 E3 C342 R322 1 M11@ 2 56.2_0402_1% C4 E3
NC VDDQ NC VDDQ
1 2 C11 E12 1 2 C11 E12
M11@ R355 1 M11@ NC VDDQ NC VDDQ
2 56.2_0402_1% H4 F4 M11@ R319 1 M11@ 2 56.2_0402_1% H4 F4
0.1U_0402_16V4Z NC VDDQ 0.1U_0402_16V4Z NC VDDQ
H11 F11 H11 F11
NC VDDQ NC VDDQ
L12 G4 L12 G4
NMCL KA0# NC VDDQ NMCL KA1# NC VDDQ
<14> NMCLKA0# L13 G11 <14> NMCLKA1# L13 G11
NC VDDQ NC VDDQ
M3 J4 M3 J4
B NMCSA1# NC VDDQ NMCSA1# NC VDDQ B
M4 J11 M4 J11
<14> NMCSA1# NC VDDQ NC VDDQ
N3 K4 N3 K4
NC VDDQ NC VDDQ
K11 K11
VDDQ VDDQ
E7 E7
VSS VSS
E8 D7 E8 D7
VSS VDD VSS VDD
E10 D8 E10 D8
VSS VDD VSS VDD
K6 E4 K6 E4
VSS VDD VSS VDD
K7 E11 K7 E11
VSS VDD VSS VDD
K8 L4 K8 L4
VSS VDD VSS VDD
K9 L7 K9 L7
VSS VDD VSS VDD
L5 L8 L5 L8
VSS VDD VSS VDD
L10 L11 L10 L11
VSS VDD VSS VDD
E5 E5
VSS VSS
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH

VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
HY5DU573222AFM-33_FBGA144 HY5DU573222AFM-33_FBGA144
F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9
M11@ M11@

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA DDR CHANNEL A
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Cus tom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
Date: Friday, September 17, 2004 Sheet 17 of 47
5 4 3 2 1
 5 4 3 2 1

+2.5VS
+2.5VS

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
0.01U_0402_16V7K

0.01U_0402_16V7K
22U_1206_16V4Z_V1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C292 C298 C317 C304 C318 C308 C297 C319 C315 C293 C314 C300 C306 C316 C305 C299 C312 C303
M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@ M11@
22U_1206_16V4Z_V1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.1U_0402_16V4Z

D D

G10

G10
D10
D11

H10

D10
D11

H10
B11

K10

B11

K10
F10

F10
J10

J10
G5

G5
D4
D5
D6
D9

H5

D4
D5
D6
D9

H5
B4

E6
E9

K5

B4

E6
E9

K5
F5

F5
J5

J5
U2 U1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
NMDB[0..63]
<14> NMDB[0..63]
NMAB[0 ..13]
<14> NMAB[0..13]
NMAB0 N5 B7 NMDB7 NMAB0 N5 B7 NMDB38
NDQMB[0..7] NMAB1 A0 DQ0 NMDB4 NMAB1 A0 DQ0 NMDB39
<14> NDQMB[0..7] N6 C6 N6 C6
NMAB2 A1 DQ1 NMDB6 NMAB2 A1 DQ1 NMDB37
M6 B6 M6 B6
NDQSB[0..7] NMAB3 A2 DQ2 NMDB5 NMAB3 A2 DQ2 NMDB36
<14> NDQSB[0..7] N7 B5 N7 B5
NMAB4 A3 DQ3 NMDB0 NMAB4 A3 DQ3 NMDB34
N8 C2 N8 C2
NMAB5 A4 DQ4 NMDB1 NMAB5 A4 DQ4 NMDB35
M9 D3 M9 D3
NMAB6 A5 DQ5 NMDB2 NMAB6 A5 DQ5 NMDB33
N9 D2 N9 D2
NMAB7 A6 DQ6 NMDB3 NMAB7 A6 DQ6 NMDB32
N10 E2 N10 E2
NMAB8 A7 DQ7 NMDB24 NMAB8 A7 DQ7 NMDB63
N11 K13 N11 K13
NMAB9 A8/AP DQ8 NMDB26 NMAB9 A8/AP DQ8 NMDB62
M8 K12 M8 K12
NMAB10 A9 DQ9 NMDB29 NMAB10 A9 DQ9 NMDB60
L6 J13 L6 J13
NMAB11 A10 DQ10 NMDB31 NMAB11 A10 DQ10 NMDB61
M7 J12 M7 J12
NMAB12 A11 DQ11 NMDB30 NMAB12 A11 DQ11 NMDB56
N4 G13 N4 G13
NMAB13 BA0 DQ12 NMDB28 NMAB13 BA0 DQ12 NMDB58
M5 G12 M5 G12
BA1 DQ13 NMDB25 BA1 DQ13 NMDB59
F13 F13
NDQMB0 DQ14 NMDB27 NDQMB4 DQ14 NMDB57
B3 F12 B3 F12
C NDQMB3 DM0 DQ15 NMDB14 NDQMB7 DM0 DQ15 NMDB47 C
H12 F3 H12 F3
+2.5VS NDQMB1 DM1 DQ16 NMDB15 +2.5VS NDQMB5 DM1 DQ16 NMDB45
H3 F2 H3 F2
NDQMB2 DM2 DQ17 NMDB13 NDQMB6 DM2 DQ17 NMDB46
B12 G3 B12 G3
DM3 DQ18 NMDB12 DM3 DQ18 NMDB44
G2 G2
1

1
NDQSB0 DQ19 NMDB9 NDQSB4 DQ19 NMDB40
B2 J3 B2 J3
R13 NDQSB3 DQS0 DQ20 NMDB11 R15 NDQSB7 DQS0 DQ20 NMDB43
H13 J2 H13 J2
M11@ NDQSB1 DQS1 DQ21 NMDB8 M11@ NDQSB5 DQS1 DQ21 NMDB41
H2 K2 H2 K2
1K_0402_1% NDQSB2 DQS2 DQ22 NMDB10 1K_0402_1% NDQSB6 DQS2 DQ22 NMDB42
B13 K3 B13 K3
DQS3 DQ23 NMDB21 DQS3 DQ23 NMDB52
E13 E13
2

2
VR_VREF_3 DQ24 NMDB23 VR_VREF_4 DQ24 NMDB54
20mil N13
VREF DQ25
D13 20mil N13
VREF DQ25
D13
M13 D12 NMDB22 M13 D12 NMDB55
1

1
MCL DQ26 MCL DQ26
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2 L9 C13 NMDB20 2 L9 C13 NMDB53
R17 C9 RFU1 DQ27 NMDB16 R16 C8 RFU1 DQ27 NMDB51
M10 B10 M10 B10
M11@ M11@ RFU2 DQ28 NMDB18 M11@ M11@ RFU2 DQ28 NMDB50
B9 B9
1K_0402_1% NMRASB# DQ29 NMDB17 1K_0402_1% NMRASB# DQ29 NMDB48
M2 C9 M2 C9
1 <14> NMRASB# NMCASB# RAS# DQ30 NMDB19 1 NMCASB# RAS# DQ30 NMDB49
L2 B8 L2 B8
2

2
<14> NMCASB# NMWEB# CAS# DQ31 NMWEB# CAS# DQ31
L3 L3
<14> NMWEB# NMCSB0# WE# NMCSB0# WE#
N2 N2
<14> NMCSB0# CS# CS#
C3 +2.5VS C3 +2.5VS
NMCKEB VDDQ NMCKEB VDDQ
N12 C5 N12 C5
<14> NMCKEB CKE VDDQ CKE VDDQ
C7 C7
NMCL KB0 VDDQ NMCL KB1 VDDQ
<14> NMCLKB0 M11 C8 <14> NMCLKB1 M11 C8
CK VDDQ CK VDDQ
M12 C10 M12 C10
56.2_0402_1% CK# VDDQ 56.2_0402_1% CK# VDDQ
C12 C12
C283 R271 1 M11@ 2 VDDQ C282 R274 1 M11@ 2 VDDQ
C4 E3 C4 E3
NC VDDQ NC VDDQ
1 2 C11 E12 1 2 C11 E12
M11@ NC VDDQ NC VDDQ
1 M11@ 2 H4 F4 M11@ 1 M11@ 2 H4 F4
0.1U_0402_16V4Z R272 56.2_0402_1% NC VDDQ 0.1U_0402_16V4Z R275 56.2_0402_1% NC VDDQ
H11 F11 H11 F11
NC VDDQ NC VDDQ
L12 G4 L12 G4
NMCL KB0# NC VDDQ NMCL KB1# NC VDDQ
<14> NMCLKB0# L13 G11 <14> NMCLKB1# L13 G11
NC VDDQ NC VDDQ
M3 J4 M3 J4
B NMCSB1# NC VDDQ NMCSB1# NC VDDQ B
M4 J11 M4 J11
<14> NMCSB1# NC VDDQ NC VDDQ
N3 K4 N3 K4
NC VDDQ NC VDDQ
K11 K11
VDDQ VDDQ
E7 E7
VSS VSS
E8 D7 E8 D7
VSS VDD VSS VDD
E10 D8 E10 D8
VSS VDD VSS VDD
K6 E4 K6 E4
VSS VDD VSS VDD
K7 E11 K7 E11
VSS VDD VSS VDD
K8 L4 K8 L4
VSS VDD VSS VDD
K9 L7 K9 L7
VSS VDD VSS VDD
L5 L8 L5 L8
VSS VDD VSS VDD
L10 L11 L10 L11
VSS VDD VSS VDD
E5 E5
VSS VSS
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH

VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
HY5DU573222AFM-33_FBGA144 HY5DU573222AFM-33_FBGA144
F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9
M11@ M11@

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA DDR CHANNEL B
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Cus tom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
Date: Friday, September 17, 2004 Sheet 18 of 47
5 4 3 2 1
 A B C D E

TV Encoder
remove this page when use M11P

DVOC_D[0..11]
1 <7,13> DVOC_D[0..11] 1

21
22
24
25
27
28
30
31
U37
DVOC_D11 50 9

NC
NC
NC
NC
NC
NC
NC
NC
DVOC_D10 D11 NC
51
D VOC_D9 D10
52 47
D VOC_D8 D9 BCO
53
D VOC_D7 D8
54 48
D VOC_D6 D7 C/H Sync
55
D VOC_D5 D6 R397 75_0402_1% R605 75_0402_1%
58 36
D VOC_D4 D5 CVBS UMA@ UMA@
59
D VOC_D3 D4 7011_TV_LUMA
60 37 7011_TV_LUMA <21>
D VOC_D2 D3 Y/G
61
D VOC_D1 D2 7 011_TV_CRMA
62 38 7011_TV_CRMA <21>
D VOC_D0 D1 C/R/V
63
D0 R396 75_0402_1% R606 75_0402_1%
39
CVBS/B/U UMA@ UMA@
<7,13> DVOC_CLK# 56
XCLK*
<7,13> DVOC_CLK 57 1 +3VS
XCLK DVDD0
12
DVDD1
2 49
NC DVDD2
R386 UMA@ 0_0402_5% 46 6
<7,13> DVOBC_CLKINT Pout/DET# DGND0 +3VS
11
DGND1
4 64
<7,13> DVO C_ H SYNC H DGND2
5
Q34 <7,13> DVO C_ VSYNC V
45
2N7002_SOT23 DVDDV
<7,13,22,25,27,28,30> PCIRST# 13
RESET* +1.5VS C468 C487 C480 C470 C485 C464
23
2 NC UMA@ UMA@ UMA@ 2
S

3 1 14 29 UMA@ UMA@ UMA@

<7,13> MI2CDATA SD NC
UMA@ 15 20 22U_1206_16V4Z_V1 0.1U_0402_16V4Z 0.1U_0402_16V4Z
Q33 SC NC 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
26
2N7002_SOT23 GPIO1 NC
G

7 32
2

+3VS GPIO1 NC
S

3 1 GPIO0 8
<7,13> MI2CCLK I2C Address = 1110110X GPIO0
UMA@ R393 18 +3VS
@ AVDD0
10 44
+3VS R410 AS AVDD1
G

16
2

UMA@ 10K_0402_5% ISET AGND0

35 17
10K_0402_5% With Wide & Short Trace ISET AGND1
41
R395 AGND2
19 33
NC VDD

XI/FIN
1.5K_0402_5% R391 R398 34
GND0

XO
UMA@ UMA@ 140_0402_1% 3 40
330_0402_5% UMA@ VREF GND1
R404 CH7011A-T_LQFP64

42

43
10K_0402_5% UMA@
UMA@
R394
4.7K_0402_5% +1.5VS
UMA@
Y4
+3VS
1 2
R384 UMA@
10K_0402_1%
UMA@ 14.318MHZ_16PF_DSX840GA
UMA@
C477 UMA@ C471
CH7011_VREF 22P_0402_50V8J 22P_0402_50V8J
+3VS

R385
3 UMA@C469 10K_0402_1% 3
0.1U_0402_16V4Z UMA@ R389
10K_0402_5%
@

GPIO1 GPIO0 Pull High: PAL

Pull Low: NTSC*
UMA@
C472 R388
0.1U_0402_16V4Z 330_0402_5%
UMA@

4 4

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TV Encoder CH7011A
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS EAL20 LA-2462
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Friday, September 17, 2004 Sheet 19 of 47
A B C D E
 5 4 3 2 1

+12VALW
+3VS
LCD CONN.
LCD POWER CIRCUIT VGS(th)= 0.95V,
Width: 40mils

2
ID(max)=2.1A, 1 JP6
D30 INVPWR_B+ 16 1
+ LCDVDD R20 RDS(on)= 0.07OHm C10 +3VS 16 1 INVPWR_B+
100K_0402_5% 2DA C_BRIG <34> DA C_BRIG
DA C_BRIG 17 2 DI SPOFF#
+5VALWP 4.7U_0805_10V4Z INVT_ PWM 17 2 + LCDVDD_LCD
1 <34> INVT_PWM 18 3 1 2

1
D 2 18 3 + L CDVDD
3INVT_ PWM 1 2 +3VS_LCD 19 4 R19 0_1206_5%

1
Q2 R294 0_0805_5% LCD_CLK 19 4 LCD_DATA
2 20 5

2
G SI2302DS_SOT23 SM05_SOT23 20 5
1 21 6
21 6

2
R14 R293 1 S TZCLK- 22 7 TXCLK+

3
C301 TZCLK+ 22 7 TXCLK-
100_0402_5% 100K_0402_5% 23 8
R18 C 15 + L CDVDD 0.1U_0402_16V4Z 23 8
24 9
0.047U_0402_16V7K 2 TZOUT1- 24 9 TXOUT2+
width = 80mil 25 10

1 2

1
D 25 10 D
150K_0402_5% 2 TZOUT1+ 26 11 TXOUT2-

1
26 11

1
D D TZOUT2+ TXOUT1-
27 12
TZOUT2- 27 12 TXOUT1+
2 Q24 2 Q1 1 1 28 13
G 2N7002_SOT23 G 2N7002_SOT23 TZOUT0+ 28 13 TXOUT0-
29 14
C11 C14 TZOUT0- 29 14 TXOUT0+
S S 30 15

3
4.7U_0805_10V4Z 30 15
2
0.1U_0402_16V4Z 2 ACES_87216-3002

1
Q3
DTC124EK_SC59

ENVDD 2 M11_TXOUT0- R266 1 M11@ 2 0_0402_5% TXOUT0-

<13> ENVDD <13> M11_TXOUT0-
M11_TXOUT0+ R267 1 M11@ 2 0_0402_5% TXOUT0+
<13> M11_TXOUT0+
1 2 M11_TXOUT1- R264 1 M11@ 2 0_0402_5% TXOUT1-
<7> G M CH_ENVDD <13> M11_TXOUT1-
R22 UMA@ 0_0402_5% M11_TXOUT1+ R265 1 M11@ 2 0_0402_5% TXOUT1+
<13> M11_TXOUT1+
M11_TXOUT2- R263 1 M11@ 2 0_0402_5% TXOUT2-

3
<13> M11_TXOUT2-
M11_TXOUT2+ R262 1 M11@ 2 0_0402_5% TXOUT2+
<13> M11_TXOUT2+
M11_TXCLK- R261 1 M11@ 2 0_0402_5% TXCLK-
<13> M11_TXCLK-
M11_TXCLK+ R260 1 M11@ 2 0_0402_5% TXCLK+
reserved for GMCH <13>
<13>
M11_TXCLK+
M11_TZOUT0-
M11_TZOUT0- R24 1 M11@ 2 0_0402_5% TZOUT0-
M11_TZOUT0+ R25 1 M11@ 2 0_0402_5% TZOUT0+
INVPWR_B+ + L CDVDD <13> M11_TZOUT0+
M11_TZOUT1- R29 1 M11@ 2 0_0402_5% TZOUT1-
+3VS <13> M11_TZOUT1-
width = 60mil M11_TZOUT1+ R28 1 M11@ 2 0_0402_5% TZOUT1+
<13> M11_TZOUT1+
M11_TZOUT2- R26 1 M11@ 2 0_0402_5% TZOUT2-
<13> M11_TZOUT2-
1 2 M11_TZOUT2+ R27 1 M11@ 2 0_0402_5% TZOUT2+
B+ <13> M11_TZOUT2+

1
L5 CHB2012U170_0805 M11_TZCLK- R31 1 M11@ 2 0_0402_5% TZCLK-
<13> M11_TZCLK-
R21 1 2 1 M11_TZCLK+ R30 1 M11@ 2 0_0402_5% TZCLK+
<13> M11_TZCLK+
4.7K_0402_5% 1 L4 CHB2012U170_0805 C 17 C 18
From EC C16 0.1U_0402_16V4Z R259 1 M11@ 2 0_0402_5% LCD_DATA

2
68P_0402_50V8K 2 <13> M11_LCD_DATA
1 2 DI SPOFF# 10U_0805_10V4Z R32 1 M11@ 2 0_0402_5% LCD_CLK
C <34> B KOFF# 2 <13> M11_LCD_CLK C
D6 RB751V_SOD323

For ATI M11P

GMCH_TXOUT0- R289 1 UMA@ 2 0_0402_5% TXOUT0-

<7> GMCH_TXOUT0-
GMCH_TXOUT0+ R290 1 UMA@ 2 0_0402_5% TXOUT0+
<7> GMCH_TXOUT0+
GMCH_TXOUT1- R287 1 UMA@ 2 0_0402_5% TXOUT1-
<7> GMCH_TXOUT1-
GMCH_TXOUT1+ R288 1 UMA@ 2 0_0402_5% TXOUT1+
<7> GMCH_TXOUT1+
GMCH_TXOUT2- R286 1 UMA@ 2 0_0402_5% TXOUT2-
<7> GMCH_TXOUT2-
GMCH_TXOUT2+ R285 1 UMA@ 2 0_0402_5% TXOUT2+
<7> GMCH_TXOUT2+
GMCH_TXCLK- R284 1 UMA@ 2 0_0402_5% TXCLK-
<7> GMCH_TXCLK-
GMCH_TXCLK+ R283 1 UMA@ 2 0_0402_5% TXCLK+
<7> GMCH_TXCLK+
GMCH_TZOUT0- R309 1 UMA@ 2 0_0402_5% TZOUT0-
<7> GMCH_TZOUT0-
GMCH_TZOUT0+ R308 1 UMA@ 2 0_0402_5% TZOUT0+
<7> GMCH_TZOUT0+
GMCH_TZOUT1- R304 1 UMA@ 2 0_0402_5% TZOUT1-
<7> GMCH_TZOUT1-
GMCH_TZOUT1+ R305 1 UMA@ 2 0_0402_5% TZOUT1+
<7> GMCH_TZOUT1+
GMCH_TZOUT2- R307 1 UMA@ 2 0_0402_5% TZOUT2-
<7> GMCH_TZOUT2-
GMCH_TZOUT2+ R306 1 UMA@ 2 0_0402_5% TZOUT2+
<7> GMCH_TZOUT2+
GMCH_TZCLK- R302 1 UMA@ 2 0_0402_5% TZCLK-
<7> GMCH_TZCLK-
GMCH_TZCLK+ R303 1 UMA@ 2 0_0402_5% TZCLK+
<7> GMCH_TZCLK+

R282 1 UMA@ 2 0_0402_5% LCD_DATA

<7> GMCH_LCD_DATA
R301 1 UMA@ 2 0_0402_5% LCD_CLK
<7> GMCH_LCD_CLK
B B

For GMCH

+3VS

LCD_DATA R424 1 2 2.2K_0402_5%

LCD_CLK R299 1 2 2.2K_0402_5%

A A

Compal Electronics, Inc.

Title
LCD CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Cus tom EAL20 LA-2462
Date: Friday, September 17, 2004 Sheet 20 of 47
5 4 3 2 1
 A B C D E

CRT Connector +5VS +R_CRT_VCC +CRT_VCC

R3,R5,R6,R9,R23,R291 D4 W=40mils

1
reserved for GMCH D1 @ D2 @ D3 @ 2 1 F1
+3VS 1 M11@
2
R11 0_0603_5% RB411D_SOT23 POLYSWITCH_1A
+1.5VS 1 UMA@ 2 1
R4 1 M11@ 2 R12 0_0603_5%
<13> M11_CRT_R
R8 2 M11@ 1 0_0402_5% DAN217_SC59 DAN217_SC59 DAN217_SC59 C2

3
75_0402_1% 0.1U_0402_16V4Z
R5 C RT_R
R12 reserved for GMCH 2
<7> GMCH_CRT_R 1 UMA@ 2
1
R9 2 UMA@ 1 0_0402_5% J P2 1
75_0402_1% FOX_DZ11A91-L7

R7 1 M11@ 2 6
<13> M11_CRT_G
R1 2 M11@ 1 0_0402_5% 11
75_0402_1% 1 2 CRT_R_L 1
R6 1 UMA@ 2 CRT_G L2 7
<7> GMCH_CRT_G
R23 2 UMA@ 1 0_0402_5% FCM2012C-800_0805 12
75_0402_1% 1 2 CRT_G_L 2
L1 8 +3VS
R2 1 M11@ 2 FCM2012C-800_0805 13 +CRT_VCC
<13> M11_CRT_B +3VS
R10 2 M11@ 1 0_0402_5% CRT_B 1 2 CRT_B_L 3
75_0402_1% L3 9
R3 1 UMA@ 2 FCM2012C-800_0805 3.3P for GMCH 14 R241 R240 R243 R257
<7> GMCH_CRT_B DDC_MD2
R291 2 UMA@ 1 0_0402_5% 1 1 1 1 1 1 4

1
2.2K_0402_5%

2.2K_0402_5%

4.7K_0402_5%

4.7K_0402_5%
75_0402_1% 10
C1 C7 C3 C4 C5 C6 15
5
2 2 2 2 2 2
ATi suggest use precision termination

2
2
8P_0402_50V8K 8P_0402_50V8K 8P_0402_50V8K 8P_0402_50V8K

G
8P_0402_50V8K 8P_0402_50V8K
1 2 HSYNC _L 1 3 CRT_DDC_DATA 2 M11@ 1
L12 FCM1608C-121T_0603 0_0402_5% R234 M11_CRT_DDC_DATA <13>

S
+CRT_VCC Q22 2 UMA@ 1

2
C265 VSY NC_L 2N7002_SOT23 0_0402_5% R242 GMCH_CRT_DATA <7>

G
1 2
1 2 2 1 L13 FCM1608C-121T_0603
0.1U_0402_16V4Z R250 10K_0402_5% 1 3 C RT_DDC_CLK 2 M11@ 1
0_0402_5% R248 M11_CRT_DDC_CLK <13>

S
1 1 1 1 1

5
1
U25 C262 C261 C260 C263 C259 Q23 2 UMA@ 1
2N7002_SOT23 0_0402_5% R252 GMCH_CRT_CLK <7>

OE#
P

10P_0402_50V8K

10P_0402_50V8K

68P_0402_50V8K

68P_0402_50V8K
100P_0402_50V8J
1 M11@ 2 CRT_HS YNC2 4 H S Y NC
2 <13> M11_CRT_HSYNC A Y 2 2 2 2 2 2
R246 0_0402_5% R242,R252 reserved for GMCH
1 UMA@ 2 G SN74AHCT1G125GW_SOT353-5 33P for GMCH
<7> G MCH _CRT_HSYNC
R247 0_0402_5%
3

+CRT_VCC

1 2
C266
5
1
0.1U_0402_16V4Z
OE#
P

<13> M11_CRT_VSYNC 1 M11@ 2 CRT_ VSYNC 2 4 V S YNC

R245 0_0402_5% A Y
G

<7> G M CH_CRT_VSYNC 1 UMA@ 2 U 24

R244 0_0402_5% SN74AHCT1G125GW_SOT353-5
3

R247,R244 reserved for GMCH

TV-Out Connector

DAN217_SC59

DAN217_SC59
1

1
D18 @ D17 @

+3VS

3
3 3

R256,R253 reserved for TV encoder S-Video

1 2 @ 47P_0402_50V8J
C272
<13> M11_TV_LUMA 1 M11@ 2 TV_LUMA 1 2 L UMA_L 4P Normal Type
R255 0_0402_5% L15 FCM1608C-121T_0603 JP3
<19> 7011_TV_LUMA 1 UMA@ 2 1
R256 0_0402_5% 1
1 2 @ 47P_0402_50V8J 2 5
C271 2 GND
3 6
TV_CRMA CRMA_L 3 GND
<13> M11_TV_CRMA 1 M11@ 2 1 2 4
R254 0_0402_5% L14 FCM1608C-121T_0603 4

<19> 7011_TV_CRMA 1 UMA@ 2

82P_0402_50V8J

82P_0402_50V8J
R253 0_0402_5% SUYIN_030336FR004T115ZU
1

1
75_0402_1%

75_0402_1%

82P_0402_50V8J

82P_0402_50V8J

R251 R249 1 1 1 1
@ @ C274 C273 C269 C268
2

2 2 2 2

For M11P, Capacitance is 82pF For M11P, Capacitance is 82pF

For CH7011A, Capacitance is 100pF For CH7011A, Capacitance is 270pF

4 4

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT & TV-OUT Connector
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
Date: Friday, September 17, 2004 Sheet 21 of 47
A B C D E
 A B C D

U34A

PCI_AD0 H5
AD0
ICH4 INTRUDER#
W6 INTRUDER#
PCI_AD[0..31] PCI_AD1 J3 AC3 SMLINK0
<26,27,28,30> PCI_AD[0..31] AD1 SMLINK0
PCI_AD2 H3 AB1 SMLINK1
PCI_AD3 AD2 SMLINK1 SMB_CLK
PCI_AD4
K1
G5
AD3 SM I/F SMB_CLK AC4
AB4 SMB_DATA
SMB_CLK <10,12>
AD4 SMB_DATA SMB_DATA <10,12>
PCI_AD5 J4 AA5 2 1
AD5 SMB_ALERT#/GPI11 AC IN <34,36,38>
PCI_AD6 H4 RB751V_SOD323 D29
PCI_AD7 AD6
J5 1 2 +3VALW
1 PCI_AD8 AD7 R101 100K_0402_5% 1
K2
PCI_AD9 AD8
G2 Y22 GATEA20 <34>
CLK_PCI _ICH PCI_AD10 AD9 A20GATE
L1 AB23 H_A20M# <4>
PCI_AD11 AD10 A20M#
G4 U23 H_DPSLP# <4,7>
1
AD11 DPSLP#
PCI_AD12 L2 AA21 1 R133 2 H_FER R#
H_FERR# <4>
R86 PCI_AD13 AD12 FERR# 56_0402_5%
H2 W21 H_IGNNE# <4>
PCI_AD14 AD13 IGNNE#
L3 V22 H_INIT# <4>
@ 10_0402_5% PCI_AD15 AD14 INIT#
PCI_AD16
F5
F4
AD15 CPU I/F INTR
AB22
V21
H_INTR <4>
H_NMI <4>
2

PCI_AD17 AD16 NMI

1 N1 Y23 H_CPUPW RGD <4>
C59 PCI_AD18 AD17 CPU_PWRGOOD +1.5VS
E5 U22 R C# <34>
PCI_AD19 AD18 RCIN#
N2 U21 H_CPUSLP# <4>
@ 15P_0402_50V8J PCI_AD20 AD19 SLP#
E3 W23 H_SMI# <4>
2 PCI_AD21 AD20 SMI# HUB_RCO MP_ICH 1
N3 V23 H_STPCLK# <4> 2
PCI_AD22 AD21 STPCLK# R399 48.7_0402_1%
E4
PCI_AD23 AD22
M5
PCI_AD24 AD23
E2
C LK_ICH_66M PCI_AD25 AD24 HUB_ PD0
P1 L19
PCI_AD26 AD25 HI0 HUB_ PD1 HUB_PD[0..10]
E1 L20 HUB_PD[0..10] <6>
1

PCI_AD27 AD26 HI1 HUB_ PD2

P2 M19
R132 PCI_AD28 AD27 HI2 HUB_ PD3 HUB_VREF
D3 M21 1 2
@ 22_0402_5% PCI_AD29 AD28 HI3 HUB_ PD4 C484 0.01U_0402_16V7K
R1 P19
PCI_AD30 AD29 HI4 HUB_ PD5 HUB_VSWING 1
D2 R19 2
PCI_AD31 AD30 HI5 HUB_ PD6 C482 0.01U_0402_16V7K
P4 T20

PCI I/F
2

AD31 HI6 HUB_ PD7

1 R20
HI7 HUB_ PD8
P23
C95 PCI_CBE#0 HI8 HUB_ PD9
<26,27,28,30> PCI_CBE#0 J2 L22
@10P_0402_50V8K PCI_CBE#1 C/BE#0 HI9 HUB_ PD10 R130
2 <26,27,28,30> PCI_CBE#1
PCI_CBE#2
K4
M4
C/BE#1 HUB I/F HI10
N22
K21 1 2 56_0402_5%
<26,27,28,30> PCI_CBE#2 C/BE#2 HI11
PCI_CBE#3 N4
<26,27,28,30> PCI_CBE#3 C/BE#3
T21 CLK_ICH_66M
CLK66 CLK_ICH_66M <12>
PCI_REQ#0 B1 +3VS
2 <27> PCI_REQ#0 REQ#0 2
PCI_REQ#1 A2 P21
<26> PCI_REQ#1 REQ#1 HI_STB HUB_PSTRB <6>
PCI_REQ#2 B3 N20
<28> PCI_REQ#2 REQ#2 HI_STB# HUB_PSTRB# <6>
PCI_REQ#3 C7 SMB_CLK 1 2
<30> PCI_REQ#3 REQ#3
PCI_REQ#4 B6 R23 HUB_RCO MP_ICH R69
<30> PCI_REQ#4 REQ#4 HICOMP
M23 HUB_VR EF 10K_0402_5%
HUB_VREF HUB_VREF
PCI_GNT#0 C1 R22 HUB_VSWING SMB_DATA 1 2
<27> PCI_GNT#0 GNT#0 HUB_VSWING HUB_VSWING
PCI_GNT#1 E6 R73
<26> PCI_GNT#1 GNT#1
PCI_GNT#2 A7 10K_0402_5%
<28> PCI_GNT#2 GNT#2
PCI_GNT#3 B7 J19 APICCLK
<30> PCI_GNT#3 GNT#3 APICCLK
PCI_GNT#4 D6 H19 APICD0
PCI Pullups <30> PCI_GNT#4 GNT#4 APICD0
K20 APICD1
APICD1

Interrupt I/F
CLK_PCI _ICH P5 D5 PCI_ PIRQA#
<12> CLK_PCI_ICH PCICLK PIRQA# PCI_PIRQA# <13,28>
C2 PCI_ PIRQB#
+3VS PIRQB# PCI_PIRQB# <28>
PC I_FRAME# F1 B4 PCI_PIRQC#
8.2K_1206_8P4R_5% <26,27,28,30> PCI_FRAME# FRAME# PIRQC#
PCI_DEVSEL# M3 A3 PCI_PIRQD#
<26,27,28,30> PCI_DEVSEL# DEVSEL# PIRQD#
4 5 PCI_REQ#2 PC I_IRDY# L5 C8 PCI_ PIRQE#
<26,27,28,30> PC I_IRDY# IRDY# PIRQE#/GPI2 PCI_PIRQE# <27>
3 6 PCI_PIRQD# G1 D7 PCI_PIRQF#
<26,27,28,30> PCI_PAR PAR PIRQF#/GPI3 PCI_PIRQF# <26>
4 2 7 PCI_PIRQH# PCI_PERR# L4 C3 PCI_ PIRQG#
<26,27,28,30> PCI_PERR# PERR# PIRQG#/GPI4 PCI_PIRQG# <30>
1 8 PCI_PIRQC# PCI_LOCK# M2 C4 PCI_PIRQH#
LOCK# PIRQH#/GPI5 PCI_PIRQH# <30>
W2 AC13 PD_ IRQ14
RP40 PME# IRQ14 PD_IRQ14 <25>
PCIRST# U5 AA19 SD_ IRQ15
<7,13,19,25,27,28,30> PCIRST# PCIRST# IRQ15 SD_IRQ15 <25>
PCI_SERR# K5 J22 SIRQ
8.2K_1206_8P4R_5% <26,28,30> PCI_SERR# SERR# SERIRQ SIRQ <28,33,34>
PCI_STOP# F3
<26,27,28,30> PCI_STOP# STOP#
4 5 PCI_LOCK# PCI_TRDY# F2
<26,27,28,30> PCI_TRDY# TRDY#
3 6 PCI_DEVSEL# D10
PCI_PERR# PCI_REQA# EE_CS
1 2 7 B5
REQA#/GPI0 EEPROM I/F EE_IN
D11
1 8 PC I_IRDY# PCI_REQB# A6 A8 1 2
PIDERST# REQB#/GPI1/REQ5# EE_OUT
<25> PIDERST# E8 C12
RP37 SIDERST# GNTA#/GPO16 EE_SHCLK R96
<25> SIDERST# C5
GNTB#/GPO17/GNT5# @ 1K_0402_5%
8.2K_1206_8P4R_5% A10
PCI_PIRQF# LAN_RXD0
4 5 A9
3 PCI_REQ#3 LAN_RXD1 3
3 6 A11
PCI_ PIRQE# LAN_RXD2
6 2
1
7
8
LAN_TXD0
B10
C10 +RTCVCC

RP42
LAN I/F LAN_TXD1
LAN_TXD2
A12
C11 INTRUDER# 1 2
LAN_CLK
B11 R85
8.2K_1206_8P4R_5% LAN_RSTSYNC 330K_0402_5%
Y5 1 2
PCI_SERR# LAN_RST#
4 5
3 6 PCI_FRAME# R72
PCI_TRDY# 10K_0402_5%
2 2
1
7
8 PCI_STOP# FW82801DBM_BGA421
+VCCP
RP38
H_FER R# 1 2
8.2K_1206_8P4R_5%
R126
4 5 PCI_PIRQG# 56_0402_5%
3 6 PCI_PIRQB#
PCI_REQ#0 +3VS
3 2
1
7
8 PCI_REQ#1

RP39 +3VALW
5

2 1 PD_ IRQ14 U32

R376 SMLINK0 R87
1 2
OE#
P

8.2K_0402_5% PCIRST# 2 4 APIC CLK 4.7K_0402_5%

I O B_PCIRST# <26,33,34>
2 1 SD_ IRQ15 APIC D0
G

R129 APIC D1 SMLINK1 R83

1 2
8.2K_0402_5% @ 74LVC1G125GW_SOT3535 4.7K_0402_5%
3

2
RP41
8 1 PCI_PIRQA# R124 R122 R123
7 2 PCI_REQA# 10K_0402_5% 10K_0402_5% 0_0402_5%
PCI_REQ#4
5 6 3

1
4 PCI_REQB# 4
5 4
1 2
8.2K_1206_8P4R_5% R331 0_0402_5%

2 1 SIRQ
R400
8.2K_0402_5%

Compal Electronics, Inc.

Title
PIDERST#
1
R97
2
@ 1K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH4-M(1/3) PCI/HUB/CPU/INT
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
D ate: Friday, September 17, 2004 Sheet 22 of 47
A B C D
 A B C D

+3VS

1
R337

10K_0402_5%
1 2 PM_DPRSLPVR

2
R131 100K_0402_5% U34B

<7,13> AGP_BUSY#
AGP_ BUSY# R2
AGPBUSY#
ICH4 GPI7
R3
1 SYSR ST# Y3 V4 EC_SMI# 1
+3VS <4> ITP_DBRESET# PM_BATLOW# SYSRST# GPI8 SCI# EC_SMI# <34> +3VALW
<34> PM_BATLOW# AB2 V5 SCI# <34>
C3_STAT# BATLOW# GPI12 EC _LID_OUT#
<13> STP_AGP#
T3 W3 EC_LID_OUT# <34>
PM_ CLKRUN# AC2 C3_STAT# GPI13
GPIO

14
<26,30,33,34> PM_CLKRUN# V2 EC_FLASH# <35>
LPC _DRQ#0 PM_DPRSLPVR V20 CLKRUN# GPIO25 U16D
2 1 <45> PM_DPRSLPVR W1
R63 10K_0402_5% DPRSLPVR GPIO27 SLP_S4#
AA1 W4 12

P
<34> PWRBTN_OUT# PWRBTN# GPIO28 A
+3VS AB6 11 PM_SLP_S5# <34>
<36,45> PM_POK EC_ RIOUT# PWROK SLP_S5# O
<34> EC_RIOUT#
Y1 13
RI# B

G
PM_RSMRST# AA6 PM
PM_ CLKRUN# <34> PM_RSMRST# RSMRST# PD_A0
2 1 W18 AA13 PD_A0 <25>

7
R67 10K_0402_5% <12,34> SLP_S1# SLP_S1# PDA0 PD_A1 SN74LVC08APW_TSSOP14
<34> SLP_S3# Y4 AB13 PD_A1 <25>
SLP_S4# SLP_S3# PDA1 PD_A2
Y2 W13 PD_A2 <25>
SLP_S5# SLP_S4# PDA2 PD _CS#1
AA2 Y13 PD_CS#1 <25>
PM_RSMRST# SLP_S5# PDCS1# PD _CS#3
2 1 <12,45> STP_CPU# W19 AB14 PD_CS#3 <25>
R78 10K_0402_5% STP_CPU# PDCS3#
<12> STP_PCI# Y21
RTC CLK STP_PCI# PD_DR EQ
<7> RTCCLK AA4 AA11 PD_DREQ <25>
SUS_STAT# SUS_CLK PDDREQ PD_D ACK#
<13,35> SUS_STAT# AB3 Y12 PD_DACK# <25>
RTC CLK EC_THRM# SUS_STAT#/LPCPD# PDDACK# PD_ IOR# PD_D[ 0..15]
1 2 <34> EC_THRM# V1 AC12 PD_IOR# <25> PD_D[0..15] <25>
R70 @ 10K_0402_5% THRM# PDIOR# PD _IOW#
W12 PD_IOW# <25>
PDIOW# P D_PIORDY
+3VS 1 2 AB12 P D_PIORDY <25>
R335 8.2K_0402_5% PIORDY SD_D[ 0..15]
SD_D[0..15] <25>
J21 AB11 PD_ D0
CPUPERF# SSMUXSEL PDD0 PD_ D1
Y20
V19
CPUPERF# IST PDD1
AC11
Y10 PD_ D2
<7,12,45> VGATE VGATE/VRMPWRGD PDD2 PD_ D3
AA10
+VCCP PDD3 PD_ D4
AC97_BITCLK B8
AC97 I/F PDD4
AA7
AB8 PD_ D5
<31> AC97_BITCLK AC_BITCLK PDD5 PD_ D6 C LK_ICH_14M
<31> AC97_RST# C13 Y8
CPUPERF# AC97 _SDIN0 AC_RST# PDD6 PD_ D7
1 2 <31> AC97_SDIN0 D13 IDE I/F AA8

1
R125 AC97 _SDIN1 AC_SDATAIN0 PDD7 PD_ D8
<31> AC97_SDIN1 A13 AB9
8.2K_0402_5% AC_SDATAIN1 PDD8 PD_ D9
B13 Y9
ICH_AC_SDOUT AC_SDATAIN2 PDD9 PD _D10 R402
D9 AC9
2 IC H_AC_SYNC AC_SDATAOUT PDD10 PD _D11 @ 22_0402_5% 2
C9 W9
AC_SYNC PDD11 PD _D12
AB10

2
+3VS PDD12 PD _D13
W10 1
LPC_AD0 PDD13 PD _D14
<33,34> LPC_AD0
T2 W11
LPC_AD1 LPC_AD0 PDD14 PD _D15 C486
<33,34> LPC_AD1 R4 Y11
R408 LPC_AD2 LPC_AD1 PDD15 @ 10P_0402_50V8K
<33,34> LPC_AD2 T4
SB_SPKR LPC_AD3 LPC_AD2 SD_A0 2
1 2
@ 1K_0402_5% <33,34> LPC_AD3 LPC _DRQ#0
U2
U3
LPC_AD3 LPC I/F SDA0
AA20
AC20 SD_A1
SD_A0 <25>
LPC_DRQ#0 SDA1 SD_A1 <25>
+3VS <33> LPC_DRQ#1 LPC _DRQ#1 U4 AC21 SD_A2
LPC_DRQ#1 SDA2 SD_A2 <25>
L PC_FRAME# T5 AB21 SD _CS#1
<33,34> LPC_FRAME# LPC_FRAME# SDCS1# SD_CS#1 <25>
AC22 SD _CS#3
SDCS3# SD_CS#3 <25>
C LK_ICH_48M
2 R100 1 ICH_AC_SDOUT AB18 SD_DR EQ
SD_DREQ <25>

1
@ 10K_0402_5% SDDREQ SD_D ACK#
C20 AB19 SD_DACK# <25>
+3VS USBP0+ SDDACK# SD_ IOR# R128
D20 Y18 SD_IOR# <25>
USBP0- SDIOR# SD _IOW# 22_0402_5%
A21 AA18 SD_IOW# <25>
USBP1+ SDIOW# S D_SIORDY @
B21 AC19 S D_SIORDY <25>
USBP1- SIORDY
<35> USB20P2+ C18

2
USBP2+
2 R336 1 AGP_ BUSY#
<35> USB20P2- D18 W17 SD_ D0 1
10K_0402_5% USBP2- SDD0 SD_ D1
<35> USB20P3+ A19 AB17
USBP3+ SDD1 SD_ D2 C101
<35> USB20P3- B19 W16
USBP3- SDD2 SD_ D3 @ 10P_0402_50V8K
<35> USB20P4+ C16 AC16
+3VALW USBP4+ SDD3 SD_ D4 2
<35> USB20P4- D16 W15
USBP4- SDD4 SD_ D5
A17 AB15
RP43 USBP5+ SDD5 SD_ D6
B17
USBP5- USB I/F SDD6
W14
AA14 SD_ D7
OVCUR#1 SDD7 SD_ D8
1 8 Y14
OVCUR#0 OVCUR#0 SDD8 SD_ D9
2 7 B15 AC15
OVCUR#5 OVCUR#1 OC#0 SDD9 SD _D10
3 6 C14 AA15
OVCUR#2 OC#1 SDD10 SD _D11
4 5 <35> OVCUR#2 A15 Y15
OVCUR#3 OC#2 SDD11 SD _D12
<35> OVCUR#3 B14 AB16
10K_1206_8P4R_5% OVCUR#4 OC#3 SDD12 SD _D13 +RTCVCC
<35> OVCUR#4 A14 Y16
3 OVCUR#5 OC#4 SDD13 SD _D14 3
D14 AA17
OC#5 SDD14
1 2 EC_LID_OUT# Y17 SD _D15
R89 10K_0402_5% USB_ RBIAS SDD15
A23
USB_RBIAS
1 2 PM_BATLOW# 2 R403 1 B23 1 2
R90 10K_0402_5% USB_RBIAS# R91
22.6_0402_1% 1
1 2 SCI# J23 C LK_ICH_14M R579 180K_0402_5%
CLK14 CLK_ICH_14M <12>
R98 10K_0402_5% F19 C LK_ICH_48M 2 1 2 1 C55
CLK48 CLK_ICH_48M <12>
J20 0.1U_0402_16V4Z
GPIO32 RTC_RST# J1 1K_0402_5% 2
G22 W7
GPIO33 RTCRST# JOPEN
F20
GPIO34 VBIAS
G20 CLOCK Y6 1 2R_VBIAS 1 2
GPIO35 VBIAS R79
F21
GPIO36 RTCX1 C381 1K_0402_5%
H20 AC7
GPIO37 RTCX1 0.047U_0603_16V7K
F23
GPIO38 RTCX2
H22
G23
GPIO39 GPIO RTCX2
AC6 1
R354
2
GPIO40 10M_0402_5%
H21
GPIO41 10M_0402_5%
F22 H23 SB_SPKR SB_SPKR <31>
GPIO42 SPKR
E23 1 2 2 1
GPIO43 R351 R350
MISC THRMTRIP# W20 THRMTRIP# THRMTRIP# <4>

2
1 1 @ 22M_0603_5%

1
C400 C417 R346
15P_0402_50V8J 15P_0402_50V8J @ 2.4M_0603_1%

OUT

IN
FW82801DBM_BGA421 2 2

1
NC

NC
R102
0_0402_5%

2
1 2 IC H_AC_SYNC Y3
<31> AC97_SYNC
32.768KHZ_12.5P_1TJS125DJ2A073
4 ICH_AC_ SDOUT 4
<31> AC97_SDOUT 1 2
1 1 R107
0_0402_5%
C66 C70
22P_0402_50V8J @ @ 22P_0402_50V8J
2 2

Compal Electronics, Inc.

Title

ICH4-M(2/3) PM/AC97/USB/IDE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
D ate: Friday, September 17, 2004 Sheet 23 of 47
A B C D
 A B C D E F G H

U34C +3VS

D22
VSS0
ICH4 VCC3.3_0
A5
E10 AC17 +3VS +1.5VALW +3VS
VSS1 VCC3.3_1
E14 AC8
VSS2 VCC3.3_2 10U_0805_10V4Z 1U_0603_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
E16 B2
VSS3 VCC3.3_3
E17 H18
VSS4 VCC3.3_4
E18 H6 1 1 1 1 1 1 1 1 1 1 1 1 1
VSS5 VCC3.3_5 C466 C353 C352 C99 C65 C49 C35 C46 C91
E19 J1
VSS6 VCC3.3_6 C72 C98 C90 C48
E21 J18
VSS7 VCC3.3_7

0.1U_0402_16V4Z

0.1U_0402_16V4Z
E22 K6
1 VSS8 VCC3.3_8 2 2 2 2 2 2 2 2 2 2 2 2 2 1
F8 M10
VSS9 VCC3.3_9
G19 P12
VSS10 VCC3.3_10 1U_0603_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
G21 P6
VSS11 VCC3.3_11
G3 U1
VSS12 VCC3.3_12
G6 V10
VSS13 VCC3.3_13
H1 V16
VSS14 VCC3.3_14
J6 V18
VSS15 VCC3.3_15 +3VALW
K11
VSS16 +1.5VS +1.5VS +1.5VS
K13
VSS17
K19 E11
VSS18 VCCSUS3.3_0
K23 F10
VSS19 VCCSUS3.3_1
K3 F15
VSS20 VCCSUS3.3_2
L10 F16 1 1 1 1 1 1
VSS21 VCCSUS3.3_3
L11 F17
VSS22 VCCSUS3.3_4 C84 C73 C68 C56 C67 C85
L12 F18
VSS23 VCCSUS3.3_5 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K
L13 K14
VSS24 VCCSUS3.3_6 2 2 2 2 2 2
L14 V7
VSS25 VCCSUS3.3_7
L21 V8
VSS26 VCCSUS3.3_8
M1 V9
VSS27 VCCSUS3.3_9
M11
VSS28 +1.5VS
VCC1.5 power place VCCLAN1.5 power place VCCPLL power place
M12
VSS29
M13
M20
VSS30 GND POWER K10
VSS31 VCC1.5_0
M22 K12
VSS32 VCC1.5_1
N10 K18
VSS33 VCC1.5_2 +3VALW +1.5VS
N11 K22
VSS34 VCC1.5_3 +VCCP
N12 P10
VSS35 VCC1.5_4 1U_0603_10V4Z 0.1U_0402_16V4Z
N13 T18
VSS36 VCC1.5_5
N14 U19
VSS37 VCC1.5_6
N19 V14 1 1 1 1 1 1 1
VSS38 VCC1.5_7 +1.5VALW
N21 C82
VSS39 C460 C89 C83 C60 C483 C100
N23 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 VSS40 0.1U_0402_16V4Z 2
N5 E12
VSS41 VCCSUS1.5_0 2 2 2 2 2 2 2
P11 E13
VSS42 VCCSUS1.5_1
P13 E20
VSS43 VCCSUS1.5_2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
P20 F14
VSS44 VCCSUS1.5_3
P22
VSS45 VCCSUS1.5_4
G18 VCCHI power place
P3 R6
VSS46 VCCSUS1.5_5
R18 T6
VSS47 VCCSUS1.5_6
R21 U6
VSS48 VCCSUS1.5_7
R5
VSS49
T1
VSS50 VCC5REF
T19 E7
VSS51 VCC5REF1 +3VALW +5VALW +3VS +5VS +5VCD
T23 V6
VSS52 VCC5REF2
U20
VSS53 VCC5REFSUS
V15 E15

1
VSS54 VCC5REFSUS1 +1.5VS
V17
VSS55 D23 R116 D22 R84 R182
V3
VSS56 1K_0402_5% @ 1K_0402_5% 1K_0402_5%
W22 L23 1SS355_SOD323 1SS355_SOD323
VSS57 VCCHI_0
W5 M14
VSS58 VCCHI_1
W8 P18

2
VSS59 VCCHI_2 VCC5REFSUS VCC5REF
Y19 T22
VSS60 VCCHI_3 +VCCP
Y7
VSS61
A16 1 1
VSS62
A18 AA23
VSS63 VCC_CPU_IO_0 C86 C54
A20 P14
VSS64 VCC_CPU_IO_1 0.1U_0402_16V4Z 0.1U_0402_16V4Z
A22 U18
VSS65 VCC_CPU_IO_2 2 2
A4
VSS66
AA12
VSS67
AA16 C22 +1.5VS
VSS68 VCCPLL
AA22
VSS69
AA3
VSS70
AA9 AB5 +RTCVCC
VSS71 VCCRTC
AB20
3 VSS72 3
AB7
VSS73
AC1
VSS74
AC10 E9 +3VS
VSS75 VCCLAN3.3_0
AC14 F9
VSS76 VCCLAN3.3_1
AC18
VSS77
AC23
VSS78
AC5 F6 +1.5VS
VSS79 VCCLAN1.5_0
B12 F7
B16
B18
VSS80
VSS81
VCCLAN1.5_1
RTC Battery
VSS82 +RTCPWR
B20
VSS83
B22
VSS84 BATT1
B9
C15
C17
VSS85
VSS86
VSS87
-2
+ 1 1
C488
2
C19
VSS88 0.1U_0402_16V4Z
C21

1
VSS89
C23
VSS90 ML1220T13RE
C6
VSS91
D1 BAS40-04_SOT23
VSS92
D12
VSS93 D24
D15
VSS94 +RTCVCC
D17

2
VSS95
D19
VSS96
D21
VSS97
D23
VSS98
D4 +CHGRTC
VSS99
D8
VSS100
A1
VSS101

4 4

FW82801DBM_BGA421

Compal Electronics, Inc.

Title

ICH4-M(3/3) PWR/GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
D ate: Friday, September 17, 2004 Sheet 24 of 47
A B C D E F G H
 5 4 3 2 1

HDD Connector <23> PD_D[0..15]

PD_D[0..15]

Q6
SUYIN_20125A-44G5T-01-C_NORMAL SI3443DV_TSOP6
PIDE_RST#

D
PD_ D7 1 2 PD_ D8

S
6
PD_ D6 3 4 PD_ D9
5 6 +5VALW 4 5 +5VCD Placea caps. near HDD
PD_ D5 PD _D10 2 1
PD_ D4 7 8 PD _D11 1 1
CONN.
D PD_ D3 9 10 PD _D12 C168 +5VS D

G
PD_ D2 11 12 PD _D13 C177 0.1U_0402_16V4Z

3
PD_ D1 13 14 PD _D14 10U_0805_10V4Z 2 10U_1206_16V4Z 1U_0603_10V4Z
PD_ D0 15 16 PD _D15 2
17 18 1 1
R601 R184 1 1 1
4.7K_0402_5% PD_DREQ 19 20 C475 C479 C473
<23> PD_DREQ +5VALW 1 2
21 22 R103 240K_0402_5% C478 C474
+3VS 1 2 <23> PD_IOW# 23 24 470_0402_5% 2 2
<23> PD_IOR# 25 26
P D_PIORDY PC SEL 1 2 C172 R186 10K_0402_5% 1000P_0402_50V7K 2 2 2
<23> P D_PIORDY 27 28
1 2 2 1 10U_1206_16V4Z 0.1U_0402_16V4Z
<23> PD_DACK# 29 30 R117
<22> PD_IRQ14

1
31 32 10K_0402_5% 1U_0603_10V4Z
<23> PD_A1 1 2
33 34
<23> PD_A0 35 36 PD_A2 <23>
<23> PD_CS#1 37 38 PD_CS#3 <23>
PHDD_LED#
<34> PHDD_LED# 39 40
+5VS 2 CD_PLAY
+5VS 41 42 C D_PLAY <34>
43 44 Q7
+5VS 1 2
R127 100K_0402_5% JP8 DTC124EK_SC59

3
+3VALW +5VCD

This is reverse type conn, PIDE_RST# connect to pin44.

1
G _PCI_RST#
After connector library ready, R176
10K_0402_5%

14
correct connection is PIDE_RST# connect to pin1!

1
U15A
<31,34> EC_IDERST

OE#
P

2
SD _CS#3 2 3 SW_SD_CS#3 +3VALW C138
<23> SD_CS#3 I O 0.1U_0402_16V4Z

G
1 2
C SN74LVC125APWLE_TSSOP14 +3VALW C

14
U16A

14
+5VCD U16B 1

P
PCIRST# A PIDE_RST#
4 3

P
A O
6 2

1
O B

G
G _PCI_RST# 5
<22> PIDERST# B

G
R178 SN74LVC08APW_TSSOP14

7
10K_0402_5% SN74LVC08APW_TSSOP14

7
4
U15B

OE#

2
SD _CS#1 5 6 SW_SD_CS#1
<23> SD_CS#1 I O

SN74LVC125APWLE_TSSOP14

SD_D[ 0..15]
CDROM CONN <23> SD_D[0..15]

C162
2 1 CD_AGND
C D_AGND <31>

10U_0805_10V4Z <34> PCMRST# +5VCD

JP11

1
INT_CD_L 1 2 INT_CD_R +3VALW
<31> INT_CD_L INT_CD_R <31>
3 4
SIDE_RST# SD_ D8 R179

14

10
5 6 1 2
B SD_ D7 SD_ D9 R167 @ 0_0603_5% U16C U15C 10K_0402_5% B
7 8
SD_ D6 9 10 SD_D10 PCIRST# 9

OE#
P

2
SD_ D5 SD_D11 A SI DE_RST#
11 12 8 9 8
SD_ D4 SD_D12 O I O
13 14 <22> SIDERST# 10
B

G
SD_ D3 15 16 SD_D13

2
SD_ D2 17 18 SD_D14

7
R484 SD_ D1 19 20 SD_D15 SN74LVC125APWLE_TSSOP14
4.7K_0402_5% SD_ D0 21 22 SD_DREQ SN74LVC08APW_TSSOP14
SD_DREQ <23> R165
1 2 23 24 SD_ IOR#
+3VS SD_IOR# <23>
SD_IOW# 25 26 10K_0402_5%
<23> SD_IOW#

1
S D_SIORDY 27 28 SD_DACK#
<23> S D_SIORDY SD_DACK# <23>
SD_ IRQ15 29 30
<22> SD_IRQ15 100K_0402_5%
<23> SD_A1 31 32 PDIAG# 1 R490 2 +5VCD
<23> SD_A0 33 34 SD_A2 <23>
SW_SD_CS#1 35 36 SW_SD_CS#3
SHDD_ LED# 37 38 W=80mils +3VALW
<34> SHDD_LED# +5VCD
39 40
1 2 +5VCD 41 42
+5VCD

1
R504 100K_0402_5% 43 44
45 46 R177
SD_ CSEL 47 48 10K_0402_5%
49 50 1 2 +5VCD
2

51 52 R541 @ 100K_0402_5%

2
R533 ALLTOP_C12431-1-5001 G _PCI_RST#
470_0402_5%

1
D
PCI RST# 2 2N7002_SOT23
1

<7,13,19,22,27,28,30> PCIRST# G Q5
S

3
A +5VCD
Placea caps. near CDROM A
CONN.

1 1 1 1
C596 C601 C606
C598 1U_0603_10V4Z 10U_1206_16V4Z
1000P_0402_50V7K 2 2 2 2 Compal Electronics, Inc.
Title
0.1U_0402_16V4Z
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & CDROM Connector & Direct CD
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
D ate: Friday, September 17, 2004 Sheet 25 of 47
5 4 3 2 1
 5 4 3 2 1

U 26 +3V
<22,27,28,30> PCI_AD[0..31]
PCI_AD[0..31] PCI_AD0
PCI_AD1
104
103
AD0
AD1
EEDO
AUX/EEDI
108
109
LAN_EEDO
LAN_EEDI 1 2 +3V
LAN_EECS 1
U30
CS VCC
8
LAN RTL8100C(L)
PCI_AD2 102 111 LAN_EECLK R314 LAN_EECLK 2 7 1
PCI_AD3 AD2 EESK LAN_EECS 5.6K_0402_5% LAN_EEDI SK NC
98 106 3 6
PCI_AD4 AD3 EECS LAN_EEDO DI NC C348
97 4 5
PCI_AD5 AD4 ACTIVITY# DO GND 0.1U_0402_16V4Z
96 117
PCI_AD6 AD5 LED0 L INK10_100# AT93C46-10SI-2.7_SO8 2
95 115
PCI_AD7 AD6 LED1
93 114
PCI_AD8 AD7 LED2
D 90 113 D
PCI_AD9 AD8 NC/LED3
CLK_PCI_ LAN PCI_AD10
89
87
AD9
1 LAN_TD+
H=1.98mm
PCI_AD11 AD10 TXD+/MDI0+ LAN_TD- U28
86 2
1
PCI_AD12 AD11 TXD-/MDI0- LAN_RD+
85 5
PCI_AD13 AD12 RXIN+/MDI1+ LAN_RD- LAN_R D+ RJ45_RX+
83 6 1 16
R279 PCI_AD14 AD13 RXIN-/MDI1- LAN_RD- RD+ RX+ RJ45_RX-
82 2 15
10_0402_5% PCI_AD15 AD14 RD- RX-
79 14 3 14
PCI_AD16 AD15 NC/MDI2+ CT CT
59 15
2

PCI_AD17 AD16 NC/MDI2-

1 58 18
PCI_AD18 AD17 NC/MDI3+
57 19 6 11
C284 PCI_AD19 AD18 NC/MDI3- LAN_TD+ CT CT RJ45_TX+
55 7 10
AD19 TD+ TX+

1
15P_0402_50V8J PCI_AD20 53 121 LAN_X1 LAN_TD- 8 9 RJ45_TX-
2 PCI_AD21 AD20 X1 LAN_X2 R312 R313 TD- TX-
50 122

1
AD21 X2

PCI I/F
PCI_AD22 49 10mil 49.9_0402_1% 49.9_0402_1%
PCI_AD23 AD22 R280 1
47 105 2 1K_0402_5% +3VS R310 R311 NS0013_16P

1
PCI_AD24 AD23 LWAKE LAN_ISOLATE# R281 1
43 23 2 15K_0402_5% 49.9_0402_1% 49.9_0402_1%

2
PCI_AD25 AD24 ISOLATE# LO AN_RTSET R292 1
42 127 2 5.36K_0603_1%
PCI_AD26 AD25 RTSET R278 R277
40 72 10mil

2
PCI_AD27 AD26 NC/SMBCLK 75_0402_1% 75_0402_1%
39 74
PCI_AD28 AD27 NC/SMBDATA
37

2
PCI_AD29 AD28
36 88 1 1 1
PCI_AD30 AD29 NC/M66EN
34
PCI_AD31 AD30 C328 C326 C325 R J45_GND
33 10
AD31 NC/AVDDH 0.01U_0402_25V7Z 0.01U_0402_25V7Z 0.1U_0402_16V4Z
120
PCI_CBE#0 NC/HV 2 2 2
<22,27,28,30> PCI_CBE#0 92
PCI_CBE#1 C/BE#0
<22,27,28,30> PCI_CBE#1 77 11
PCI_CBE#2 C/BE#1 NC/HSDAC+
<22,27,28,30> PCI_CBE#2 60 123
PCI_CBE#3 C/BE#2 NC/HG
<22,27,28,30> PCI_CBE#3 44 124
C/BE#3 NC/LG2 +LAN_DVDD
126
PCI_AD17 NC/LV2
1 2 LAN_IDSEL 46
IDSEL

LAN I/F
R300 100_0402_5%
C +3V C
<22,27,28,30> P CI_PAR 76
PAR
<22,27,28,30> PCI_FRAME# 61 9
FRAME# NC/VSS
<22,27,28,30> PCI_ I RDY# 63 13
IRDY# NC/VSS
<22,27,28,30> PCI _TRDY# 67

3
TRDY# E
<22,27,28,30> PCI_DEVSEL# 68
DEVSEL# CTRL25 Q27
<22,27,28,30> PCI_STOP# 69 22 2
STOP# NC/GND B 2SB1197K_SOT23 Q25
48
NC/GND C DTA114YKA_SOT23 JP4
70 62 40mil

E
<22,27,28,30> P CI_PERR#

1
PERR# NC/GND
<22,28,30> P CI_SERR# 75
SERR# NC/GND
73 +2.5V_LAN +3V
3 1 1 2 10mil 12
Amber LED+

47K
112 1 1 R268

C
NC/GND 300_0402_5%
<22> PCI_REQ#1 30 118 11
REQ# NC/GND Amber LED-

10K
29 C294 C288 16

B
<22> PCI_GNT#1 GNT# SHLD4
10U_0805_10V4Z 0.1U_0402_16V4Z 8
2 2 PR4-
25 15

2
<22> PCI_PIRQF# INTA# CTRL25 SHLD3
8 7
CTRL25 ACTIVITY# PR4+
<28,30,34> ONBD_LAN_PME# 31
PME# RJ45_RX-
125 6
RTT3/CRTL18 PR2-
<22,33,34> B_PCIRST# 27
RST#
26 +3V 5
CLK_PCI_ LAN VDD33 PR3-
<12> CLK_PCI_LAN 28 41
PM_CLKRU N# CLK VDD33
<23,30,33,34> PM_CLKRUN# 65 56 4
CLKRUN# VDD33 PR3+
71
VDD33 RJ45_RX+
84 3
VDD33 PR2+
94
VDD33 RJ45_TX-
107 2
VDD33 PR1-
4 14
GND/VSS RJ45_TX+ SHLD2
17 1
GND/VSS PR1+
128 13
GND/VSS +LAN_AVDDL SHLD1
3 1 2 +3V 10
AVDD33/AVDDL L16 0_0805_5% Green LED-
7 40mil

E
AVDD33/AVDDL
21
GND/VSSPST AVDD33/AVDDL
20 1 1 1 +3V
3 1 1 2 10mil 9
GreenLED+

47K
B 38 16 C286 0.1U_0402_16V4Z C291 R258 B

1
GND/VSSPST NC/AVDDL 300_0402_5%
51 AMP RJ45/RJ11 with LED
GND/VSSPST

10K
66 0.1U_0402_16V4Z C290 0.1U_0402_16V4Z

B
GND/VSSPST 2 2 2 Q26 R270 R269
Y1 81 32
LAN_X1 LAN_X2 GND/VSSPST VDD25/VDD18 DTA114YKA_SOT23 75_0402_1% 75_0402_1%
91 54

2
GND/VSSPST VDD25/VDD18
101 78

2
GND/VSSPST VDD25/VDD18 +LAN_DVDD L INK10_100#
119 99 1 2 +2.5V_LAN
25MHZ_20P_1BX25000CK1A GND/VSSPST VDD25/VDD18 R273 0_0805_5%
1 1 40mil
Power

1 1 1
C320 C311 35 24 0.1U_0402_16V4Z R J45_GND 1 2 L A NGND
27P_0402_50V8J 27P_0402_50V8J GND NC/VDD18 C345
2 2
52
GND NC/VDD18
45 20mil 1 1
80 64 C331 C3220.1U_0402_16V4Z C275
GND NC/VDD18 2 2 2 1000P_1206_2KV7K C267 C270
100 110
GND NC/VDD18 0.1U_0402_16V4Z 4.7U_0805_10V4Z
116
NC/VDD18 2 2
+3V
12 +2.5V_LAN_VDD 1 2 +2.5V_LAN 0.1U_0402_16V4Z
AVDD25/HSDAC- R276 0_0805_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z
20mil 1 1
RTL8100C_QFP128 1 1 1 1 1 1 Termination plane should be closed
C289 C287
0.1U_0402_16V4Z 10U_0805_10V4Z C324 C302 C347 C344 C346 C285
to chassis ground and also depends
2 2 0.1U_0402_16V4Z on safety concern
2 2 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

A A

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN RTL8100CL
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Cus tom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
Date: Friday, September 17, 2004 Sheet 26 of 47
5 4 3 2 1
 A B C D E

+3VS

+3VS
C580 C583 C571 C555 C549 C521 C579 C537 U43
1 8
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z A0 VCC
2 7 1 2
A1 WC EECK_1394 R470
3 6
A2 SCL EEDI_1394 560_0402_5%
4 5
GND SDA
AT24C02N-10SC-2.7_SO8
+3VS Use 24C02 D Version :SA024020310

1 1
C522 C535 C520 C568 C540

1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K

+3VS

+3VS
PCI_AD[0..31]
<22,26,28,30> PCI_AD[0..31]

2
L24
FCM2012C-800_0805

110
122

111

100
108
118
126

112
46
36
99

17
32

21
30

31
47
91

13
23
33

22
38
5

6
U41

PVD
PVD
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

1
PCI_AD0 25
PCI_AD1 AD0 +3V_1394
24
PCI_AD2 AD1
20
PCI_AD3 AD2
19
PCI_AD4 AD3 0.1U_0402_16V4Z
18 59
PCI_AD5 AD4 PVA
16 62 2 2 2 2
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
15
14
11
AD5
AD6
AD7
AD8
Power PVA
PVA
PVA
PVA
72
73
86
1
C586
1
C559
1 1
C548
C560
0.1U_0402_16V4Z
10 87
PCI_AD10 AD9 PVA 0.1U_0402_16V4Z 0.1U_0402_16V4Z
9
2 PCI_AD11 AD10 2
8
PCI_AD12 AD11
7
PCI_AD13 AD12
4 61
PCI_AD14 AD13 GND
3 65
PCI_AD15 AD14 GND
2 66
PCI_AD16 AD15 GND
117 79
PCI_AD17 AD16 GND
116 80
PCI_AD18 AD17 GND
115
AD18 GND
56 W/ EEPROM Pop R467
PCI_AD19 114
PCI_AD20 113
AD19 W/O EEPROM Unpop 467
PCI_AD21 AD20
109
AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
107
106
103
102
101
AD22
AD23
AD24
AD25
IEEE 1394 EEPROM EEDO
I/F EEDI/SDA
EECK/SCL
EECS
26
27
28
29
R467

EEDI_1394
EECK_1394
1

@ 4.7K_0402_5%
2 +3VS
PCI Bus

AD26

IDSEL:PCI_AD16
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
98
97
96
95
94
AD27
AD28
AD29
AD30
VT6301S PM & Test
PME#
34

60 R491 1K_0402_5% R503 6.34K_0402_1%

AD31 XCPS
12 63 C587 2 1 47P_0402_50V8J
<22,26,28,30> PCI_CBE#0 CBE0# XREXT

Differential Pairs
1 FOX_UV31413-4R1-TR
<22,26,28,30> PCI_CBE#1 CBE1#
119 67 XTPB0- XTPA0+ 4 Connect To
<22,26,28,30> PCI_CBE#2 CBE2# TPB0M 4
104 68 XTPB0+ XTPA0- 3 6
<22,26,28,30> PCI_CBE#3 CBE3# TPB0P
69 XTPA0- XTPB0+ 2
3 6
5
Shielding
PCI_AD16 TPA0M XTPA0+ XTPB0- 2 5 GND
1 R428 2 100_0402_5% 105 70 1
IDSEL TPA0P XTPBIAS0 1
<22,26,28,30> PCI_FRAME# 120 71
FRAME# TPBIAS0

54.9_0402_1%

54.9_0402_1%

54.9_0402_1%

4.99K_0603_1% 54.9_0402_1%
121 JP18
<22,26,28,30> PCI_ I RDY# IRDY#

1
<22,26,28,30> PC I_TRDY# 123
3 TRDY# R472 R475 R479 R481 3
124
<22,26,28,30> PCI_DEVSEL# DEVSEL#
<22,26,28,30> PCI_STOP# 125
STOP#
<22,26,28,30> P CI_PERR# 127
PERR#
128

2
<22,26,28,30> PCI_PAR PAR
<22> PCI_REQ#0 93
REQ#
92
<22> PCI_GNT#0
NC

1
GNT#

0.33U_0603_16V4Z

270P_0402_25V8K
<22> PCI_PIRQE# 88 1 1
INTA# C567 C576 R486
89 55
<7,13,19,22,25,28,30> PCIRST#
CLK_ PCI_1394 90 PCIRST#
OSC PHYRESET#
CARDEN

<12> CLK_PCI_1394 PCICLK

I2CEN
1

2 2

2
1394
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

XO

R446
XI

@ 10_0402_5% 2
VT6301S-CD_LQFP128 C578
41
42
45
48
49
50
37
51
52
53
54
40
39
35
74
75
76
77
78
64
81
82
83
84
85

43
44

57

58

Note:These components
2

1 0.1U_0402_16V4Z
1 need to close to chip pins.
C541
@ 18P_0402_50V8K
2
X2
XI 2 1XO
+3VS
R487
4.7K_0402_5%
24.576MHz_16P_3XG-24576-43E1
If use 93C46, Delete R649
2 2
R485
C588 1M_0402_5% C589
10P_0402_50V8K 10P_0402_50V8K
1 1
4 4

Compal Electronics, Inc.

Title
IEEE1394a VIA VT6301S
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
PROPRIETARY NOTE TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE Cus tomEAL20 LA-2462 0.1
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, September 17, 2004 Sheet 27 of 47
A B C D E
 A B C D E

+3VS
<29> VPPD0 +S1_VCC
<29> VPPD1 +3VS
<29> VCCD0#
<29> VCCD1# 1 1 1 2
1 1

M13

M12

G13
N13

N12

D12
H11

G1
C8

N4
A7

B4

K2
C153 C164 C167 C181

F3
L9
L6
U42 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
S1_A[0..25] 2 2 2 1

VCCD1#
VCCD0#

VPPD1
VPPD0

VCCA2
VCCA1

VCC10
VCC9
VCC8
VCC7
VCC6
VCC5
VCC4
VCC3
VCC2
VCC1
S1_A[0..25] <29>
S1_D[0..15]
PCI_AD[0..31] S1_D[0..15] <29>
<22,26,27,30> PCI_AD[0..31] +3VS
PCI_AD31 C2 B2 S1_D10
PCI_AD30 AD31 CAD31/D10 S1_D9
C1 C3
PCI_AD29 AD30 CAD30/D9 S1_D1
D4 B3 1 1 1 1
CLK_EXT_SD48 CL K_PCI_PCM PCI_AD28 AD29 CAD29/D1 S1_D8
D2 A3
PCI_AD27 AD28 CAD28/D8 S1_D0 C156 C151 C180 C174
D1 C4
1

PCI_AD26 AD27 CAD27/D0 S1_A0 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

E4 A6
R183 R464 PCI_AD25 AD26 CAD26/A0 S1_A1 2 2 2 2
E3 D7
10_0402_5% 10_0402_5% PCI_AD24 AD25 CAD25/A1 S1_A2
E2 C7
@ @ PCI_AD23 AD24 CAD24/A2 S1_A3
F2 A8
PCI_AD22 AD23 CAD23/A3 S1_A4
F1 D8
2

PCI_AD21 AD22 CAD22/A4 S1_A5

1 1 G2 A9
PCI_AD20 AD21 CAD21/A5 S1_A6
G3 C9
C158 C561 PCI_AD19 AD20 CAD20/A6 S1_A25 +S1_VCC
H3 A10
15P_0402_50V8J 15P_0402_50V8J PCI_AD18 AD19 CAD19/A25 S1_A7
H4 B10
2 @ 2 @ PCI_AD17 AD18 CAD18/A7 S1_A24
J1 D10
PCI_AD16 AD17 CAD17/A24 S1_A17
J2 E12 1 1 1 1
PCI_AD15 AD16 CAD16/A17 S1_IOWR#
N2 F10 S1_IOWR# <29>
PCI_AD14 AD15 CAD15/IOWR# S1_A9 C152 C161 C147 C160
M3 E13
PCI_AD13 AD14 CAD14/A9 S1_IORD# 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
N3 F13 S1_IORD# <29> 0.1U_0402_16V4Z
PCI_AD12 AD13 CAD13/IORD# S1_A11 2 2 2 2
K4 F11
+VCC_5IN1 PCI_AD11 AD12 CAD12/A11 S1_OE#
M4 G10 S1_OE# <29>
PCI_AD10 AD11 CAD11/OE# S1_CE2#
K5 G11 S1_CE2# <29>
PCI_AD9 AD10 CAD10/CE2# S1_A10
L5 G12
PCI_AD8 AD9 CAD9/A10 S1_D15
M5 H12
2

2 PCI_AD7 AD8 CAD8/D15 S1_D7 2

K6 H10
R435 PCI_AD6 AD7 CAD7/D7 S1_D13
M6 J11
PCI_AD5 AD6 CAD6/D13 S1_D6
0_0805_5% N6 J12
@ PCI_AD4 AD5 CAD5/D6 S1_D12
M7 K13
PCI_AD3 AD4 CAD4/D12 S1_D5
N7 J10
1

PCI Interface
AD3 CAD3/D5
2 5IN1@ 1 SD_PUL LHIGH PCI_AD2 L7 K10 S1_D11
AD2 CAD2/D11

CARDBUS
R495 0_0805_5% PCI_AD1 K7 K12 S1_D4
AD1 CAD1/D4
1 5IN1@ 2 SDCM_XDALE PCI_AD0 N8 L13 S1_D3
R440 43K_0402_5% AD0 CAD0/D3
1 5IN1@ 2 SD DA0_XDD7
<22,26,27,30> PCI_CBE#3 E1 B7 S1_REG#
S1_REG# <29>
R438 43K_0402_5% CBE3# CCBE3#/REG# S1_A12 S1_CD1# S1_CD2#
<22,26,27,30> PCI_CBE#2 J3 A11
CBE2# CCBE2#/A12
1 5IN1@ 2 SD DA1_XDD0
<22,26,27,30> PCI_CBE#1 N1 E11 S1_A8
R456 43K_0402_5% CBE1# CCBE1#/A8 S1_CE1#
<22,26,27,30> PCI_CBE#0 N5 H13 S1_CE1# <29> 1 1
CBE0# CCBE0#/CE1#
1 5IN1@ 2 SD DA2_XDCL C179 C530
R443 43K_0402_5% G4 B9 S1_RST
<7,13,19,22,25,27,30> PCIRST# PCIRST# CRST#/RESET S1_RST <29>
1 5IN1@ 2 SD DA3_XDD4
<22,26,27,30> PCI_FRAME# J4 B11 S1_A23 10P_0402_50V8K 10P_0402_50V8K
R447 43K_0402_5% FRAME# CFRAME#/A23 S1_A15 2 2
<22,26,27,30> PC I_IRDY# K1 A12
+3VS IRDY# CIRDY#/A15 S1_A22
<22,26,27,30> PCI_TRDY# K3 A13
TRDY# CTRDY#/A22 S1_A21
<22,26,27,30> PCI_DEVSEL# L1 B13
DEVSEL# CDEVSEL#/A21 S1_A20
<22,26,27,30> PCI_STOP# L2
STOP# CSTOP#/A20
C12 Closed to Pin L12 Closed to Pin A4
L3 C13 S1_A14
<22,26,27,30> PCI_PERR# PERR# CPERR#/A14
1 2 S DCD# M1 A5 S1_WAIT#
<22,26,30> PCI_SERR# SERR# CSERR#/WAIT# S1_WAIT# <29>
R468 @ 43K_0402_5% M2 D13 S1_A13
<22,26,27,30> PCI_PAR PAR CPAR/A13
1 2 SD WP A1 B8 S1_INPACK#
<22> PCI_REQ#2 PCIREQ# CREQ#/INPACK# S1_INPACK# <29>
R452 @ 43K_0402_5% B1 C11 S1_WE#
<22> PCI_GNT#2 PCIGNT# CGNT#/WE# S1_WE# <29>
1 2 MSINS# CL K_PCI_PCM H1 B12 A16_CLK 1 2 S1_A16 Close chip termenal
<12> CLK_PCI_PCM PCICLK CCLK/A16
R473 @ 43K_0402_5% R444 33_0402_5%
<26,30,34> PCM_PME# R500 1 2 @ 0_0402_5% L8 C5 S1_BVD1
R477 1 RIOUT#_PME# CSTSCHG/BVD1_STSCHG# S1_BVD1 <29>
+3VS 2 10K_0402_5% L11 D5 S1_WP
S1_WP <29>
SUSPEND# CCLKRUN#/WP_IOIS16#
IDSEL: PCI _AD20 1 2 PC M_ID F4 D11 S1_A19
R460 100_0402_5% IDSEL CBLOCK#/A19 MSD0_XDD2 1 2
3 PCI_AD20 PCI_ PIRQA# K8 D6 S1_RDY# R462 @ 43K_0402_5% 3
<13,22> PCI_PIRQA# MFUNC0 CINT#/READY_IREQ# S1_RDY# <29>
R501 SD_PUL LHIGH N9 MSD1_XDD6 1 2
PCI_ PIRQB# MFUNC1 PCM_SPK# R465 @ 43K_0402_5%
+3VS 2 1 <22> PCI_PIRQB# K9 M9 PCM_SPK# <31>
5IN1@ 43K_0402_5% MFUNC2 SPKROUT S1_BVD2 MSD2_XDD5
<22,33,34> SIRQ N10 B5 S1_BVD2 <29> 1 2
MFUNC3 CAUDIO/BVD2_SPKR# R457 @ 43K_0402_5%
<29> SM_CD# L10
5IN1_LED# MFUNC4 S1_CD2# MSD3_XDD3
N11 A4 S1_CD2# <29> 1 2
MFUNC5 CCD2#/CD2# S1_CD1# R453 @ 43K_0402_5%
M11 L12 S1_CD1# <29>
SDO C# MFUNC6 CCD1#/CD1# S1_VS2 MSBS_XDD1
One memory card controller use MFUNC7 as OC#, <29> SDOC# J9
MFUNC7 CVS2/VS2#
D9 S1_VS2 <29> 1 2
C6 S1_VS1 R471 @ 43K_0402_5%
Another one use MFUNC6 as OC#. CVS1/VS1 S1_VS1 <29>
A2 S1_D2
CRSV3/D2
Connect 2 pin together to assert over current even to 2 PCIRST# M10
GRST# CRSV2/A18
E10 S1_A18
J13 S1_D14
controller at the same time. CRSV1/D14
This is ENE suggestion.

+VCC_5IN1 E7
SD/MMC/MS/SM H7
VCC_SD MSINS# MSINS# <29>
J8 XD_MS_PWREN#
MSPWREN#/SMPWREN# XD_MS_PWREN# <29>
S DCD# E8 H8 MSBS_XDD1
<29> S DCD# SDCD# MSBS/SMDATA1 MSBS_XDD1 <29>
SD WP F8 E9 1 2 5IN1@
<29> SDW P SDWP/SMWPD# MSCLK/SMRE# MSCLK_XDRE# <29>
SDPW REN# G7 G9 MSD0_XDD2 R448 33_0402_5%
<29> SDPW REN# SDPWREN33# MSDATA0/SMDATA2 MSD0_XDD2 <29>
H9 MSD1_XDD6
MSDATA1/SMDATA6 MSD1_XDD6 <29>
H5 G8 MSD2_XDD5
<12> CLK_EXT_SD48 SDCLKI MSDATA2/SMDATA5 MSD2_XDD5 <29>
R458 5IN1@ F9 MSD3_XDD3
MSDATA3/SMDATA3 MSD3_XDD3 <29>
<29> SD_CLK 1 2 22_0402_5% F6
SDCM_XDALE SDCLK/SMWE#
<29> SDCM_XDALE E5
SDCMD/SMALE
<29> XDWE# 1 2 22_0402_5% <29> SDDA0_XDD7
SDDA0_XDD7 E6 H6 XDBSY# <29>
SDDA1_XDD0 SDDAT0/SMDATA7 SMBSY#
<29> SDDA1_XDD0 F7 J7 XDCD# <29>
R628 5IN1@ SDDA2_XDCL SDDAT1/SMDATA0 SMCD#
<29> SDDA2_XDCL F5 J6 XDWP# <29>
SDDA3_XDD4 SDDAT2/SMCLE SMWP#
<29> SDDA3_XDD4 G6 J5 XDCE# <29>
SDDAT3/SMDATA4 SMCE#
2
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

G5
GND_SD R474
4 4
2.2K_0402_5%
CB714_LFBGA169 5IN1@
D3
H2
L4
M8
K11
F12
C10
B6

+3VS
5IN1 LED Side View
5IN1@ D12 5IN1@
5I N1_LED#
1 2 2 1
Compal Electronics, Inc.
R217 HT-110UYG-CT_YEL/GRN Title
120_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CardBus Controller CB714
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
D ate: Friday, September 17, 2004 Sheet 28 of 47
A B C D E
 5 4 3 2 1

JP12
PCMCIA Power Controller CardBus Socket 1 35
U18 +S1_VCC S1 _D3 GND GND S1_CD1#
1 2 2 36
C195 0.1U_0402_16V4Z S1 _D4 D3 / CAD0 CD1# / CCD1# S1 _D11 S1_CD1# <28>
VCC
13 40mil 3
D4 / CAD1 D11 / CAD2
37
12 S1 _D5 4 38 S1 _D12
VCC C196 0.1U_0402_16V4Z S1 _D6 D5 / CAD3 D12 / CAD4 S1 _D13
9 11 5 39
12V VCC S1 _D7 D6 / CAD5 D13/ CAD6 S1 _D14
1 2 6 40
C192 1U_0603_10V4Z S1 _CE1# D7 / CAD7 D14/ RFU S1 _D15
7 41
+S1_VPP <28> S1_CE1# S1_A10 CE1# / CCBE0# D15 / CAD8 S1 _CE2#
1 2 8 42
C197 @ 0.01U_0402_25V4Z S1_OE# A10 / CAD9 CE2# / CAD10 S1_VS1 S1_CE2# <28>
+5VS
20mil <28> S1_OE#
9
OE# / CAD11 VS1# / CVS1
43
S1_VS1 <28>
10 1 2 S1_A11 10 44 S1_IO RD#
VPP C190 @ 1U_0603_10V4Z S1_A9 A11 / CAD12 IORD# / CAD13 S1_IOWR# S1_IORD# <28>
11 45
0.1U_0402_16V4Z C217 S1_A8 A9 / CAD14 IOWR# /CAD15 S1_A17 S1_IOWR# <28>
5 12 46
5V S1_A13 A8 / CCBE1# A17 / CAD16 S1_A18
6 13 47
4.7U_0805_10V4Z C222 5V S1_A14 A13 / CPAR A18 / RFU S1_A19
D 14 48 D
S1_WE# A14 / CPERR# A19 / CBLOCK# S1_A20
1 VC CD0# <28> <28> S1_WE# 15 49
VCCD0 S1 _RDY# WE# / CGNT# A20 / CSTOP# S1_A21
2 VC CD1# <28> <28> S1 _RDY# 16 50
VCCD1 IREQ# / CINT# A21 / CDEVSEL#
15 VPPD0 <28> +S1_VCC 17 51 +S1_VCC
+3VS VPPD0 VCC VCC
14 VPPD1 <28> +S1_VPP 18 52 +S1_VPP
VPPD1 S1_A16 VPP1 VPP2 S1_A22
19 53
0.1U_0402_16V4Z C216 S1_A15 A16 / CCLK A22 / CTRDY# S1_A23
3 20 54
3.3V S1_A12 A15 / CIRDY# A23 / CFRAME# S1_A24
4 8 21 55
3.3V OC A12 / CCBE2# A24 / CAD17

SHDN
4.7U_0805_10V4Z C221 S1_A7 22 56 S1_A25

GND
S1_A6 A7 / CAD18 A25 / CAD19 S1_VS2
23 57
2

S1_A5 A6 / CAD20 VS2# / CVS2 S1_RST S1_VS2 <28>

24 58
R195 CP2211D3_SSOP16 S1_A4 A5 / CAD21 RESET / CRST# S1_WAIT# S1_RST <28>
25 59

16
10K_0402_5% S1_A3 A4 / CAD22 WAIT# / CSERR# S1_INPACK# S1_WAIT# <28>
26 60
S1_A2 A3 / CAD23 INPACK# / CREQ# S1_REG# S1_INPACK# <28>
27 61
S1_A1 A2 / CAD24 REG# / CCBE3# S1_BVD2 S1_REG# <28>
28 62
1

S1_A0 A1 / CAD25 SPKR# / CAUDIO S1_BVD1 S1_BVD2 <28>

29 63
S1 _D0 A0 / CAD26 STSCHG# / CSTSCHG S1 _D8 S1_BVD1 <28>
30 64
S1 _D1 D0 / CAD27 D8 / CAD28 S1 _D9
31 65
S1 _D2 D1 / CAD29 D9 / CAD30 S1 _D10
32 66
S1_WP D2 / RFU D10 / CAD31 S1_CD2#
33 67
<28> S1_WP IOIS16# / CCLKRUN# CD2# / CCD2# S1_CD2# <28>
34 68
+3VS GND GND
SD PWR Control +3VS
69 70
2

+VCC_5IN1 S1_A[0..25] GND GND

<28> S1_A[0..25] 71 72

2
R502 +3VS U44 5IN1@ GND GND
73 74
10K_0402_5% R520 S1_D[0 ..15] GND GND
75 76
5IN1@ 10K_0402_5% <28> S1_D[0..15] GND GND
1 8 77 78
GND OUT 5IN1@ GND GND
2 7 79 80
1

IN OUT GND GND

<28> SDP WREN# 3 6 81 82

1
IN OUT GND GND
<28> XD_MS_PWREN# 4 5 1 5IN1@ 2 S DOC# <28> 83 84
EN# OC# R528 0_0402_5% GND GND
1 85 86
C C592 GND GND C
87 88
+VCC_5IN1 GND GND
0.1U_0402_16V4Z

TPS2041ADR_SO8
5IN1@ FOX_WZ21131-G2-P4_RT
2
10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1
C518 C585 C618
C617
5IN1@ 5IN1@ 5IN1@ 5IN1@
2 2 2 2

5in1 Socket

+3VS xD PU and PD. Close to Socket

2 1 XDCD#
XDCD# <28>
R493 @ 43K_0402_5%
+S1_VCC
+VCC_5IN1
Reserve for Debug.
S1_WP 2 1
43K_0402_5% R436
2 5IN1@ 1 XDBSY# S1_OE# 2 1
XDBSY# <28>
R492 10K_0402_5% 47K_0402_5% R480 JP13
1 5IN1@ 2 S1_RST 2 1 SDDA1 _XDD0 34 11 SDDA3 _XDD4
XDCE# <28> <28> SDDA1_XDD0 SM-D0 / XD-D0 SD-DAT3
R494 2.2K_0402_5% 47K_0402_5% R433 MSBS_XDD1 33 12 SDDA2 _XDCL
<28> MSBS_XDD1 SM-D1 / XD-D1 SD-DAT2 SDDA2_XDCL <28>
1 5IN1@ 2 MSCLK_XDRE# S1 _CE1# 2 1 <28> MSD0_XDD2
MSD0_XDD2 32 6 SDDA1 _XDD0
B R449 10K_0402_5% 47K_0402_5% R463 MSD3_XDD3 SM-D2 / XD-D2 SD-DAT1 SDDA0 _XDD7 B
<28> MSD3_XDD3 31
SM-D3 / XD-D3 5 IN 1 CONN SD-DAT0
7
1 5IN1@ 2 XDWE# S1 _CE2# 2 1 <28> SDDA3_XDD4
SDDA3 _XDD4 21 5 SDWP
SDWP <28>
R455 10K_0402_5% 47K_0402_5% R459 MSD2_XDD5 SM-D4 / XD-D4 SD-WP-SW SDCM_XDALE
<28> MSD2_XDD5 22 10
MSD1_XDD6 SM-D5 / XD-D5 SD-CMD SD_CLK
<28> MSD1_XDD6 23 8
SDDA0 _XDD7 SM-D6 / XD-D6 SD_CLK
<28> SDDA0_XDD7 24 9 +VCC_5IN1
SM-D7 / XD-D7 SD-VCC
4
XDWP# N/C SDC D#
<28> XDWP# 35 42 SDC D# <28>
SDWP SM_WP-IN / XD_WP-IN SD-CD-SW
43 41
XDWE# SM-WP-SW SD-CD-COM
<28> XDWE# 36
SDCM_XDALE #SM_-WE / XD_-WE MSD0_XDD2
<28> SDCM_XDALE 37 15
#SM-ALE / XD-ALE MS-DATA0 MSD1_XDD6
SD CLK Close to +S1_VCC MS-DATA1
14
SD_CLK 25 16 MSD2_XDD5
<28> SD_CLK CardBus Conn. SM-LVD MS-DATA2
SM_CD# 3 18 MSD3_XDD3
<28> SM_CD#
1

SM-CD-SW MS-DATA3 MSC LK_XDRE#

+VCC_5IN1 29 19
R450 XDBSY# SM_-VCC / XD_-VCC MS-SCLK MSINS#
1 1 26 17 MSINS# <28>
0_0402_5% @ MSCLK_XDRE# #SM_R/-B / XD_R/-B MS-INS MSBS_XDD1
27 13
C194 C193 XDCE# #SM_-RE / XD_-RE MS-BS
28 20 +VCC_5IN1
10U_0805_10V4Z 0.1U_0402_16V4Z XDCD# #SM_-CE / XD_-CE MS-VCC
30
2

2 2 #SM_-CD
1 2 40 +VCC_5IN1
C536 SDDA2 _XDCL SM-CD-COM XD-VCC XDCD#
38 39
10P_0402_50V8K @ SM-CLE / XD-CLE XD-CD
1
GND
44
2 GND
TAITW _R0 07-010-N3 5IN1@
+S1_VPP

MS CLK 1 1
MSCLK_XDRE#
<28> MSCLK_XDRE#
C187 C188
1

4.7U_0805_10V4Z@ 0.01U_0402_25V7Z@
A R454 2 2 A
0_0402_5% @
2

1
C552
10P_0402_50V8K @
2 Compal Electronics, Inc.
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cardbus Slot & 5in1 Socket
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Cus tom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
Date: Friday, September 17, 2004 Sheet 29 of 47
5 4 3 2 1
 A B C D E

+3V
+5VS +3VS +3VS

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 1 1 1 1 1 1 1 1 1 1
C597 C126 C623 K S@ C135 C129 C163 KS@ C139 C191 C176 KS@ C504 C511 C514 KS@
KS@ KS@ 10U_0805_10V4Z KS@ K S@ 4.7U_0805_10V4Z KS@ KS@ 4.7U_0805_10V4Z KS@ KS@
2 2 2 2 2 2 2 2 2 2 2 2
4.7U_0805_10V4Z
1 1
1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K
1000P_0402_50V7K

+3V PCI_AD[0..31]
PCI_AD[0..31] <22,26,27,28>
C117 0.1U_0402_16V4Z
KS@

5
U13 JP10
1 TIP 1 2 RING

P
<34> W L_OFF# B 1 2
4 KEY KEY
Y
<32,34> KILL_SW# 2 3 4

G
A KS@ 3 4
5 6
5 6
7 8

3
TC7SH08FU_SSOP5 7 8
9 10
D7 9 10
11 12
KS@ 1 11 12
2 13 14
RB751V_SOD323 13 14
15 16
15 16
<22> PCI_PIRQH# 17 18 W=40mils +5VS
17 18
+3VS W=40mils 19
19 20
20 PCI_PIRQG# <22>
21 22 PCI_ GNT#4
<22> PCI_REQ#4 21 22 PCI_GNT#4 <22>
23
23 24
24 W=40mils +3V
CLK_PCI_MINI 25 26
2 <12> CLK_PCI_MINI 25 26 PCIRST# <7,13,19,22,25,27,28> 2
27 28 W=40mils +3VS
PCI_REQ#3 27 28 PCI_ GNT#3
<22> PCI_REQ#3 29 30
29 30 PCI_GNT#3 <22>
31 32
PCI_AD31 31 32
33 34
PCI_AD29 33 34 MINI_PME# <26,28,34>
35 36
35 36 PCI_AD30
37 38
PCI_AD27 37 38
39 40
PCI_AD25 39 40 PCI_AD28
41 42
41 42 PCI_AD26
43 44
43 44 PCI_AD24
<22,26,27,28> PCI_CBE#3 45 46
CLK_PCI_MINI PCI_AD23 45 46 MINI_IDSEL
47 48 1 2 R170 PCI_AD18
47 48 KS@ 100_0402_5%
49 50
PCI_AD21 49 50 PCI_AD22
51 52
1

PCI_AD19 51 52 PCI_AD20
53 54
R164 53 54
55 56 P CI_PAR <22,26,27,28>
PCI_AD17 55 56 PCI_AD18
57 58
@ 10_0402_5% PCI_CBE#2 57 58 PCI_AD16
<22,26,27,28> PCI_CBE#2 59 60
PCI_ I RDY# 59 60
<22,26,27,28> PCI_ I RDY# 61 62
2

61 62 PCI_FRAME#
1 63 64 PCI_FRAME# <22,26,27,28>
C132 63 64 PC I_TRDY#
65 66 PCI _TRDY# <22,26,27,28>
<23,26,33,34> PM_CLKRUN# PCI_SERR# 65 66 PCI_STOP#
67 68 PCI_STOP# <22,26,27,28>
@ 10P_0402_50V8K <22,26,28> PCI_SERR# 67 68
69 70
2 PCI_PERR# 69 70 PCI_DEVSEL#
<22,26,27,28> P CI_PERR# 71 72 PCI_DEVSEL# <22,26,27,28>
PCI_CBE#1 71 72
73 74
<22,26,27,28> PCI_CBE#1 PCI_AD14 73 74 PCI_AD15
75 76
75 76 PCI_AD13
77 78
PCI_AD12 77 78 PCI_AD11
79 80
PCI_AD10 79 80
81 82
81 82 PCI_AD9
83 84
PCI_AD8 83 84 PCI_CBE#0
85 86
PCI_AD7 85 86 PCI_CBE#0 <22,26,27,28>
87 88
3 87 88 PCI_AD6 3
89 90
PCI_AD5 89 90 PCI_AD4
91 92
91 92 PCI_AD2
93 94
PCI_AD3 93 94 PCI_AD0
95 96
95 96
+5VS W=40mils 97 98
PCI_AD1 97 98
99 100
99 100
101 102
101 102
103 104
103 104
105 106
105 106
107 108
107 108
109 110
109 110
111 112
111 112
113 114
113 114
115 116
115 116
117 118
117 118
119 120
119 120
W=30mils 121
121 122
122 W=40mils
+5VS 123 124 +3V
123 124
KS@ AMP_1318644-1

4 4

Compal Electronics, Inc.

Title
Mini PCI Slot
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
Date: Friday, September 17, 2004 Sheet 30 of 47
A B C D E
 A B C D E F G H

+AVDD_AC97 +AC97_DVDD
L27
Direct CD
AC97 Codec +5VAMP 1 2
1 2
L28 0_0805_5%
+3VS
CTL POWER ON
0_0805_5% 1 2 PATH +5VALWP
+3V
L26 1 1 0_0805_5%

14
1 1
INT_CD_L 2 1 CD_L C604 C646 SN74HCT4066PW_TSSOP14
<25> INT_CD_L 10U_0805_10V4Z R607
R583 20K_0402_5% 0.1U_0402_16V4Z C609 C632 @ U48A

P
INT_C D_R2 1 C D _R 2 2 0.1U_0402_16V4Z 10U_0805_10V4Z 2 1 1 2 AMP_LEFT
<25> INT_CD_R 2 2 +5VAMP A B
R587 20K_0402_5% @ 1M_0402_5%

C
1M_0402_5%
2 1 CD_GNA
<25> CD_AGND R585 20K_0402_5% L_OUT_L R608

25

38

13
1

9
U45 1 2 @

2
R593 R586 R584 R588 C616 @ 1000P_0402_50V7K

AVDD1

AVDD2

DVDD1

DVDD2
6.8K_0402_5%

6.8K_0402_5%
1 1

6.8K_0402_5%

14
1 2

2
0_0402_5% C611 @ 1000P_0402_50V7K SN74HCT4066PW_TSSOP14
R609 @ U48B

P
2

2
1
14 35 LI NEL 1 2 L_OUT_L +5VAMP 2 1 11 10 AMP_RIGHT
AUX_L LINE_OUT_L C615 1U_0402_6.3V4Z @ 1M_0402_5% A B
bypass EQ when NBA_PLUG = High

C
1M_0402_5%
15 36 LINER 1 2 L_OUT_R
AUX_R LINE_OUT_R C612 1U_0402_6.3V4Z L_OUT_R R610

12
16 37 @
NBA_PLUG JD2 MONO_OUT/VREFOUT3
<32> NBA_PLUG
R590 1 2 17 39

2
C651 1U_0402_6.3V4Z JD1 HP_OUT_L +3VS
MD_SPK 1 2 C_MD_SPK 1 2 23 41 C626 47P_0402_50V8J
C649 0.1U_0402_16V4Z LINE_IN_L HP_OUT_R
1 1 2 1
1

2
0.01U_0402_25V4Z

0_0402_5% 1 2 24 PATH_SEL
C656 R582 C650 0.1U_0402_16V4Z LINE_IN_R
C653 6 1 2 AC97_BITCLK <23>
@ @ 10K_0402_5% CD_L BIT_CLK
2 1 CD_LIN 18 R555 33_0402_5% R519
0.1U_0402_16V4Z 2 2 C641 1U_0402_6.3V4Z CD_L @ 10K_0402_5% +5VALWP
SDATA_IN
8 1 2 AC97_SDIN0 <23> DIRECT PLAY PATH
C D _R 2 1 C D _ RIN 20 R561 33_0402_5%
2

1
C643 1U_0402_6.3V4Z CD_R XTL_IN

14
2 1 2 CLK_14M_CODEC <12>
CD_GNA XTL_IN R527 SN74HCT4066PW_TSSOP14
2 1 CD_G NA1 19

2
C642 1U_0402_6.3V4Z CD_GND @ 0_0402_5% R611 @ U48C

P
M IC 2 1 C_ MIC 21 +5VAMP 2 1 4 3 AMP_LEFT
<32> MIC MIC1 A B
C644 1U_0402_6.3V4Z R517 @ 1M_0402_5%

C
+AVDD_AC97

1M_0402_5%
22 3 XTL_OUT @ 10K_0402_5%
MIC2 XTL_OUT C698 R612
Use to isolate +5VALW and +AC97_DVDD

5
C_MD_SPK 2 1 13 29 1 2 INT_CD_L 1 2 @

2
C648 1U_0402_6.3V4Z PHONE AFILT1 C630 1000P_0402_50V7K
M ONO_IN @ 1U_0603_10V4Z

14
12 30 1 2

2
PC_BEEP AFILT2 C628 1000P_0402_50V7K R602 SN74HCT4066PW_TSSOP14
Use to isolate +5VALW and +AC97_DVDD
28 + VREFOUT 1 2 1M_0402_5% R613 @ U48D

P
VREFOUT +AUD_VREF
AC97_RST# 1 2 11 R566 0_0603_5% +5VAMP 2 1 8 9 AMP_RIGHT
<23> AC97_RST#

1
R511 2 R578 33_0402_5% RESET# @ 1M_0402_5% A B
1 27

G
VREF

C
1M_0402_5%
2 10K_0402_5% AC97_SYNC 2 1 10 2
<23> AC97_SYNC SYNC
+AC97_DVDD 2 1 R577 33_0402_5% 32 C699 R614

6
R510 1K_0402_5% AC 97_SDOUT 2 DCVOL INT_C D_R @
<23> AC97_SDOUT 1 5 1 2
SDATA_OUT

1U_0402_6.3V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z
0.01U_0402_16V7K
R550 33_0402_5%
2

Q40 EC_SM_D2 @ 1U_0603_10V4Z

G

45 31 1 1 1 1

2
2N7002_SOT23 SDA NC C621 C622 C635 C636
46 33
XTLSEL VREFOUT2

1U_0402_6.3V4Z
1 3 EC_SM_D2 34 +VAUX 1 2
<4,34> EC_SMD_2 +AVDD_AC97

1
VAUX R518 0_0603_5% R546
47 43
D

<32> EAPD_CODEC SPDIFI/EAPD DISABLE# 1

2 2 2 2

0_0402_5%
44 EC_SM_C2 PATH_SEL_1
1

SCK @
1 2 48
R549 @ 0_0402_5% R521 SPDIFO C624
40
R512 2 0_0402_5% NC 2
1 Ra 4 26

2
10K_0402_5% @ DVSS1 AVSS1
7 42 A GND L_OUT_L 1 R619 2AMP_LEFT AMP_LEFT <32>
DVSS2 AVSS2 0_0402_5%
+AC97_DVDD 2 1
2

R513 1K_0402_5% ALC250-C_LQFP48 L_OUT_R 1 R620 2AMP_RIGHT

+5VALWP 0_0402_5% AMP_RIGHT <32>
DGND AGND 1 2 +3VS
2

Q39 R523 10K_0402_5%

G

2N7002_SOT23 UnPoped:Clock source from X'tal 1 2 EC_IDERST <25,34>

2
EC_SM_C2 R522 0_0402_5%
<4,34> EC_SMC_2 1 3
Poped: Clock source from Clock Gen Place these components R615
D

close to Codec 10K_0402_5%

1 2 1 2 @
R535 @ 0_0402_5% R540 @ 1M_0402_5% R616

1
X3 PATH_SEL_1 2 1 EC_IDERST
XTL_IN 2 1 XTL_OUT @ 0_0402_5%

1
D R617
24.576MHz_16P_3XG-24576-43E1 C638 4.7U_0805_10V4Z 2 PATH_SEL 2 1 SUSP# <34,37,42,43,44>

22P_0402_50V8J
1 1 +AUD_VREF 1 2 Q43 G
22P_0402_50V8J

C610 C619 2N7002_SOT23 S @ @ 0_0402_5%

3
GND Connect AGND 1 2
Keep a 80mil bridge far away from DC-DC area 2 2 C629 0.1U_0402_16V4Z
3 3

System Sound +3V +3VALW

+AVDD_AC97
1
1

C206 R581
<34> BEEP#
R189 1 2 10K_0402_5%
100K_0402_5%
0.1U_0402_16V4Z
MDC Connector
2
13

14
2

U15D U17A 1 2 1 MD_SPK

+3V
1

R193 C209 R200 C659 0_0805_5% R187 2 JP14 L11

OE#

12 11 1 2 1 2 1 2 1 2 R594 10U_0805_10V4Z +5VS_MDC 1 2

I O I O +5VS
8.2K_0402_5% 10K_0402_5% C184 1 2 2 0_0603_5%
G

1U_0402_6.3V4Z 560_0402_5% 2 MONO_OUT/PC_BEEP AUDIO_PWRDN/DETECH

+3V_MDC
1 10U_0805_10V4Z 3 4
SN74LVC125APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14 1 GND MONO_PHONE C204 1U_0603_10V4Z
5 6
7

C211 +3V POWER C647 0_0603_5% AUXA_RIGHT RESERVED/BT_ON#

7 8
0.22U_0402_10V4Z MONO_IN_O M ONO_IN AUXA_LEFT GND 1
2 1 +3VS 1 2+3VS_MDC 9 10
2 L9 CD_GND +5Vmain
2 11 12
1U_0402_6.3V4Z CD_RIGHT RESERVED/USB+ R192
13 14
C183 CD_LEFT RESERVED/USB- +3VS_MDC_R
15 16 1 2 +3VS
2

R201 GND RESERVED/PRIMARY_DN 10K_0402_5%

10U_0805_10V4Z 17 18
1

C210 C Q42 R591 1 +3.3Vaux/BT_VCC RESERVED/+5VD/WAKEUP

19 20
R488 GND RESERVED/GND R507 1
<28> PCM_SPK# 1 2 1 2 MO NO_IN_I 2 21 22 2 33_0402_5% AC97_SYNC
+3.3Vmain AC97_SYNC
2.4K_0402_5%

B AC 97_SDOUT 1 2 33_0402_5% 23 24 2 1 1 2
AC97_SDATA_OUT AC97_SDATA_IN1 AC97_SDIN1 <23>
2SC2411K_SC59

1U_0402_6.3V4Z 560_0402_5% E AC97_RST# 1 2 33_0402_5% 25 26 R191 0_0402_5% R194 33_0402_5%

3

R489 AC97_RESET# AC97_SDATA_IN0

27 28
GND GND R190 1
+3VALW 29 30 2 33_0402_5% AC97_BITCLK
4 AC97_MSTRCLK AC97_BITCLK 4
+3V POWER
ACES_88018-3010
14

U17B
C212 R202
P

<23> SB_SPKR 3 4 1 2 1 2
I O
G

1U_0402_6.3V4Z 560_0402_5%
Compal Electronics, Inc.
1

SN74LVC14APWLE_TSSOP14
7

Title
R203 D8
10K_0402_5% RB751V_SOD323
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AC97 CODEC ALC250 Ver.C
Size Document Number Rev
2

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C ustom EAL20 LA-2462
D ate: Friday, September 17, 2004 Sheet 31 of 47
A B C D E F G H
 A B C D E

Audio AMP Audio Board Connector

+5VAMP

W=40Mil
W/O EQ R385=R386= 1.3K Ohm SHUTD OWN# 2 1 +5VAMP
C537=C539= 0.47U 1 1 R597 100K_0402_5%
JP20
R = R385, R386 C245 C663 +5VAMP 1 13

1
0.1U_0402_16V4Z 4.7U_0805_10V4Z D NBA_PLUG 1 13
C = C537, C539 2 14
2 2 Q41 EAPD VOL_AMP 2 14
2 3 15
3 15
fo=1/(2*3.14*R*C)=260Hz G +AUD_VREF 4
4 16
16
R=1.5K / C=0.47U 2N7002_SOT23S 5 17

3
1 M IC 5 17 1
<31> MIC 6 18
6 18
7 19
HIGH PIN 10,4 ACTIVE INTSPK_R1 7 19
8 20
U21 INTSPK_L1 8 20
Pin 22 9
9 21
21
LOW PIN 9,5 ACTIVE 7 22 10 22
PVDD SHUTDOWN# NBA_PLUG 10 22
18 15 <34> WL_LED# 11 23
PVDD SE/BTL# 11 23
19 14 1 2 <30,34> KILL_SW# 12 24
VDD PC-BEEP C239 0.1U_0402_16V4Z 12 24
<31> NBA_PLUG 11
NBA_PLUG BYPASS INTSPK_L2 ACES_85203-1202
2 9
VOL_AMP HP/LINE# LOUT- INTSPK_R2
2 1 3 16
C235 0.1U_0402_16V4Z INTSPK_L1 VOLUME ROUT-
4 10
INTSPK_R1 LOUT+ LIN
21 8
AMP_LEFT AMP_L AMP_LIN ROUT+ RIN
<31> AMP_LEFT 1 2 1 2 5
C240 0.47U_0603_16V4Z C237 0.47U_0603_16V4Z AMP_RIN LLINEIN
23 1
RLINEIN GND

0.47U_0603_16V4Z

0.47U_0603_16V4Z

0.47U_0603_16V4Z
AMP_RIGHT 1 2 AMP_R 1 2 6 12
<31> AMP_RIGHT LHPIN GND
C661 0.47U_0603_16V4Z C665 0.47U_0603_16V4Z 20 13 2 1 1
AMP_LEFT H P_L RHPIN GND
1 2 24
C241 0.47U_0603_16V4Z GND
17
AMP_RIGHT H P_R CLK C253 C251 C252
1 2
C666 0.47U_0603_16V4Z TPA0232PWP_TSSOP24 1 2 2
1
1.5K_0402_5% 2 1 R221 AMP_L C238
0.047U_0402_16V4Z (0.47U~1U)
1.5K_0402_5% 2 1 R596 AMP_R 2

+3VALW

14
U9A
1 Speaker Connector

P
2 <31> EAPD_CODEC A 2
3 EAPD
O
<34> EAPD_KBC 2
B

G
SN74LVC32APWLE_TSSOP14

1
D28 D27
V-PORT-0603-220 M-V05_0603 @ @ V-PORT-0603-220 M-V05_0603

JP19

2
INTSPK_R1 L34 1 2 FBM-11-160808-121-T_0603
INTSPK_R2 L33 FBM-11-160808-121-T_0603 1
1 2
INTSPK_L1 L32 FBM-11-160808-121-T_0603 2
1 2
Regulator for AMP INTSPK_L2 L31 1 2 FBM-11-160808-121-T_0603 3
4
ACES_85204-0400

1
D26 D25
+5VALW DECOUPLING
+5VALW TO +5VLDO
V-PORT-0603-220 M-V05_0603 @ @ V-PORT-0603-220 M-V05_0603
+5VALWP

2
+5VALWP
3

R232 10K_0402_5%
22U_1206_16V4Z_V1

1 2 2
1U_0603_10V4Z

1U_0603_10V4Z
22U_1206_16V4Z_V1

1
Q19
C254 1 1 1 1
1U_0603_10V4Z AOS 3401_SOT23 C244 C243
1

2 C255 C249
3 @ 3
+5VALW_LDO 2 2 2 2
Moat Bridge
5
6
7
8

+5VALWP +12VALW
D
D
D
D
1

R230 R215 SI4800 1N_SO8

G
S
S
S

U20 (4.5V)
10K_0402_5% 1K_0402_5%
4
3
2
1

+5VLDO DECOUPLING
2

+5VLDO
1

D
1U_0805_25V4Z

1
2 Q20 C234 +5VLDO (4.5V)
G
S 2N7002_SOT23 @ 1 2
3

2 R223 0_0805_5%
1

D
4.7U_0805_10V4Z

4.7U_0805_10V4Z

1U_0603_10V4Z

0.1U_0402_16V4Z

0.1U_0402_10V6K
22U_1206_16V4Z_V1

R595 1 2
1U_0603_10V4Z

2 LM431SB_SOT23 R516 0_0805_5%

34,36,37,43> SY SON
G 3.9K_0603_1% 1 2
Q21 S 2 1 1 1 1 1 1 1 R567 0_0805_5%
3

2N7002_SOT23 K C645 C660 C652 C662 C664 C657 C658

1
A @ @ @
3 2 2 2 2 2 2 2
R
1

D13 R592

4.99K_0603_1%
+5VAMP TO +5VLDO
2

4 L29 4

+5VLDO 1 2 +5VAMP
0_0805_5%

L30
1 2
0_0805_5%

Compal Electronics, Inc.

Title
AMP & Audio Jack
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C ustom EAL20 LA-2462
D ate: Friday, September 17, 2004 Sheet 32 of 47
A B C D E
 10 9 8 7 6 5 4 3 2 1

SUPER I/O SMsC LPC47N217

+3VS FIR Module L: R POP; FIR Enable
H: R De-POPFIR Disable

1 1 1 1
H C45 SIO@ C53 SIO@ C 32 SIO@ C69 SIO@ H

4.7U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
+3VS FIR_DET# 1 2
IRRX 1 2 F IR@ R112 0_0402_5%
2 2 2 2 R P2 R357 F IR@
DC D#1 8 1 10K_0402_5%
RI#1 7 2
D SR#1 6 3
CTS#1 5 4
SIO@ +IR_ANODE
4.7K_1206_8P4R_5%
1 2
for VISHAY FIR issue +3VS
R157 4.7_1206_5% @
1
R160
2
4.7_1206_5% F IR@
W=60mil

G G
U8 SIO@ 1K_0402_5%
LPC_AD0 10 62 RXD1 R 62 1 2 U38
<23,34> LPC_AD0 LPC_AD1 LAD0 RXD1 TXD1

SERIAL I/F
<23,34> LPC_AD1 12 63 1
LPC_AD2 LAD1 TXD1 D SR#1 +IR_3VS IRED_A
<23,34> LPC_AD2
13
LAD2 DSR1#
64 2
IRED_C TXD
3 T = 12mil IRTXOUT
LPC_AD3 14 1 RTS#1 IRRX 4 5 T = 12mil I RMODE
<23,34> LPC_AD3 LAD3 RTS1# CTS#1 +IR_3VS RXD SD/MODE
2 +3VS 1 2 6 7
LPC_FRAME# CTS1# DTR#1 R163 F IR@ VCC MODE
<23,34> LPC_FRAME# LPC_DRQ#1
15
LFRAME# DTR1#
3
RI#1 47_1206_5%
W=40mil 8
GND
16 4 1 1
<23> LPC_DRQ#1 LDRQ# RI1#

LPC I/F
5 DC D#1 C130 C125 TFDU6102-TR3_8P F IR@
B_PCIRST# DCD1# F IR@ F IR@
<22,26,34> B_PCIRST# 17
R109 1 SIO@ SIO_PD# PCI_RESET# IRRX
2 10K_0402_5% 18 37 10U_0805_10V4Z 0.1U_0402_16V4Z
+3VS LPCPD#
FIR IRRX2
38 IRTXOUT 2 2 Change to Vishay 6102
PM_CLKRUN# IRTX2 I RMODE
19 39
<23,26,30,34> PM_CLKRUN# CLK_PCI_SIO CLKRUN# IRMODE/IRRX3
<12> CLK_PCI_SIO 20
SI RQ PCI_CLK LPTINIT#
<22,28,34> S IRQ 21 41
F SIO_PME# SER_IRQ INIT# LPTSLCTIN# F
1 2 6 42
+3VS R76 SIO@ 10K_0402_5% IO_PME# SLCTIN# LPD0
44
CL K_14M_SIO PD0 LPD1
9 46
<12> CLK_14M_SIO CLK14 PD1 LPD2
CLOCK 47
PD2 LPD3
23 48
GPIO40 PD3
Parallel Port

PARALLEL I/F
R104 100K_0402_5% NOT-FIR@ 24 49 LPD4
GPIO41 PD4 LPD5
2 1 25 50
+3VS GPIO42 PD5 LPD6
27 51
FIR_DET# GPIO43 PD6 LPD7 +5V_PRN

GPIO
28 53
GPIO44 PD7 LPTSLCT
29 55 D16
LPT_DET# GPIO45 SLCT LPTPE W=20mil
30 56 +5VS 2 1
R105 100K_0402_5% NOT-PIO@ GPIO46 PE LPTBUSY PIO@
31 57
GPIO47 BUSY LPTACK#
2 1 32 58 RB420D_SOT23 1
GPIO10 ACK#

1
R92 2 +3VS
1 1K_0402_5% SIO _GPIO11 33 59 LPTERR# PIO@
SIO@ R95 1 SIO@ SIO_SMI# GPIO11/SYSOPT ERROR# LPTAFD#
2 10K_0402_5% 34 60 R239 C264 RP32
+3VS R362 1 SIO@ SIO_IRQ GPIO12/IO_SMI# ALF# LPTSTB# 0.1U_0402_16V4Z
E 2 10K_0402_5% 35 61 PIO@ E
GPIO13/IRQIN1 STROBE# 2.2K_0402_5% 2 LPD3 F D3
36 1 8
R82 SIO _GPIO23 GPIO14/IRQIN2 LPD2 F D2
1 SIO@ 2 10K_0402_5% 40 2 7

2
GPIO23 LPD1 F D1
W=20mil LPD0
3 6
F D0
8 7 +3VS 4 5
VSS VTR LPTSTB# 1 +5V_PRN_R
22 11 2
VSS VCC PIO@ R238 33_0402_5% PIO@ 33_1206_8P4R_5%
43
VSS POWER VCC
26
52 45 J P1
VSS VCC RP35
54
VCC LPD7 F D7
1 1 8
CLK_14M_SIO CLK_PCI_SIO LPC47N217_STQFP64 SIO@ LPTAFD# 1 2 AFD/3 M# 14 LPD6 2 7 F D6
PIO@ R235 33_0402_5% F D0 2 LPD5 3 6 F D5
2

Base I/O Address LPTERR# 15 LPD4 4 5 F D4

R81 R110 * 0 = 02Eh F D1 3
10_0402_5% 33_0402_5% 1 = 04Eh LPT_INIT# 16 PIO@ 33_1206_8P4R_5%
@ @ F D2 4
D SLCTIN# 17 LPTINIT# 1 2 LPT_INIT# D
1

2 2 F D3 5 PIO@ R237 33_0402_5%

18
C 47 C81 F D4 6 LPTSLCTIN# 1 2 SLCTIN#
@ 15P_0402_50V8J @ 22P_0402_50V8J 19 PIO@ R236 33_0402_5%
1 1 F D5 7
20
F D6 8
21 +5V_PRN
F D7 9
22
LPTACK# 10 RP33 C P8
23 1 8 F D0 AFD/3M# 1 8
LPTBUSY 11 2 7 F D1 LPTERR# 2 7
24 3 6 F D2 LPT_INIT# 3 6
C LPTPE 12 4 5 F D3 SLCTIN# 4 5 C
25 PIO@
LPTSLCT 13 PIO@ 2.7K_1206_8P4R_5% 220P_1206_8P4C_50V8K

RP34 CP10
PIO@ FOX_DZ11391-H7 1 8 F D7 LPTACK# 1 8
2 7 F D6 LPTBUSY 2 7
3 6 F D5 LPTPE 3 6
4 5 F D4 LPTSLCT 4 5
PIO@
PIO@ 2.7K_1206_8P4R_5% 220P_1206_8P4C_50V8K

RP31 C P9
1 8 SLCTIN# F D0 1 8
2 7 LPT_INIT# F D1 2 7
3 6 LPTERR# F D2 3 6
B Place on the TOP side(Under MDC conn.) 4 5 AFD/3 M# F D3 4 5 B
L: R POP; PIO Enable PIO@
H: R De-POP PIO Disable PIO@ 2.7K_1206_8P4R_5% 220P_1206_8P4C_50V8K
+5VS
RP36 C P7
1 8 LPTACK# F D4 1 8
J P9 2 7 LPTBUSY F D5 2 7
1 LPT_DET# 1 2 3 6 LPTPE F D6 3 6
1 PIO@ R113 0_0402_5% LPTSLCT F D7
2 4 5 4 5
RXD1 2 PIO@
3
TXD1 3 PIO@ 2.7K_1206_8P4R_5% 220P_1206_8P4C_50V8K
4
D SR#1 4
5
RTS#1 5
6
CTS#1 6
7
DTR#1 7
A RI#1
8
9
8 Compal Electronics, Inc. A
DC D#1 9 Title
10
10
@ E&T_96212-1011S
SMsC LAP47N217 SIO,PIO,FIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.1
For SW debug use when no seial port Cus tom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS EAL20 LA-2462
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Friday, September 17, 2004 Sheet 33 of 47
10 9 8 7 6 5 4 3 2 1
 A B C D E

+3VALW +EC_RTCVCC 1 2
+EC_AVCC R56 0_0402_5%
+3VALW
JP23 For EC Tools
0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z 1 2 1
+3VALW + RTCVCC 1 +3VALW
1 1 1 1 1 1 2 R59 @ 0_0402_5% 2

ECA GND
2
C105 C367 C372 C371 C462 C427 C31
For ENE KB910 Rev.B4 3
3
4
4
1U_0603_10V4Z 5
2 2 2 2 2 2 1 5
6
6
7

123
136
157
166

161

159
4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 7 E51_RXD

16
34
45

95

96
8
U35 KSO[0..15] 8 E51_TXD
KSO[0..15] <36> 9
9
15 10

VCCA

VCCBAT
VCC
VCC
VCC
VCC
VCC
VCC
VCC

AGND

BATGND
L23 <23,33> LPC_AD0 LAD0 KSI[0..7] 10
1 2 14 49 KSO0 KSI[0..7] <36>
+3VALW +EC_AVCC <23,33> LPC_AD1 LAD1 GPOK0/KSO0
FBM-L11-160808-800LMT_0603 2 1 13 50 KSO1 @ E&T_96212-1011S
<23,33> LPC_AD2 LAD2 GPOK1/KSO1 ADB[0..7]
10 51 KSO2
1 C463 <23,33> LPC_AD3 LAD3 GPOK2/KSO2 ADB[0..7] <35> +3VALW 1
C467 KSO3
LFRAME# LPC Interface
<23,33> LPC_FRAME# 9 52
0.1U_0402_16V4Z GPOK3/KSO3 KSO4 KBA[0 ..18]
<22,26,33> B_PCIRST# 165 53 KBA[0..18] <35>
1 2 LRST#/GPIO2C GPOK4/KSO4

ENE-KB910-B4
L8 CLK_PCI_ LPC 18 56 KSO5
ECA GND <12> CLK_PCI_LPC LCLK GPOK5/KSO5 KSO6 KBA5
1 2 <22,28,33> S IRQ 7 57 1 2
FBM-L11-160808-800LMT_0603 1000P_0402_50V7K SERIRQ GPOK6/KSO6 KSO7 R348 1K_0402_5%
<23,26,30,33> PM_CLKRUN# 25 58
CLKRUN#/GPIO0C * GPOK7/KSO7 KSO8 KBA4
24 59 1 2
LPCPD#/GPIO0B * GPOK8/KSO8 KSO9 R55 1K_0402_5%
60
FRE AD# GPOK9/KSO9 KSO10 KBA1
<35> FR EAD# 150 61 1 2
F WR# RD# GPOK10/KSO10 KSO11 R57 1K_0402_5%

Internal Keyboard
<35> F WR# 151 64
FSEL# WR# GPOK11/KSO11 KSO12
<35> FSEL# 173 65 1 2
+5VS MEMCS# GPOK12/KSO12 KSO13 R622 @ 10K_0402_5%
152 66
ADB0 IOCS# GPOK13/KSO13 KSO14
138 67 1 2
R P3 ADB1 D0 GPOK14/KSO14 KSO15 R623 @ 10K_0402_5%
139 68
PSCLK1 ADB2 D1 GPOK15/KSO15
1 8 140 153 1 2
PSDATA1 ADB3 D2 GPOK16/KSO16 KSO17 R624 @ 10K_0402_5%
2 7 141 154 KSO17 <36>
TP_DATA ADB4 D3 GPOK17/KSO17
3 6 144
TP_CLK ADB5 D4 KSI0 SKU_ID0
4 5 145 71 1 2
D5 GPIK0/KSI0

X-BUS Interface
ADB6 146 72 KSI1 R625 10K_0402_5%
10K_1206_8P4R_5% ADB7 D6 GPIK1/KSI1 KSI2 SKU_ID1
147 73 1 2
KBA0 D7 GPIK2/KSI2 KSI3 R626 10K_0402_5%
124 74
A0 GPIK3/KSI3
1 2 PSDATA2 KBA1 125 77 KSI4 SKU_ID2 1 2
R111 10K_0402_5% KBA2 A1/XIOP_TP GPIK4/KSI4 KSI5 R627 10K_0402_5%
126 78
A2 GPIK5/KSI5
1 2 PSCLK2 KBA3 127 79 KSI6
R114 10K_0402_5% KBA4 A3 GPIK6/KSI6 KSI7
128 80
KBA5 A4/DMRP_TP GPIK7/KSI7
131
KBA6 A5/EMWB_TP
132 32 INVT_PWM <20>
KBA7 A6 GPOW0/PWM0
133 33 BEEP# <31>
+3VALW KBA8 A7 GPOW1/PWM1
143 36 SUSP_LED <36>
KBA9 A8 FAN2PWM/GPOW2/PWM2
142 37 ACO FF <40>
A9
1 2 FSEL# KBA10 135
A10 Pulse Width GPOW3/PWM3
GPOW4/PWM4
38 PM_BATLOW# <23>
R353 10K_0402_5% KBA11 134 39
2 A11 GPOW5/PWM5 E C_ON <36> 2
1 2 MUL_KEY# KBA12 130 40
A12 GPOW6/PWM6 EC_LID_OUT# <23>
R387 10K_0402_5% KBA13 129 43
1 2 FRE AD# KBA14 121
A13 FAN1PWM/GPOW7/PWM7 S4_LATCH <36> Board ID
R316 10K_0402_5% KBA15 A14
120 2 O N/OFFBTN# <36>
EC_ SMI# KBA16 A15 GPWU0 +3VALW
1 2 113 26 A CIN <22,36,38>
R392 10K_0402_5% KBA17 A16 GPWU1
112 29 KILL_SW# <30,32>
KBA18 A17 GPWU2
104 30 SLP_S3# <23>

1
A18 GPWU3
103
A19 Wake Up Pin GPWU4
44 PM_SLP_S5# <23>
108 76 R135
+3VALW R375 2 1 10K_0402_5% EC_TINIT# 105
A20/GPIO23 GPWU5
172
SLP_S1# <12,23> Ra 10K_0402_5%
E51CS#/GPIO20/ISPEN TIN1/GPWU6 PCI_PME# <26,28,30>
176 BATT_TEMP <39>
PSCLK1 TIN2/FANFB2/GPWU7
110

2
PSDATA1 PSCLK1 ECA GND AD_BID0
111 81 1 2
PSCLK2 PSDAT1 GPIAD0/AD0 A DP_IR C110 0.01U_0402_16V7K 1 R141
114 82 2 ADP_I <40>

1
PSDATA2 PSCLK2 GPIAD1/AD1
PSDAT2PS2 Interface
115 83
<36> TP_CLK
TP_CLK 116
PSCLK3
GPIAD2/AD2
GPIAD3/AD3
84 AD_BID0
BATT_OVP <40> 10K_0402_5%
* Rb R140
+5VALW TP_DATA 117 Analog To Digital 87 0_0402_5%
<36> TP_DATA PSDAT3 GPIAD4/AD4 LI/NIMH# <39> 1
R P1 88
GPIAD5/AD5 S4_DATA <36>
8 1 EC_SMD_2 EC_SMC_1 163 89 MUL_KEY# C109

2
<35,39> EC_SMC_1 SCL1 GPIAD6/AD6 MUL_KEY# <36> 0.22U_0603_16V7K
7 2 EC_SMC_2 EC_SMD_1 164 90
<35,39> EC_SMD_1 SDA1 GPIAD7/AD7 2
6 3 EC_SMC_1 EC_SMC_2 169 SMBus
<4,31> EC_SMC_2 SCL2
5 4 EC_SMD_1 <4,31> EC_SMD_2 EC_SMD_2 170 99
SDA2 GPODA0/DA0 DA C_BRIG <20>
100
10K_1206_8P4R_5% GPODA1/DA1
8 101 I REF <40>
+3VALW S CI# GPIO04 GPODA2/DA2
<23> S CI# 20 102 EN _DFAN1 <4>
GPIO07 GPODA3/DA3
21
GPIO08 Digital To Analog GPODA4/DA4
1
CD_ PLAY <25>
1 2 LID_SW# 22 42
R371 20K_0402_5% ENBKL GPIO09 GPODA5/DA5
27 47
<13> ENBKL GPIO0D GPODA6/DA6 +3VALW
28 174
<20> B KOFF# GPIO0E GPODA7/DA7
<40> FS TCHG 48
CLK_PCI_ LPC EC_ SMI# GPIO10
<23> EC_SMI# 62 85 MODE_LED# <36>

1
3 EC_IDERST GPIO13 * GPIO18/XIO8CS# 3
<25,31> EC_IDERST 63 86 CHARGING_LED# <36>
GPIO14 * GPIO19/XIO9CS# R61
<30> W L_OFF# 69 91 DEV_LED# <36>
1

GPIO15 * GPIO1A/XIOACS#
<23> EC_RIOUT#
70
GPIO16 GPIO * GPIO1B/XIOBCS# 92 POWER_LED# <36> 100K_0402_5%
R366 SKU_ID2 75 Expanded I/O * GPIO1C/XIOCCS# 93 SKU_ID0
GPIO17 SKU_ID1
109 94

2
@ 10_0402_5% LID_SW# GPIO24 * GPIO1D/XIODCS#
<36> LID_SW# 118 97 WL_LED# <32> <26,28,30> PCM_PME#
GPIO25 * GPIO1E/XIOECS#
119 98 BATT_LOW_LED# <36>
2

GPIO26 * GPIO1F/XIOFCS#
1 148 F ANSPEED1 <4> <26,28,30> MINI_PME#
C433 <32,36,37,43> SYSO N GPIO27
<31,37,42,43,44> SUSP# 149 171
GPIO28 GPIO2E/TOUT1/FANFB1 1K_0402_5% 1
<37,45> V R_ON 155 12 2 R106
@ 10P_0402_50V8K GPIO29 DPLL_TP/GPIO06/FANFB3 1K_0402_5% 1 <26,28,30> ONBD_LAN_PME#
<25> PCMRST# 156 FANTEST_TP/GPIO05/FAN3PWM 11 2 R356
2 GPIO2A 0_0402_5% 1
162 2 R621 EAPD_KBC <32>
GPIO2B
<23> PWRBTN_OUT# 168 175 EC_THRM# <23>
GPIO2D
Timer Pin TOUT2/GPIO2F PCI_PME#
PADS_ LED# 55 3
<36> PADS_LED# FnLock#/GPIO12 * E51IT0/GPIO00 PM_RSMRST# <23>
CAPS_ LED# 54 4 S HDD_LED#
<36> CAPS_LED# CapLock#/GPIO011 * E51IT1/GPIO01 SHDD_LED# <25>
NUM_LED# 23 106 E51_RXD
<36> NUM_LED# NumLock#/GPIO0A * E51RXD/GPIO21/ISPCLK
reserved for GMCH R367 P HDD_LED# 41 107 E51_TXD
<25> P HDD_LED# ScrollLock#/GPIO0F * E51TXD/GPIO22/ISPDAT
1 2 EC_RST# 19 MISC
+3VALW ECRST#
47K_0402_5% GATEA20 5 158 CRY1
<22> GATEA20 GA20/GPIO02 XCLKI
2 1 R C# 6 160 CRY2 R344 2 1
<22> R C# KBRST#/GPIO03 XCLKO
C439 31 @ 20M_0603_5%
GND
GND
GND
GND
GND
GND

ECSCI#

10P_0402_50V8K
0.1U_0402_16V4Z 1 R340 2
1 2 ENBKL 0_0402_5% 1 1
<7> GMCH_ENBKL

10P_0402_50V8K
R115 0_0402_5% UMA@ KB910Q B4_LQFP176 C376 C364
17
35
46
122
137
167

1
OUT

IN
2 2

NC

NC
4 4

2
Y2
32.768KHZ_12.5P_1TJS125DJ2A073

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC KB910(LPC)
Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Cus tom EAL20 LA-2462
Date: Friday, September 17, 2004 Sheet 34 of 47
A B C D E
 1 2 USB_EN
<37> SYSON#
R342 0_0402_5%

+USB_VCCA +3VALW +USB_VCCC +3VALW

1
R296 R599
U27 U47 100K_0402_5%
1 8 100K_0402_5% 1 8
GND OUT GND OUT
+5VALWP 2 7 +5VALWP 2 7

2
IN OUT R295 R298 IN OUT R598 R600
3 6 OVCUR#2 <23> 3 6
USB_EN IN OUT USB_EN IN OUT
4 5 1 2 1 2 OVCUR#3 <23>
4 5 1 2 1 2 OVCUR#4 <23>
EN# FLG EN# FLG
1 1
C309 G528_SO8 @ 0_0402_5% 47K_0402_5% C667 G528_SO8 @ 0_0402_5% 47K_0402_5%
1 1
4.7U_0805_10V4Z C307 4.7U_0805_10V4Z C668
2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2
Close to JP21
Close to JP20

USB CONN. 3
USB CONN. 1 USB CONN. 2
+USB_VCCA +USB_VCCA
W=40mils W=40mils
+USB_VCCA +USB_VCCB +USB_VCCC
W=40mils
1 1
1 1 1 1 +USB_ VCCC
C296 + C277 C281 C276 C280 + C295 1
150U_D2_6.3VM 1 1
0.1U_0402_16V4Z 1000P_0402_50V7K 1000P_0402_50V7K 0.1U_0402_16V4Z 150U_D2_6.3VM C257 + C258 C256
2 2 2 2 2 2 150U_D2_6.3VM
0.1U_0402_16V4Z 1000P_0402_50V7K
JP5 2 2 2
5 1
VCC VCC JP21
<23> USB20P3- 6 2 USB20P2- <23>
D1- D0-
<23> USB20P3+ 7 3 USB20P2+ <23>
D1+ D0+ 1
8 4 <23> USB20P4-
C279 VSS VSS 2
1 1 C278 1 C13 1 C12 <23> USB20P4+ 3

10P_0402_50V8K

10P_0402_50V8K

10P_0402_50V8K

10P_0402_50V8K
9 10
G1 G2 4
11
G3 G4
12 1 C670 1 C669

10P_0402_50V8K

10P_0402_50V8K
@ @ @ @ SUYIN_2569A-04G3T
2 2 SUYIN_020122MR008S540ZU 2 2
@ @
2 2

KBA[0..18]
512kB Flash ROM <34> KBA[0..18]
<34> ADB[0..7]
ADB[0 ..7]

+3VALW
F D4 F D3 F D1 FD2 F D5 F D6

1 2 C102
0.1U_0402_16V4Z

1
U4

KBA18 1 32 C F8 C F6 C F4 CF19 CF14 C F7 C F3 CF22 C F2 CF18 CF12 CF21 C F1

KBA16 NC VCC F WE#
2 31 1 1 1 1 1 1 1 1 1 1 1 1 1
KBA15 A16 WE* KBA17
3 30
KBA12 A15 A17 KBA14
4 29
KBA7 A12 A14 KBA13
5 28
KBA6 A7 A13 KBA8 C F9 CF20 C F5 CF17 CF11 CF15 CF10 CF16 CF13
6 27
KBA5 A6 A8 KBA9
7 26 1 1 1 1 1 1 1 1 1
KBA4 A5 A9 KBA11
8 25
KBA3 A4 A11 FREAD#
9 24 FREAD# <34>
KBA2 A3 OE* KBA10
10 23
KBA1 A2 A10 FSEL#
11 22 FSEL# <34>
KBA0 A1 CE* ADB7 H9 H8 H7 H16 H15 H19 H18 H20 H3 H17 H12
12 21
AD B0 A0 DQ7 ADB6 H_S315D126 H_S315D126 H_S315D126 H_S315D126 H_S315D126 H_S315D126 H_S315D126 H_S315D126 H_S315D161 H_S315D161 H_S315D161
13 20
AD B1 DQ0 DQ6 ADB5
14 19
AD B2 DQ1 DQ5 ADB4
15 18
DQ2 DQ4 ADB3
16 17
1

1
VSS DQ3

29F040/SST39VF040_PLCC

+3VALW H2 H5 H23 H6 H1 H4
H_O126X157D126X157N H_C126D126N H_C126D126N H_O157X126D157X126N H_T236D161 H_T236D161
20K_0402_5%
1

+3VALW
1

1
R94
SUS_STAT# <13,23>
2

+3VALW +3VALW Q31

G
14

U9B 2N7002_SOT23
New Screw Hole
2

4 1 3 H10 H11 H14 H13

P
1

F WE# A EC_FLASH# <23> H_C394D122 H_C394D122 H_C394D122 H_C394D122

6
D

O
1 2 C356 R332 5 H24 H25 H21 H22
G

0.1U_0402_16V4Z 10K_0402_5% B H_O79X126D40X87 H_O79X126D40X87 H_S276D118 H_S276D118

SN74LVC32APWLE_TSSOP14
7

1
U31
2

8 1

1
VCC A0 FW R# <34>
7 2
WP A1
<34,39> EC_SMC_1 6 3
SCL A2
<34,39> EC_SMD_1 5 4
SDA GND
1

AT24C16N-10SI-2.7_SO8
R334 R326 Compal Electronics, Inc.
1K_0402_5% 1K_0402_5% Title

BIOS/WL-SW/Screw Hole/USB
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
D ate: Friday, September 17, 2004 Sheet 35 of 47
 +3VALW
LID Switch KSI[0..7]
KSI[0..7] <34>
ON/OFF BUTTON INT_KBD CONN.

1
KSO[0 ..15]
+3VALW KSO[0..15] <34>
R363

100K_0402_5% DAN202U_SC70 for ON/OFF switch KEYBOARD CONN.

1
D 19

2
2 S W1 R219 ACES_88172-3400
<34> LID_SW#
1 1 2 J-PB J OPEN 100K_0402_5%
S4_LI D_SW# 3 2 1 37 38

1
D11 34 NUM_LED#

2
NUM_LED# <34>
2 ON/OFFBTN# PADS_ LED#
33
ON/OFFBTN# <34> <34> PADS_LED#
D5 ON/O FF 1 32 CAPS_ LED#
CAPS_LED# <34>
V-PORT-0603-220 M-V05_0603 3 4 3 5 1_ON# 2 R226 1 31
51_ON# <38> +3VS
@ ESE11MV9_4P 300_0402_5% 30 KSO15
+3VALW DAN202U_SC70 KSO14 29

2
28 KSO10
KSO11 27

1
1 26 KSO8

1
R216 D10 KSO9 25
4.7K_0402_5% Q12 RLZ20A_LL34 24 KSO13
C231 KSI7 23
2 0.01U_0402_16V7K

DTC124EK_SC59
22 KSO3

2
1 R213 2 2 KSO7 21
<34> E C_ON 0_0402_5% KSO12
20
KSI4 19
18 KSI6
KSI5 17

3
16 KSO6

1
D KSO5
SW/LED Connector C613 0.1U_0402_16V4Z Q13 2
15
14 KSI3
1 2 G KSI0 13
JP15 @ 2N7002_SOT23 S WHEN R=0,Vbe=1.35V 12 KSO0

3
1 WHEN R=33K,Vbe=0.8V KSO1 11
1 +5V KSI1
2 MODE_LED# <34> 10
2 KSI2
3 DEV_LED# <34> 9
3 PWR_LED# KSO2
4 8
4 PWR_SUSP_LED KSO4
5 7
5 EC_ STOPBTN#
6 KSI1 <34> 6 1 R214 2
6 EC_PLAYBTN# 300_0402_5% +3VS
7 KSI0 <34> 5
7 E C_FRDBTN#
8 KSI3 <34> 4
8 EC_REVBTN#
9 KSI2 <34> D9 3
9 EC_ UTXD/KSO17 R227
10 KSO17 <34> 2
10
11 3 5 1_ON# 1 2 2 1 1
11 MUL_KEY_ESD# R233 0_0603_5% +3VS 300_0402_5%
12 1 35 36
12 ON/O FF
13 2 MUL_KEY# MUL_KEY# <34>
13 JP17
14
14 AO3402_SOT23
ACES_85203-1402 DAN202U_SC70

S
+5VALW 1 3
Q18 +5V
@
Touch Pad Connector 1
C250

G
2
ACES_85203-1202
+5VS <37> SU SON 0.1U_0402_16V4Z
24 12
24 12 2
23 11 TP_CLK <34>
23 11
22 10 2 2 1PADS_ LED# NUM_LED# 1 2
22 10 TP_DATA <34> C232 100P_0402_50V8J C329 C676 100P_0402_50V8J
21 9
21 9 +5VS
20 8 2 1 KSO14 CAPS_ LED# 1 2
20 8 +5V 0.1U_0402_16V4Z 100P_0402_50V8J C680 C685 100P_0402_50V8J
19 7 +5VALW
19 7 1
18 6 A CIN <22,34,38> 2 1 KSO11 KSO15 1 2
18 6 PWR_LED# 100P_0402_50V8J C689 C694 100P_0402_50V8J
17 5 POWER_LED# <34>
17 5 PWR_SUSP_LED
16 4 SUSP_LED <34> 2 1 KSO9 KSO10 1 2
16 4 100P_0402_50V8J C672 C684 100P_0402_50V8J
15 3 CHARGING_LED# <34>
15 3 KSI7 KSO8 1
14 2 BATT_LOW_LED# <34> 2 1 2
14 2 100P_0402_50V8J C681 C693 100P_0402_50V8J
13 1
13 1
2 1 KSO7 KSO13 1 2
JP16 100P_0402_50V8J C690 C677 100P_0402_50V8J
2 1 KSI4 KSO3 1 2
100P_0402_50V8J C673 C686 100P_0402_50V8J
2 1 KSI5 KSO12 1 2
Battery mode Hibernation 100P_0402_50V8J
2
C682
1 KSO5 KSI6
C695
1
100P_0402_50V8J
2
RTC VREF 100P_0402_50V8J C691 C678 100P_0402_50V8J
RTC VREF 2 1 KSI0 KSO6 1 2
100P_0402_50V8J C674 C687 100P_0402_50V8J
RT CVREF D14 2 1 KSO1 KSI3 1 2
1

1N4148_SOT23 100P_0402_50V8J C683 C696 100P_0402_50V8J

680K_0402_5% C242 0.1U_0402_16V4Z 2 1 KSI2 KSO0 1 2
1 2 ON/O FF 100P_0402_50V8J C692 C679 100P_0402_50V8J
1

2 1 KSO4 KSI1 1 2
R218 R220 R225 100P_0402_50V8J C675 C688 100P_0402_50V8J
KSO2 1 2
5

100K_0402_5% 100K_0402_5% U22 C697 100P_0402_50V8J

1

D
P
2

1 2 2 4 1 2 2 Q16
A Y R222 G 2N7002_SOT23
G
1

D C236 1U_0603_10V6K 10K_0402_5% S

3

S4_LID_SW# 2 Q14 NC7SZ14M5X_SOT23-5

Power OK Circuit
3

G 2N7002_SOT23
S
3

+3VS
1

<32,34,37,43> SYSO N 2 +3VALW +3VALW

G

1
Q17 S
3

2N7002_SOT23 R212
180K_0402_5% SN74LVC14APWLE_TSSOP14

14

14
RTC VREF 1 2 1 2 U 17C U 17D
R224 C246 1U_0603_10V4Z

P
2
10K_0402_5% 5 6 9 8
RTC VREF I O I O PM_POK <23,45>

G
R228 U 23 0.1U_0402_16V4Z 1

1
1 2 1 14 1 2

7
10K_0402_5% CD1# VCC C247 C229 R188
2 13
D1 CD2# 1U_0603_10V4Z 100K_0402_5%
<34> S4_LATCH 3 12
CP1 D2 2
RTC VREF 1 2 4 11
R229 SD1# CP2 SN74LVC14APWLE_TSSOP14
1 5 10

2
10K_0402_5% C248 Q1 SD2#
6 09
Q1# Q2
7 08
1U_0805_25V4Z @ GND Q2#
2 74LCX74MTC_TSSOP14

+3VALW 1 2 1
R231 Q15
Compal Electronics, Inc.
1

10K_0402_5% D 15 D C233
2 1 D_SET_S4 2 @ 220P_0402_50V7K Title
<34> S4_DATA 2
G
RB751V_SOD323 2N7002_SOT23 S S4R,LID,PIO,SYS CONN
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number R ev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
Date: Friday, September 17, 2004 Sheet 36 of 47
 A B C D E

+3VALW to +3V Transfer +5VALW to +5VS Transfer

+5VALW +5VS
+3VALW +3V
U19
U29 +12VALW 8 1
1 +12VALW D S 1
8 1 7 2
D S D S
7 2 1 6 3

1
D S D S
1 6 3 5 4 1 1

1
C327 D S R618 C226 D G C214 R204
5 4 1 1
R476 D G C323 C330 R318 100K_0402_5% SI4800DY_SO8 C218 470_0402_5%
100K_0402_5% SI4800DY_SO8 470_0402_5% 2 10U_0805_10V4Z 10U_0805_10V4Z
2 10U_0805_10V4Z 2 2

0.1U_0402_16V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z

1 2
2 2
2

1 2
5 VS_ON D
SUSON D Q8 +5VALW
<36> SUSON 2 SUSP
2 SYSON# 1 2N7002_SOT23 G

1
G D C700
1 S

3
1

1
D Q30 C332 Q29 SUSP Q44
S 2

3
SYSON# 2 2N7002_SOT23 G 2N7002_SOT23 0.01U_0402_16V7K R211
G 0.01U_0402_16V7K S 2 100K_0402_5%

3
S 2N7002_SOT23 2
3

2
SYSON#
<35> SYSON#

1
D
SY SON 2 Q10
<32,34,36,43> SY SON
G 2N7002_SOT23
S

3
+3VALW to +3VS Transfer +1.5VALW to +1.5VS Transfer
2 2
+5VALW
+3VALW +3VS

1
U40 +1.5VALW +1.5VS
+12VALW 8 1 R210
D S U3 100K_0402_5%
7 2
D S
1 6 3 8 1
1

1
D S D S
5 4 1 1 7 2

2
1
R466 C525 D G R431 D S
6 3 1 1
100K_0402_5% SI4800DY_SO8 C506 C498 @ 470_0402_5% D S R33
5 4
2 10U_0805_10V4Z 10U_0805_10V4Z D G C22 C23 @ 470_0402_5% SUSP
2 2 <44> SUSP
1 1 1 SI4800DY_SO8 22U_1206_16V4Z_V1
2

1 2
C21 C20 2 2
0.1U_0402_16V4Z

1
R U N ON D C19 D
0.1U_0402_16V4Z 2 SUSP 10U_0805_10V4Z 10U_0805_10V4Z 2 Q11
<31,34,42,43,44> SUSP#

1
G 2 2 2 D G 2N7002_SOT23
1
1

D C554 Q36 Q28 SUSP

S 2 S
3

3
SUSP 2 Q37 @ 2N7002_SOT23 10U_0805_10V4Z R U N ON G @ 2N7002_SOT23
G 2N7002_SOT23 0.1U_0402_16V4Z S

3
S 2
3

+5VALW

3 3

2
R208
remove on integrated VGA sku
10K_0402_5%

+2.5V to +2.5VS Transfer

1
VR _ON#
<44> VR_ON#

1
D
2 Q9
+2.5V +2.5VS <34,45> VR_ON G 2N7002_SOT23
S

3
U 6 M11@
8 1
D S
7 2
D S
1 6 3
1

D S
5 4 1 1
C44 D G M11@ M11@ R51
M11@ SI4800DY_SO8 C25 C26
2 10U_0805_10V4Z @ 470_0402_5%
2 2
1 2

10U_0805_10V4Z R U N ON
D
0.1U_0402_16V4Z 2 SUSP
G Q4
S @ 2N7002_SOT23
3

4 4

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Interface
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
D ate: Friday, September 17, 2004 Sheet 37 of 47
A B C D E
 A B C D

VS

VIN V IN
PL1 1 2
P F1 FBM-L18-453215-900LMA90T_1812 P R1 1M_0402_1%

1
DC_IN_S1 1 2 DC_IN_S2 1 2

1
VS P R2
PJP1 7A_24VDC_429007 P R3
5.6K_0402_5%

1
1 1 84.5K_0402_1% 1 2

2
1

1
P C1 P R4 A CIN 22,34,36

8
1000P_0402_50V7K P C2 P C3 P C4 PU1A 1K_0402_5%

2
3 2 100P_0402_50V8J 1000P_0402_50V7K 100P_0402_50V8J 1 2 3

P
G

2
2 +
4 G P R5 22K_0402_1% 1 PAC IN
1
O PAC IN 40,41 1

2
-

G
1
1

1
SINGA_2DC-G213-B04 P R6 LM393M_SO8 P D1

4
P C5 P C6 P R7
1000P_0402_50V7K 20K_0402_1% 0.1U_0402_16V7K 10K_0402_5%

2
RLZ4.3B_LL34

2
P R8
2 1
Vin Detector
RTC VREF
10K_0402_5%
V IN 3.3V High 18.384 17.901 17.430
Low 17.728 17.257 16.976

2
P D2

1N4148_SOD80

1
P D3
2 1

1
BATT+
RB751V_SOD323 P R9
PQ1 VS
33_1206_5% 1 2
TP0610K_SOT23 PR10

2
1K_1206_5%
CH GRTCP 1 2 N1 3 1
PR11
200_0603_5% P D4
1

2 1 N3 1 2
VIN B+
1

1
2
PR13 PR12 2

P C7 P C8 1N4148_SOD80 1K_1206_5%
100K_0402_5% 0.22U_1206_25V7M 0.1U_0603_25V7K
2

2
2

36 51_ON# 1 2 1 2
PR14 22K_0402_5% PR15
1K_1206_5%
1

RT CVREF
PR16
P U2

1
S-812C33AUA-C2N-T2_SOT89 200_0603_5% 1 2 2 1
VL PR17 100K_0402_5% PR18 2.2M_0402_5% PR19
3.3V
2

PR20 PR21 499K_0402_1%

1 2 1 2 3 2 N2
+CHGRTC
1

OUT IN

2
1

8
200_0603_5% 200_0603_5% P D5 P D6 PU1B
1

GND P C9 RLZ16B_LL34 2 5

P
PC10 1U_0805_25V4Z 39,41 MAINPWON 1 7
+
2

10U_0805_10V4Z 1 O
3 6 2 PR22 1 VL
40 ACON
2

1
LM393M_SO8 -

1
RB715F_SOT323 34K_0402_1% PR23

4
1

1
PC11
PC13 PR24 499K_0402_1% 1000P_0402_50V7K

2
PC12 1000P_0402_50V7K 66.5K_0402_1% PR25

2
1000P_0402_50V7K 191K_0402_1%

2
P J1 P J2
3
+3VALWP 2 1 +3VALW +1.8VSP 2 1 +1.8VS 3
2 1 2 1
JUMP_43X118 JUMP_43X79
(5A,200mils ,Via NO.= 10) (1A,40mils ,Via NO.= 2)

1
P J3 D

+5VALWP 2 1 +5VALW P J4 PQ2

2 2 1 PAC IN
2 1 2N7002_SOT23
G PR26 47K_0402_5%
2 1
JUMP_43X118
+1.5VALWP 2 1 +1.5VALW Precharge detector S

3
(5A,200mils ,Via NO.= 10) JUMP_43X118
15.97V/14.84V FOR
P J5 (3.5A,140mils ,Via NO.= 7)

1
2 1
ADAPTOR PQ3
+12VALWP 2 1 +12VALW
DTC115EUA_SC70
P J6
JUMP_43X39
+1.25VSP 2 1 +1.25VS 2 +5VALWP
2 1
(120mA,40mils ,Via NO.= 2)
JUMP_43X118
P J7 (2A,80mils ,Via NO.= 4)
+2.5VP 2 1 +2.5V

3
2 1
JUMP_43X118 P J8
P J9 +1.35VSP 2 1 +1.35VS
2 1
2 1
2 1 JUMP_43X118
JUMP_43X118 (2A,80mils ,Via NO.= 4)
(8A,320mils ,Via NO.= 16)
PJ10
PJ11 +VGA_COREP 2 1 +VGA_CORE
2 1
+1.05VP 2 1 +VCCP
2 1 JUMP_43X118
4
JUMP_43X118 4

(3.5A,140mils ,Via NO.= 7) (5A,200mils ,Via NO.= 10)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE DCIN & DETECTOR
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY EAL20 LA-2462 0.1
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
I NC. Date: Friday, September 17, 2004 Sheet 38 of 47
A B C D
 A B C D

PH1 under CPU botten side :

CPU thermal protection at 84 degree C
Recovery at 45 degree C

1
VMB VL VS VL 1

PF2 PL2
PJP2 12A_65VDC_451012 FBM-L18-453215-900LMA90T_1812

2
BTC-07GR1 7P BATT_S1 1 2 1 2 BATT+
1K_0402_5% PR27

1
1 ALI/NIMH# 1 PR28 2
2 A B/I PR29 2 P H1 PC14 47K_0402_1%
1 +3VALWP M AINPWON 38,41
3

1
TS_A 47K_0402_5% 0.1U_0603_25V7K

1
4 EC_SMDA PC15 PC16 PR30

1
5 EC_SMCA 1000P_0402_50V7K 0.01U_0402_25V7Z 10KB_0603_1%_TH11-3H103FT 1 2

2
6 PR31 47K_0402_1% PQ4

8
7 1K_0402_5% PR32 DTC115EUA_SC70
1 2 3 PU3A P D7

P
2
16.9K_0402_1% +
1 2 1 2

2
2
TM_REF1 O
2

G
PR33 PR34 - 1SS355_SOD323
100_0402_5% 100_0402_5% LM393M_SO8

4
1

3
1 LI/NIMH# 34

1
PC17
PR36
PR35 PR37
2 1 0.22U_0805_16V7K_V2 3.32K_0402_1% 2 1
+3VALWP VL

1
100K_0402_1%
PC18

2
1
PR38 6.49K_0402_1% 1000P_0402_50V7K

1
1K_0402_5%
PR39
2

100K_0402_1%
2 2

2
BATT_TEMP 34

EC_SMD_1 34,35 PH2 near main Battery CONN :

EC_SMC_1 34,35 BAT. thermal protection at 79 degree C
Recovery at 45 degree C

VL VL

2
P H2 PR40
47K_0402_1%
10KB_0603_1%_TH11-3H103FT
PR41

1
1 2
47K_0402_1%
3
PR42 3

8
14.7K_0402_1% PU3B
1 2 5 P D8

P
+
7 2 1
TM_REF1 O
6

G
1
- 1SS355_SOD323

1
PC19 PR43 LM393M_SO8

4
0.22U_0805_16V7K_V2 3.48K_0402_1%

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE BATTERYCONN / OTP
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY EAL20 LA-2462 0.1
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
I NC. Date: Friday, September 17, 2004 Sheet 39 of 47
A B C D
 A B C D

Iadp=0~2.87A B+ PQ5
P2 P3 AO4407_SO8
1 8
PQ6 PQ7
2 7
AO4407_SO8 AO4407_SO8 PR44 PL3 3 6
8 1 1 8 2 1 FBM-L18-453215-900LMA90T_1812 5
VIN
7 2 2 7 1 2 B++
6 3 3 6 0.02_2512_1%

4
5 5

1
PC20 PC21 PC22

4
4.7U_1206_25V6K 4.7U_1206_25V6K 4.7U_1206_25V6K

2
1
1 1

PR45
1

3
PR46 PQ8 200K_0402_1%
47K_0402_5% DTA144EUA_SC70 PR47

2
47K

1
1 2 VIN
2 PC23 P U4 47K_0402_5%
47K

2
0.1U_0603_25V7K 1 24
34 ADP_I
2

3
2
1
-INC2 +INC2 PR48
PQ9 10K_0402_5%
2 1 2 23 AO4407_SO8
OUTC2 GND
1

PR49 100K_0402_5% PC24 N18 4 ACO FF#

1

1
0.022U_0402_16V7K
3 22 CS 1 2

1
PQ10 +INE2 CS
2 PC25

1
DTC115EUA_SC70 4 21 1 2

1
0.1U_0402_16V7K PR50 -INE2 VCC(o)

5
6
7
8
1
PC27 PR52 0.1U_0603_25V7K 2
1

D 1 ACO FF 34
PC26 PR51 33.2K_0402_1% 1 2 1 2 5 20
3

PQ12 PR53 10K_0402_1% 10K_0402_5% FB2 OUT PQ11

2

2
G 2N7002_SOT23 150K_0402_1% 4700P_0402_25V7K

2
S 6 19 1 2 LXCHRG DTC115EUA_SC70
3

3
VREF VH PC28
2

1
PC29 PC30 PR54 0.1U_0603_25V7K
PD12 0.1U_0402_16V7K 1 2 1 2 7 18 1 2
ACO FF#1 1K_0402_5% FB1 VCC PC31
2
CC=0.5~2.7A

2
1000P_0402_50V7K 0.1U_0603_25V7K
1SS355_SOD323 8 17 1 2
-INE1 RT PR55 CV=16.8V(12 CELLS LI-ION)
205K_0402_1% 68K_0402_5%
1

2 D 2

34 I REF 1 2 9 16
PAC IN 1 PQ13 PR56 +INE1 -INE3 PL4 PR58
38,41 PA CIN 2 2
PR57 G 2N7002_SOT23 PR60 PC32 1 2 1 2 BATT+
3K_0402_1% S 2 1 10 15 1 2 1 2 16UH_D104C-919AS-160M_3.7A_20%
3

1
PR59 10K_0402_5% OUTC1 FB3 47K_0402_5% 0.02_2512_1%

1
PR61 1500P_0402_50V7K 4.7U_1206_25V6K
AC ON PC33 11 14 AC ON
38 AC ON

1
100K_0402_1% OUTD CTL PD13 PC34 PC35 PC36

2
2

0.1U_0402_16V7K 12 13 EC31QS04 4.7U_1206_25V6K 4.7U_1206_25V6K

2
-INC1 +INC1
IREF=1.31*Icharge

2
MB3887_SSOP24
IREF=0.73~3.3V

+3VALWP
CS
PR62 PR63
4.2V
1

2 1 2 1
1

PR64
47K_0402_5% PQ14 95.3K_0603_0.1% 143K_0603_0.1%
DTC115EUA_SC70
PR65
2

2 2 1
1

95.3K_0603_0.1%
PQ15
DTC115EUA_SC70
3

3
34 F STCHG 2 3
VMB
3

PR66
340K_0402_1%
2

OVP voltage : LI
1

4S2P : 17.4V--> BATT_OVP= 1.935V +12VALWP PR67

499K_0402_1%
(BAT_OVP=0.1111 *VMB)
2
8

PU5A
LM358A_SO8 3
P

+
1
34 BATT_OVP 0
2
G

-
4
1

PR68
1

PR69 PC37

2.2K_0402_5% 0.01U_0402_25V7Z
2

105K_0402_1%
2

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CHARGER
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY EAL20 LA-2462 0.1
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
I NC. Date: Friday, September 17, 2004 Sheet 40 of 47
A B C D
 5 4 3 2 1

PC38
N4 1 2

1
PD14

2
4.7U_1206_25V6K
PC39
B+++ 470P_0805_100V7K EC11FS2_SOD106

1
PJ17 1 2 PC40 BST31 BST51

2
2 1 0.1U_0603_25V7K SNB 2 1 FL YB ACK
D B+ 2 1 D
PR70 22_1206_5%

2
JUMP_43X118 PT1

8
7
6
5
1

1
PC42 PQ16

D
D
D
D

2
PC41 SI4800DY-T1_SO8 PD15
4.7U_1206_25V6K VS
2

2
4.7U_1206_25V6K DAP202U_SOT323 1 2 PC43 10uH_SDT-1205P-100-118_5A_20%

3
G
S
S
S
0.1U_0603_25V7K B+++

1
2
3
4

1
PD16 VL
PLX3

5
6
7
8
1SS355_SOD323 +12VALWP PQ17

8
7
6
5

D
D
D
D
1

1
PQ18 SI4800DY-T1_SO8

D
D
D
D

1
SI4810DY_SO8 PC44 PC45

1
PC46 4.7U_1206_25V6K 4.7U_1206_25V6K

G
1

S
S
S
4.7U_0805_6.3V6K PR71

2
G

1
S
S
S
PC47

4
3
2
1
0.1U_0603_25V7K PC48 1.27K_0402_1%

1
2
3
4

2
1

PC49 4.7U_1206_25V6K

PD H3

2
1

47P_0402_50V8J PDL3
PL6 PD H5

5
6
7
8

1
10UH_D104C-919AS-100M_4.5A_20% PR72
2

2 1 PC50

D
D
D
D
1.87K_0402_1% 47P_0402_50V8J
2

2
22

21
2

1
PC51 P U6 PQ19

1
S
S
S
PR73 25 4 SI4810DY_SO8

V+

VL
3.74K_0402_1% 0.47U_0603_16V7K BST3 12OUT PR74
5

4
3
2
1
2

VDD
PR76 27 18
C DH3 BST5 2M_0402_1% C
16
1

1M_0402_1% DH5 PLX5

2 1 26 17

2
LX3 LX5 PDL5
24 19
+3VALWP PR75 DL3 DL5
20
1

0_0402_5% PGND
14
PR77 CS H3 CSH5 CS H5
1 13
CSL3 CSH3 CSL5
2 1.24K_0402_1%
1 2 12

1
CSL3 FB5
3 15

1
3.32K_0402_1% FB3 SEQ PC52 PR79
1 38,40 PAC IN 1 2 10 9 +2.5VREF
1

470U_6.3V_M PD17 PR78 SKIP# REF 1.82K_0402_1%

23 6
SHDN# SYNC
1

+ PR80 10K_0402_5% 11 0.47U_0603_16V7K

2
1
PC54 RST#
7

2
PC53 SKUL30-02AT_SMA 100P_0402_50V8J TIME/ON5 PC55
2

2 28 4.7U_0805_6.3V6K

GND
2

2
RUN/ON3 +5VALWP

PR81
1

1
MAX1902EAI_SSOP28

1
VS 1 2 PC56 PR82 1
2

1
1000P_0402_50V7K PC57 470U_6.3V_M PD18
2

PR83 47K_0402_5% 10.2K_0402_1% 100P_0402_50V8J PC58 +

2
2
1

10K_0402_1% SKUL30-02AT_SMA
PC59 2
1

2
1
@ 0.047U_0402_16V4Z
2

PR84

2 1 VL
PR85 10K_0402_1%

2
220K_0402_5%

B B
MA INPWON 38,39
1

PC60
0.47U_0603_16V7K
2

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE 5V/3.3V/12V
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY EAL20 LA-2462 0.1
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
I NC. Date: Friday, September 17, 2004 Sheet 41 of 47
5 4 3 2 1
 A B C D

PL7
FBM-L18-453215-900LMA90T_1812
1 2 B+

1
PC61

1
4.7U_1206_25V6K PR86 PC62

1
4.7U_1206_25V6K
0_1206_5% PC63

2
4.7U_1206_25V6K

2
1
+5VALWP 1

2
PD19

1
DAP202U_SOT323 PC64 PR87 PC65

2.2U_0805_10V6K

2
0.1U_0603_25V7K 2.2_0603_5%

1
2

3
8
7
6
5
+1.35V

D
D
D
D
PQ20
SI4800DY-T1_SO8

14

28
G
S
S
S
+1.35VSP PL8 PC66 P U7 PC67

5
6
7
8
3UH_SPC-07040-3R0_5A_30% 2 1 12 17 2 1

VIN

VCC
1
2
3
4
0.01U_0402_25V7Z SOFT1 SOFT2 0.01U_0402_25V7Z

D
D
D
D
1 2 PHASE1
PR88 PQ21
1 2 1 1 2 6 23 1 2 2 1 SI4800DY-T1_SO8

G
8
7
6
5
BOOT1 BOOT2

S
S
S
PR89
PC70 + PC68 0_0603_5% 0_0603_5% PC69 +1.5V

D
D
D
D

4
3
2
1
0.1U_0402_16V7K 0.1U_0402_16V7K
470U_6.3V_M 0.01U_0402_25V7Z PQ22 N9 5 24 N11 PL9 +1.5VALWP
2 SI4800DY-T1_SO8 UGATE1 UGATE2 3UH_SPC-07040-3R0_5A_30%

G
1

S
S
S
PC71 4 25 PHASE2 1 2
PHASE1 PHASE2

1
2
3
4
PR90 PR92
2

5
6
7
8
2
4.99K_0402_1% 2K_0402_1% 2

1 PR91
2 7 22 1 2 0.01U_0402_25V7Z

D
D
D
D
2

2K_0402_1% ISEN1 ISEN2 PQ23 PC73 1

N10 2 27

1
LGATE1 LGATE2 SI4800DY-T1_SO8 PC72 +

1
S
S
S
470U_6.3V_M

4
3
2
1

2
3 26 PR93 2
PGND1 PGND2 N12 6.81K_0402_1%

2
9 20
VOUT1 VOUT2
10 19
SUSP# VSEN1 VSEN2
1 2 8 21 1 PR95 2 +3VALWP

1
31,34,37,43,44 SUSP# PR94 EN1 EN2
15 16
1

1
PG1 PG2/REF 10K_0402_1% PR96

GND

DDR
PR97 0_0402_5% PC75
11 18
PC74 OCSET1 OCSET2 @ 0.1U_0402_16V7K 10K_0402_1%

2
1
10K_0402_1% ISL6227CA-T_SSOP28

13

2
1
@ 0.1U_0402_16V7K
2

PR99 PR98
71.5K_0402_1%
71.5K_0402_1%

2
2

3 3

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE 1.35V/1.5V
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY EAL20 LA-2462 0.1
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
I NC. Date: Friday, September 17, 2004 Sheet 42 of 47
A B C D
 5 4 3 2 1

PR100
PJ12
1 2 2 1 +5VS
2 1

2
1@ 10_0603_5% JUMP_43X118

1
PC76 1
PD20 PC78

1
1@ 1U_0603_6.3V6M 1@ 1N4148_SOD80 1@ 4.7U_1206_25V6K + PC77

2
2
1@ 470U_6.3V_M

1
1
PR101 PC79

2
5
6
7
8
1@ 470P_0402_50V8J 2

5
1@ 6.81K_0402_1% P U8

D
D
D
D
2
1@ 0.1U_0402_16V7K

VCC
1
D D

1
PC80 PQ24
1 1@ SI4800DY-T1_SO8

G
BOOT

S
S
S
7

2
OCSET

4
3
2
1
PL10
PR102 2
UGATE

1
1@ 100K_0402_5% D 1@ 1.8UH_D104C-919AS-1R8N_9.5A_20%
VL 2 1 2 PQ25 6 2 1 +VGA_COREP
G 1@ 2N7002_SOT23 FB
S 8

5
6
7
8
PR103 PHASE
1

1
1@ 0_0402_5% D

D
D
D
D
1 2 2 PQ27 + PC81
31,34,37,42,44 SUSP#
G 1@ 2N7002_SOT23 3 4 PQ26 1@ 470U_6.3V_M
GND LGATE 1@ SI4810DY_SO8
S

G
S
S
S
2
2
1 @ APW7057KC-TR_SOP8

4
3
2
1
PC82
1

@ 0.1U_0402_16V7K PR104
1@ 5.36K_0402_1%
1 2

2
PR105 PR106 PC84
1@ 20.5K_0402_1% 1@ 20.5K_0402_1% 1 2
PC83

1
@ 0.1U_0402_16V7K 1@ 0.1U_0402_16V7K

1 1

1
PR143
1 @ 100K_0402_5% D
VL 2 1 2 PQ28
C G 1@ 2N7002_SOT23 C
S

3
1

D
2 PQ43
13 POWER_SEL G 1@ 2N7002_SOT23
S PR107
3

Low:1.2V PJ13
High:1.0V 1 2 2 1 +5VALWP
2 1

2
10_0603_5% JUMP_43X118

1
PC85 1

1
PD21
1U_0603_6.3V6M 1N4148_SOD80 PC86 + PC87

2
2
4.7U_1206_25V6K 220U_6.3VM_R15

2
1
PR108 PC88

5
6
7
8
470P_0402_50V8J 2

5
6.81K_0402_1% P U9 PC89 PQ29

D
D
D
D
2
0.1U_0402_16V7K SI4800DY-T1_SO8

VCC
1

1
1

G
BOOT

S
S
S
7

2
OCSET

4
3
2
1
PL11
2
UGATE 1.8UH_D104C-919AS-1R8N_9.5A_20%
PR109 6 2 1 +2.5VP
1

100K_0402_5% D FB
VL 2 1 2 PQ30 8

5
6
7
8
G 2N7002_SOT23 PHASE
1
S

D
D
D
D
3

B + PC90 B
3 4 PQ31 220U_6.3VM_R15
GND LGATE SI4810DY_SO8

G
S
S
S
PR110 2
1

0_0402_5% D APW7057KC-TR_SOP8

4
3
2
1
1 2 2 PQ32
34,36,37 SYS ON
G 2N7002_SOT23
S
3

PR111
2

5.11K_0402_1%
PC91 1 2
1

@ 0.1U_0402_16V7K
2

1 2
PR112
PC92
2.4K_0402_1% 0.1U_0402_16V7K
1

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE 2.5V/VGA_CORE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY EAL20 LA-2462 0.1
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
I NC. Date: Friday, September 17, 2004 Sheet 43 of 47
5 4 3 2 1
 5 4 3 2 1

D
PJ14 PU10 +1.8VSP D
+2.5VP 2 1 2 3
2 1 VIN VO

2
JUMP_43X118 PC93 1 4 PC94
EN ADJ 10U_1206_6.3V7K
4.7U_0805_6.3V6K 5 7

1
GND GND
6 8
GND GND +2.5VP
G965-18P1U_SO8
1 2
34,37,42,43 SUSP#

1
PR113
84.5K_0402_1% PJ15

1
1
JUMP_43X118
PC95

2
0.1U_0402_16V7K
2

2
PU11
1 6 +3VALWP
VIN VCNTL
2 5

1
GND NC

1
PC96 3 7 PC97
10U_1206_6.3V7K VREF NC 1U_0603_6.3V6M

2
PR114 4 8
1.37K_0402_1% VOUT NC
9

2
TP
APL5331KAC-TR_SO8
PR115

1
C C
+1.05VP

1
0_0402_5% D
2N7002_SOT23 PC98
1 2 2 PQ33 0.1U_0402_16V7K

1
37 VR_ON# G PR116
S 1K_0402_1% PC99

3
1
10U_1206_6.3V7K

2
PC100
+2.5V @ 0.1U_0402_16V7K

2
1

PJ16
1

JUMP_43X118
2
2

PU12
1 6 +3VALWP
VIN VCNTL
2 5
1

1
GND NC
1

PC101 3 7 PC102
10U_1206_6.3V7K VREF NC 1U_0603_6.3V6M
2

PR117 4 8
1K_0402_1% VOUT NC
9
2

TP
APL5331KAC-TR_SO8
B PR118 B

+1.25VSP
1

0_0402_5% D PQ34
1

S USP 1 2 2 2N7002_SOT23
1

37 S USP G PR119 PC103

S 1K_0402_1% 0.1U_0402_16V7K PC104
3

2
1

10U_1206_6.3V7K
2

PC105
@ 0.1U_0402_16V7K
2

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY Compal Electronics, Inc.
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Title
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE 1.8V/1.25V/1.05V
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR Size Document Number R ev
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY EAL20 LA-2462 0.1
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
I NC. Date: Friday, September 17, 2004 Sheet 44 of 47
5 4 3 2 1
 +5VS
PD22 CPU_B+ B+
PL12
2 1
1 2
2

4.7U_1206_25V6K

4.7U_1206_25V6K
PC109 EP10QY03 1 FBM-L18-453215-900LMA90T_1812
PR120

1
10_0402_5% 2.2U_0603_6.3V6K + PC106
1 220U_25V_M

PC107

PC108
2

2
2

0.1U_0402_25V4K
V CC

1
PC111
2

5
6
7
8
PC110

12

36

2
PU13 PQ35
1U_0603_6.3V6M AO4408_SO8

VCC

VDD
1
42 PR121
V+

0.22U_0603_16V7K
32 2 1
BSTM

1
1 PR151 2 22 34 2.2_0603_5% 4
23,36 PM_POK SYSOK DHM

PC112
0_0402_5% 33
LXM
23 35

2
7,12,23 VGATE IMVPOK DLM N5
24

3
2
1
CLKEN# PL13
45
R E FV CC CMP 0.56UH_ETQP4LR56WFC_21A_20% PR122 +CPU_CORE
25 46
5 C PU_VID5 D5 CMN CPUPHASE1
26 1 2 1 2
1

PR146 5 C PU_VID4 D4
27
2

2
PR148 @ PR147 5 C PU_VID3
28
D3 0.001_2512_5%
D2

5
6
7
8
0_0402_5% 5 C PU_VID2
29
@ 5 C PU_VID1 D1
0_0402_5%

30 48
5 C PU_VID0 D0 CSP
0_0402_5%
47 PQ36
2

1
CSN AO4410_SO8 CPU VCC SENSE
8
1

S2

909_0402_1%
EC31QS04
V CC 7
S1

1
PD23
6 N6 4
S0

499_0402_1%

499_0402_1%
20

1
OAIN+
5

2
B2

1000P_0402_50V7K
PC113
REF 4

2
V CC B1 @
3

3
2
1

2
V CC B0 PC114

PR123
19 1 2 PR126

1
PR149 10_0402_5%2 OAIN- 3.01K_0402_1%
5 PSI# 21
PSI#

PR124

PR125
470P_0402_50V8J 0.47U_0603_16V7K

1
1 2 44 PR129 909_0402_1%
12,23 STP_CPU# DPSLP#
17 1 2 1 2
PR15020_0402_5% CCI PC116 @
23 PM_DPRSLPVR 1 43
SUS

34,37 V R_ON 1 2PR137 0_0402_5% 9 1 PR133 2

0_0402_5% SHDN#
PR127 1M_0402_1%
18 FB 1 2 PR131
FB 3.01K_0402_1%
1 2 14 +5VS
CCV
PC115 270P_0402_50V7K
1 2 R E F 10 1 2 1 2
REF
1 2
PC117 0.22U_0603_16V7K 39 PC118 PR134
DHS 2200P_0402_50V7K 0_0402_5%
1 2 11 40
ILIM LXS PD24 CPU_B+
38
PR132 PR130 200K_0402_1% DLS EP10QY03
1 2 41
57.6K_0402_1% BSTS
2
TON

5
6
7
8

4.7U_1206_25V6K

4.7U_1206_25V6K
37

2
PGND

2.2_0603_5%
PR128

1
PR136
2 1 1 13 PQ39
TIME GND AO4408_SO8
NEG
POS

PC121

PC122
30.1K_0402_1% 31

2
DD0# N7 4

1
15

16

MAX1987ETM_TQFN48

0.22U_0603_16V7K

3
2
1
1
PL14

PC123
1

0.56UH_ETQP4LR56WFC_21A_20%

2
PR144 CPUPHASE2 1 2
1.24K_0402_1%

909_0402_1%
5
6
7
8

1
2

EC31QS04
PQ40

PD25
AO4410_SO8
1

2
PR145 N8 4

2
100K_0402_1%

PR141
@ 1 2
2

PC124

3
2
1
0.47U_0603_16V7K

909_0402_1%
1 2

PR142

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY

OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE Compal Electronics, Inc.
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE Title
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS CPU_CORE
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY Size Document Number R ev
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, EAL20 LA-2462 0.1
I NC.
Date: Friday, September 17, 2004 Sheet 45 of 47
PWR PIR LIST

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND EAL20 PIR LIST
PROPRIETARY NOTE TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE B 0.1
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. EAL20 LA-2462
Date: Friday, September 17, 2004 Sheet 46 of 47
 A B C D E

EAL20 LA-2462 SCHEMATIC CHANGE LIST

REVISION 0.1

NO DATE PAGE MODIFICATION LIST PURPOSE

-----------------------------------------------------------------------------------------------------
1 P04 Add C702 to C709.
2 P32 Q21.2 CD_PLAY to SYSON.
3 P28 Layout: reverse D12.

4 4

3 3

2 2

1 1

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PIR LIST
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
EAL20 LA-2462
D ate: Friday, September 17, 2004 Sheet 47 of 47
A B C D E
www.s-manuals.com