DATA SHEET

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Power Factor Controller for 8

Compact and Robust, 1

SO−8
Continuous Conduction D SUFFIX
CASE 751
Mode Pre-Converters
NCP1654 MARKING DIAGRAM

The NCP1654 is a controller for Continuous Conduction Mode 8

(CCM) Power Factor Correction step−up pre−converters. It controls 54Bxx
the power switch conduction time (PWM) in a fixed frequency mode ALYW
and in dependence on the instantaneous coil current. G
Housed in a SO8 package, the circuit minimizes the number of 1
external components and drastically simplifies the PFC
xx = 65, 133 or 200
implementation. It also integrates high safety protection features that A = Assembly Location
make the NCP1654 a driver for robust and compact PFC stages like an L = Wafer Lot
effective input power runaway clamping circuitry. Y = Year
W = Work Week
Features G = Pb−Free Package
• IEC61000−3−2 Compliant
• Average Current Continuous Conduction Mode
• Fast Transient Response PIN CONNECTIONS
• Very Few External Components
• Very Low Startup Currents (< 75 mA) Ground 1 8 Driver

• Very Low Shutdown Currents (< 400 mA) VM 2 7 VCC

• Low Operating Consumption CS 3 6 Feedback
• ±1.5 A Totem Pole Gate Drive
Brown−Out 4 5 Vcontrol
• Accurate Fully Integrated 65/133/200 kHz Oscillator
• Latching PWM for cycle−by−cycle Duty−Cycle Control (Top View)

• Internally Trimmed Internal Reference

• Undervoltage Lockout with Hysteresis
ORDERING INFORMATION
• Soft−Start for Smoothly Startup Operation
• Shutdown Function Device Package Shipping†

• Pin to Pin Compatible with Industry Standard NCP1654BD65R2G SO−8 2500 /

(Pb−Free) Tape & Reel
• This is a Pb−Free Device
NCP1654BD133R2G SO−8 2500 /
Safety Features (Pb−Free) Tape & Reel
• Inrush Currents Detection
NCP1654BD200R2G SO−8 2500 /
• Overvoltage Protection (Pb−Free) Tape & Reel
• Undervoltage Detection for Open Loop Detection or Shutdown
†For information on tape and reel specifications,
• Brown−Out Detection including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
• Soft−Start Brochure, BRD8011/D.
• Accurate Overcurrent Limitation
• Overpower Limitation

Typical Applications
• Flat TVs, PC Desktops
• AC Adapters
• White Goods, other Off−line SMPS

© Semiconductor Components Industries, LLC, 2016 1 Publication Order Number:

August, 2021 − Rev. 7 NCP1654/D
 NCP1654

MAXIMUM RATINGS TABLE

Symbol Pin Rating Value Unit
DRV 8 Output Drive Capability − Source −1.5 A
Output Drive Capability − Sink +1.5
VCC 7 Power Supply Voltage, VCC pin, continuous voltage −0.3, +20 V
7 Transient Power Supply Voltage, duration < 10 ms, IVCC < 10 mA +25 V
Vin 2, 3, 4, 5, 6 Input Voltage −0.3, +10 V
Power Dissipation and Thermal Characteristics
D suffix, Plastic Package, Case 751
PD(SO) Maximum Power Dissipation @ TA = 70°C 450 mW
RqJA(SO) Thermal Resistance Junction−to−Air 178 °C/W
TJ Operating Junction Temperature Range −40 to +125 °C
TJmax Maximum Junction Temperature 150 °C
TSmax Storage Temperature Range −65 to +150 °C
TLmax Lead Temperature (Soldering, 10 s) 300 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) 2000 V per JEDEC standard JESD22, Method A114E
Machine Model (MM) 200 V (except pin#7 which complies 150 V) per JEDEC standard JESD22, Method A115A.
2. This device contains Latch−up Protection and exceeds ±100 mA per JEDEC Standard JESD78.

TYPICAL ELECTRICAL CHARACTERISTICS TABLE (VCC = 15 V, TJ from −40°C to +125°C, unless otherwise specified) (Note 3)
Symbol Rating Min Typ Max Unit
GATE DRIVE SECTION
ROH Source Resistance @ Isource = 100 mA − 9.0 20 W
ROL Sink Resistance @ Isink = −100 mA − 6.6 18 W
Tr Gate Drive Voltage Rise Time from 1.5 V to 13.5 V (CL = 2.2 nF) − 60 − ns
Tf Gate Drive Voltage Fall Time from 13.5 V to 1.5 V (CL = 2.2 nF) − 40 − ns
REGULATION BLOCK
VREF Voltage Reference 2.425 2.5 2.575 V
IEA Error Amplifier Current Capability − ±28 − mA
GEA Error Amplifier Gain 100 200 300 mS
IBpin6 Pin 6 Bias Current @ VFB = VREF −500 − 500 nA
Vcontrol Pin5 Voltage V
Vcontrol(max) Maximum Control Voltage @ VFB = 2 V − 3.6 −
Vcontrol(min) Minimum Control Voltage @ VFB = 3 V − 0.6 −
DVcontrol DVcontrol = Vcontrol(max) − Vcontrol(min) 2.7 3.0 3.3
VOUTL / VREF Ratio (VOUT Low Detect Thresold / VREF) 94 95 96 %
HOUTL / VREF Ratio (VOUT Low Detect Hysteresis / VREF) − 0.5 − %
IBOOST Pin 5 Source Current when (VOUT Low Detect) is activated 190 228 260 mA
CURRENT SENSE BLOCK
VS Current Sense Pin Offset Voltage, (ICS = 100 mA) − 10 − mV
IS(OCP) Overcurrent Protection Threshold 185 200 215 mA
POWER LIMITATION BLOCK
ICS x VBO Overpower Limitation Threshold − 200 − mVA
ICS(OPL1) Overpower Current Threshold (VBO = 0.9 V, VM = 3 V) 186 222 308 mA
ICS(OPL2) Overpower Current Threshold (VBO = 2.67 V, VM = 3 V) 62 75 110

PWM BLOCK
Dcycle Duty Cycle Range − 0−97 − %

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 NCP1654

TYPICAL ELECTRICAL CHARACTERISTICS TABLE (VCC = 15 V, TJ from −40°C to +125°C, unless otherwise specified) (Note 3)
Symbol Rating Min Typ Max Unit
OSCILLATOR / RAMP GENERATOR BLOCK
fsw Switching Frequency kHz
65 kHz 58 65 72
133 kHz 120 133 146
200 kHz 180 200 220
BROWN−OUT DETECTION BLOCK
VBOH Brown−Out Voltage Threshold (rising) 1.22 1.30 1.38 V
VBOL Brown−Out Voltage Threshold (falling) 0.65 0.7 0.75 V
IIB Pin 4 Input Bias Current @ VBO = 1 V −500 − 500 nA
CURRENT MODULATION BLOCK
IM1 Multiplier Output Current (Vcontrol = Vcontrol(max), VBO = 0.9 V, ICS = 25 mA) − 1.9 − mA
IM2 Multiplier Output Current (Vcontrol = Vcontrol(max), VBO = 0.9 V, ICS = 75 mA)
(@ 0  125°C) 1.5 4.7 8.8
(@ −40  125°C) 1.5 4.7 9.8
IM3 Multiplier Output Current (Vcontrol = Vcontrol(min) + 0.2 V, VBO = 0.9 V, ICS = 25 mA − 28.1 −
IM4 Multiplier Output Current (Vcontrol = Vcontrol(min) + 0.2 V, VBO = 0.9 V, ICS = 75 mA − 84.4 −

OVERVOLTAGE PROTECTION
VOVP / VREF Ratio (Overvoltage Threshold / VREF) 103 105 107 %
TOVP Propagation Delay (VFB – 107% VREF) to Drive Low − 500 − ns
UNDERVOLTAGE PROTECTION / SHUTDOWN
VUVP(on)/VREF UVP Activate Threshold Ratio (TJ = 0°C to +105°C) 4 8 12 %
VUVP(off)/VREF UVP Deactivate Threshold Ratio (TJ = 0°C to +105°C) 6 12 18 %
VUVP(H) UVP Lockout Hysteresis − 4 − %
TUVP Propagation Delay (VFB < 8% VREF) to Drive Low − 500 − ns
THERMAL SHUTDOWN
TSD Thermal Shutdown Threshold 150 − − °C
HSD Thermal Shutdown Hysteresis − 30 − °C
VCC UNDERVOLTAGE LOCKOUT SECTION
VCC(on) Start−Up Threshold (Undervoltage Lockout Threshold, VCC rising) 9.6 10.5 11.4 V
VCC(off) Disable Voltage after Turn−On (Undervoltage Lockout Threshold, VCC falling) 8.25 9.0 9.75 V
VCC(H) Undervoltage Lockout Hysteresis 1.0 1.5 − V
DEVICE CONSUMPTION
Power Supply Current:
ISTUP Start−Up (@ VCC = 9.4 V) − − 75 mA
ICC1 Operating (@ VCC = 15 V, no load, no switching) − 3.7 5.0 mA
ICC2 Operating (@ VCC = 15 V, no load, switching) − 4.7 6.0 mA
ISTDN Shutdown Mode (@ VCC = 15 V and VFB = 0 V) − 300 400 mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. The above specification gives the targeted values of the parameters. The final specification will be available once the complete circuit
characterization has been performed.
I cs V BO
NOTE: IM +
4 ǒVcontrol * Vcontrol(min)Ǔ

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 NCP1654

DETAILED PIN DESCRIPTIONS

Pin Sym- Name Function
bol
1 GND Ground −
2 Vin Multiplier This pin provides a voltage VM for the PFC duty cycle modulation. The input impedance of
Voltage the PFC circuits is proportional to the resistor RM externally connected to this pin. The device
operates in average current mode if an external capacitor CM is connected to the pin.
Otherwise, it operates in peak current mode.
3 CS Current Sense This pin sources a current ICS which is proportional to the inductor current IL. The sense
Input current ICS is for overcurrent protection (OCP), overpower limitation (OPL) and PFC duty
cycle modulation. When ICS goes above 200 mA, OCP is activated and the Drive Output is
disabled.
4 VBO Brown−Out / In Connect a resistor network among the rectified input voltage, BO pin, and ground. And
connect a capacitor between BO pin and ground. BO pin detects a voltage signal
proportional to the average input voltage.
When VBO goes below VBOL, the circuit that detects too low input voltage conditions
(brown−out), turns off the output driver and keeps it in low state until VBO exceeds VBOH.
This signal which is proportional to the RMS input voltage Vac is also for overpower limitation
(OPL) and PFC duty cycle modulation.
5 Vcontrol Control Voltage The voltage of this pin Vcontrol directly controls the input impedance. This pin is connected to
/ Soft−Start external type−2 compensation components to limit the Vcontrol bandwidth typically below 20
Hz to achieve near unity power factor.
The device provides no output when Vcontrol < Vcontrol(min). When it starts operation, the
power increases slowly (soft−start).
6 VFB Feed−Back / This pin receives a feedback signal VFB that is proportional to the PFC circuits output
Shutdown voltage. This information is used for both the output regulation, the overvoltage protection
(OVP), and output undervoltage protection (UVP) to protect the system from damage at
feedback abnormal situation.
When VFB goes above 105% VREF, OVP is activated and the Drive Output is disabled.
When VFB goes below 8% VREF, the device enters a low−consumption shutdown mode.

7 VCC Supply Voltage This pin is the positive supply of the IC. The circuit typically starts to operate when VCC
exceeds 10.5 V and turns off when VCC goes below 9 V. After start−up, the operating range
is 9 V up to 20 V.
8 DRV Drive Output The high current capability of the totem pole gate drive (±1.5 A) makes it suitable to
effectively drive high gate charge power MOSFET.

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 NCP1654

Iin Vin
+ L IL
IN + Output
AC EMI
Cfilter Cbulk Voltage
Input Filter
(VOUT)
−
RSENSE IL

OVP
+
-
105% Vref
- UVP
RboU + B-
OPL Vdd
8% Vref with 4% Vref O
Vdd Hysteresis
UVL- Undervoltage
RfbU Soft 200 mA O Lock−Out
Start
S

FB 6 Reference
Q
R Block
Vref
RfbL
- Off
Bias Block
95% Vref + Vout Low Detect UVP B-
- OTA O Iref Vdd
Vref +
±28 mA Vcc
Vcontrol
5 7
RZ +
Output
CP Vcontrol(min) Buffer 8
DRV
CZ 1
GND
Thermal
Shutdown

BO
Q
4 Faul- PW-
RboL t R
- BO M
CBO + Latc-
VboH / VboL R S
h
OL OVP
VboH = 1.3 V, VboL = 0.7 V
Vref -
+
Vd- Vramp
Vd- d
Vd-
d Current Mirror d + -
Ics Ics
Vbo Iref Vref/10%
Vref
Ics Divi- + Vm
RCS sion RM
C- C 2
S Ics*Vbo > 200 mVA S1
1 65/133/200 kHz CM
3
Oscillator
OPL
O-
Ics > 200 mA L Im = (Ics*Vbo) / (4*(Vcontrol − Vcontrol(min))
OCP

Figure 1. Functional Block Diagram

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 NCP1654

TYPICAL CHARACTERISTICS

10 2.60
ROH & ROL, GATE DRIVE RESIS-

8
2.55
ROH
TANCE (W)

VREF (V)
2.50
4

ROL
2.45
2

0 2.40
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 2. Gate Drive Resistance vs. Figure 3. Reference Voltage vs. Temperature
Temperature

32 −20

30 −22

28 −24
IEA_source (A)

IEA_sink (A)

26 −26

24 −28

22 −30

20 −32
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 4. Source Current Capability of the Figure 5. Sink Current Capability of the Error
Error Amplifier vs. Temperature Amplifier vs. Temperature

300 150

100
250
50
IBpin6 (nA)
GEA (mS)

200 0

−50
150
−100

100 −150
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 6. Error Amplifier Gain vs. Temperature Figure 7. Feedback Pin Current vs.
Temperature (@Vfb = VREF)

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 NCP1654

TYPICAL CHARACTERISTICS

4.0 3.3

3.9 3.2

3.8
VCONTROL(max) (V)

3.1

DVCONTROL (V)
3.7
3.0
3.6
2.9
3.5

3.4 2.8

3.3 2.7
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 8. Vcontrol Maximum Voltage vs. Figure 9. Vcontrol Maximum Swing (DVCONTROL)
Temperature vs. Temperature

95.1 260

95.0 250
94.9
240
VoutL / VREF (%)

94.8
IBoost (mA)

230
94.7
220
94.6
210
94.5

94.4 200

94.3 190
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 10. Ratio (VOUT Low Detect Threshold / Figure 11. Pin 5 Source Current when (VOUT
VREF) vs. Temperature Low Detect) is Activated vs. Temperature

215 306

210 286

205 266
ICS(OPL1) (mA)
IS(OCP) (mA)

200 246

195 226

190 206

185 186
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 12. Over−Current Protection Threshold Figure 13. Over−Power Current Threshold
vs. Temperature (@VBO = 0.9 V & Vm = 3 V) vs. Temperature

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 NCP1654

TYPICAL CHARACTERISTICS

110 100

MAXIMUM DUTY CYCLE (%)

100 99
ICS(OPL2) (mA)

90 98

80 97

70 96

60 95
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 14. Over−Power Current Threshold Figure 15. Maximum Duty Cycle vs.
(@VBO = 2.67 V & Vm = 3 V) vs. Temperature Temperature

72 140

70 138

68 136
fSW (kHz)

fSW (kHz)

66 134

64 132

62 130

60 128

58 126
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 16. Switching Frequency vs. Figure 17. Switching Frequency vs.
Temperature (65 kHz Version) Temperature (133 kHz Version)
210

205

200
fSW (kHz)

195

190

185

180
−50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C)
Figure 18. Switching Frequency vs.
Temperature (200 kHz Version)

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 NCP1654

TYPICAL CHARACTERISTICS

1.40 0.75

1.35
VBOH (V)

VBOL (L)
1.30 0.70

1.25

1.20 0.65
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 19. Brown−Out Voltage Threshold Figure 20. Brown−Out Voltage Threshold
(Rising) vs. Temperature (Falling) vs. Temperature
7.5 2.66

6.5
2.64

5.5
VOVP (V)
Im2 (mA)

2.62
4.5

2.60
3.5

2.5 2.58
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 21. Multiplier Output Current (Vcontrol = Figure 22. Over Voltage Threshold vs.
VCONTROL(max), Vbo = 0.9 V, ICS = 75 mA) vs. Temperature
Temperature
107 16
VUVP(on) / VREF and VUVP(off) / VREF (%)

14

106 12
VOVP / VREF (%)

10

105 8

104 4

2
103 0
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 23. Ratio (Over Voltage Threshold / Figure 24. UVP Activate and Deactivate
VREF) vs. Temperature Threshold Ratio vs. Temperature

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 NCP1654

TYPICAL CHARACTERISTICS

11.4 9.7
11.2
9.5
11.0
9.3
10.8
VCC(on) (V)

VCC(off) (V)
10.6 9.1

10.4 8.9
10.2
8.7
10.0
8.5
9.8
9.6 8.3
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 25. VCC Start−Up Threshold (VCC Figure 26. VCC Disable Voltage after Turn−On
Rising) vs. Temperature (VCC Falling) vs. Temperature
2.0 50

1.8 40

1.6 30
ISTUP (mA)
VCC(H) (V)

1.4 20

1.2 10

1.0 0
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 27. VCC UVLO Hysteresis vs. Figure 28. Supply Current in Startup Mode vs.
Temperature Temperature

400 4
OPERATING CURRENT (mA)

350 3 ICC2, No Load, Switching

ISTDN (mA)

ICC1, No Load, No Switching

300 2

250 1

200 0
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 29. Supply Current in Shutdown Mode Figure 30. Operating Supply Current vs.
vs. Temperature Temperature

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 NCP1654

Detailed Operating Description voltage goes below than about 8% of the regulation
level. In this case, the circuit turns off and its
Introduction consumption drops to a very low value. This feature
The NCP1654 is a PFC driver designed to operate in fixed protects the PFC stage from starting operation in case
frequency, continuous conduction mode. The fixed of low AC line conditions or in case of a failure in the
frequency operation eases the compliance with EMI feed−back network (i.e. bad connection).
standard and the limitation of the possible radiated noise that − Fast Transient Response: given the low bandwidth of
may pollute surrounding systems. In addition, continuous the regulation block, the output voltage of PFC stages
conduction operation reduces the application di/dt and their may exhibit excessive over or under−shoots because
resulting interference. More generally, the NCP1654 is an of abrupt load or input voltage variations (e.g. at start
ideal candidate in systems where cost−effectiveness, up). If the output voltage is too far from the
reliability and high power factor are the key parameters. It regulation level:
incorporates all the necessary features to build a compact Overvoltage Protection: NCP1654 turns off the
and rugged PFC stage: power switch as soon as Vout exceeds the OVP
• Compactness and Flexibility: housed in a SO8 threshold (105% of the regulation level). Hence
package, the NCP1654 requires a minimum of external a cost & size effective bulk capacitor of lower
components. In particular, the circuit scheme simplifies voltage rating is suitable for this application,
the PFC stage design and eliminates the need for any Dynamic Response Enhancer: NCP1654
input voltage sensing. In addition, the circuit offers drastically speeds up the regulation loop by its
some functions like the Brown−Out or the true power internal 200ĂmA enhanced current source when the
limiting that enable the optimizations of the PFC output voltage is below 95% of its regulation level.
design, − Brown−Out Detection: the circuit detects low AC line
• Low Consumption and Shutdown Capability: the conditions and disables the PFC stage in this case.
NCP1654 is optimized to exhibit consumption as small This protection mainly protects the power switch
as possible in all operation modes. The consumed from the excessive stress that could damage it in such
current is particularly reduced during the start−up phase conditions,
and in shutdown mode so that the PFC stage power − Over−Power Limitation: the NCP1654 computes the
losses are extremely minimized when the circuit is maximum permissible current in dependence of the
disabled. This feature helps meet the more stringent average input voltage measured by the brown−out
stand−by low power specifications. Just ground the block. It is the second OCP with a threshold that is
Feed−back pin to force the NCP1654 in shutdown line dependent. When the circuit detects an excessive
mode, power transfer, it resets the driver output
• Safety Protections: the NCP1654 permanently monitors immediately,
the output voltage, the coil current and the die − Thermal Shutdown: an internal thermal circuitry
temperature to protect the system from possible disables the circuit gate drive and then keeps the
over−stresses. Integrated protections (Overvoltage power switch off when the junction temperature
protection, coil current limitation, thermal shutdown...) exceeds 150°C typically. The circuit resumes
operation once the temperature drops below about
make the PFC stage extremely robust and reliable:
120°C (30°C hysteresis),
− Maximum Current Limit: the circuit permanently
− Soft Start: Vcontrol is pulled low brown−out detection
senses the coil current and immediately turns off the
activates, or Undervoltage protection activates, and
power switch if it is higher than the set current limit.
no drive is provided.
The NCP1654 also prevents any turn on of the power
At start up, the “200 mA enhanced current source” is
switch as long as the coil current is not below its
disabled. So there is only 28 mA to charge the
maximum permissible level. This feature protects the
compensation components, and makes Vcontrol raise
MOSFET from possible excessive stress that could
gradually. This is to obtain a slow increasing duty
result from the switching of a current higher than the
cycle and hence reduce the voltage and current stress
one the power switch is dimensioned for. In
on the MOSFET. Hence it provides a soft−start
particular, this scheme effectively protects the PFC
stage during the start−up phase when large in−rush feature.
currents charge the output capacitor. • Output Stage Totem Pole: the NCP1654 incorporates
− Undervoltage Protection for Open Loop Protection or a ±1.5A gate driver to efficiently drive TO220 or
Shut−down: the circuit detects when the feed−back TO247 power MOSFETs.

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 NCP1654

PRINCIPLE OF NCP1654 SCHEME The input filter capacitor Cfilter and the front−ended EMI
filter absorbs the high−frequency component of inductor
CCM PFC Boost
current IL. It makes the input current Iin a low−frequency
A CCM PFC boost converter is shown in Figure 31. The signal only of the inductor current.
input voltage is a rectified 50 ro 60 Hz sinusoidal signal. The
MOSFET is switching at a high frequency (typically I in + I L*50 (eq. 2)
65/133/200 kHz in NCP1654) so that the inductor current IL where
basically consists of high and low−frequency components.
Iin is the input AC current.
Filter capacitor Cfilter is an essential and very small value
capacitor in order to eliminate the high−frequency IL is the inductor current.
component of the inductor IL. This filter capacitor cannot be IL−50 supposes a 50 Hz operation. The suffix 50 means it
too bulky because it can pollute the power factor by is with a 50 Hz bandwidth of the original IL.
distorting the rectified sinusoidal input voltage. From (Equation 1) and (Equation 2), the input impedance
Zin is formulated.
Iin L IL Vout V in T * t 1 V out
Z in + + (eq. 3)
Vin
Output I in T I L*50
+
Cfilter Voltage
where Zin is input impedance.
Cbulk
Power factor is corrected when the input impedance Zin in
RSENSE (Equation 3) is constant or varies slowly in the 50 or 60 Hz
bandwidth.
Figure 31. CCM PFC Boost Converter
VM Vref
PFC Methodology Ich PFC Modula-
The NCP1654 uses a proprietary PFC methodology - tion
+ + R Q
particularly designed for CCM operation. The PFC Vramp
0 1 S
methodology is described in this section. Cramp
IL
Iin Clock
Vref

Vramp
t1 t2 Time
VM
T VM without
Filtering
Clock
Figure 32. Inductor Current in CCM
Latch Set
As shown in Figure 32, the inductor current IL in a
Latch Reset
switching period T includes a charging phase for duration t1
and a discharging phase for duration t2. The voltage Output
conversion ratio is obtained in (Equation 1).
V out t ) t2
+ 1 + T Inductor
V in t2 T * t1 Current

T * t1
V in + V out (eq. 1)
T Figure 33. PFC Duty Modulation and Timing Diagram
where
The PFC modulation and timing diagram is shown in
Vout is the output voltage of PFC stage, Figure 33. The MOSFET on time t1 is generated by the
Vin is the rectified input voltage, intersection of reference voltage VREF and ramp voltage
T is the switching period, Vramp. A relationship in (Equation 4) is obtained.
t1 is the MOSFET on time, and I cht 1
V ramp + V m ) + V REF (eq. 4)
C ramp
t2 is the MOSFET off time.
where

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 NCP1654

Vramp is the internal ramp voltage, the positive input of the R MI csV bo Vm Im
PFC modulation comparator, Vm +
4(V control * V CONTROL(min))
2
Vm is the multiplier voltage appearing on Vm pin, RM CM
Ich is the internal charging current, PFC Duty
Cramp is the internal ramp capacitor, and Modulation

VREF is the internal reference voltage, the negative input of Figure 35. External Connection on the Multiplier
the PFC modulation comparator. Voltage Pin
Ich, Cramp, and VREF also act as the ramp signal of
switching frequency. Hence the charging current Ich is The multiplier voltage Vm is generated according to
specially designed as in (Equation 5). The multiplier voltage (Equation 8).
Vm is therefore expressed in terms of t1 in (Equation 6). R MI csV bo
Vm + (eq. 8)
C rampV REF 4(V control * V CONTROL(min))
I ch + (eq. 5)
T
Where,
C rampV REF
t1 T * t1 RM is the external multiplier resistor connected to Vm pin,
V m + V REF * + V REF (eq. 6)
C ramp T T which is constant.
From (Equation 3) and (Equation 6), the input impedance Vbo is the input voltage signal appearing on the BO pin,
Zin is re−formulated in (Equation 7). which is proportional to the rms input voltage,
V m V out Ics is the sense current proportional to the inductor current
Z in + (eq. 7) IL as described in (Equation 11).
V REF I L*50
Because VREF and Vout are roughly constant versus time, Vcontrol is the control voltage signal, the output voltage of
the multiplier voltage Vm is designed to be proportional to Operational Trans−conductance Amplifier (OTA), as
the IL−50 in order to have a constant Zin for PFC purpose. It described in (Equation 12).
is illustrated in Figure 34. RM directly limits the maximum input power capability
and hence its value affects the NCP1654 to operate in either
“follower boost mode” or “constant output voltage mode”.
Vin
Vin
+
Iin Time

IL RboU
Time Vbo

VM 4
RboL - BO
Time
CBO +

Figure 34. Multiplier Voltage Timing Diagram VboH / VboL

VboH = 1.3 V, VboL = 0.7 V

It can be seen in the timing diagram in Figure 33 that Vm Figure 36. External Connection on the Brown Out Pin
originally consists of a switching frequency ripple coming
from the inductor current IL. The duty ratio can be Refer to Figure 36,
inaccurately generated due to this ripple. This modulation is 2 Ǹ2
the so−called “peak current mode”. Hence, an external V bo + K BO(V in) + K BO @ p V ac (eq. 9)
capacitor CM connected to the multiplier voltage Vm pin is R boL
essential to bypass the high−frequency component of Vm. K BO + (eq. 10)
R boU ) R boL
The modulation becomes the so−called “average current
mode” with a better accuracy for PFC. where
Vbo is the voltage on BO pin.
KBO is the decay ratio of Vin to Vbo.
<Vin> is the average voltage signal of Vin, the voltage
appearing on Cfilter.
Vac is the RMS input voltage.

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13
 NCP1654

RboL is low side resistor of the dividing resistors between Vin Refer to Figure 37, sense current Ics is proportional to the
and BO pin. inductor current IL as described in (Equation 11). IL consists
RboU is upper side resistor of the dividing resistors between of the high−frequency component (that depends on di/dt or
Vin and BO pin. inductor L) and low−frequency component (that is IL−50).
IL R SENSE
I cs + IL (eq. 11)
R CS

where
ICS CS +
NCP1654 RSENSE is the sense resistor to sense IL.
RCS +
VCS RCS is the offset resistor between CS pin and RSENSE.
Gnd
−

RSENSE IL

Figure 37. Current Sensing

Vin Vout
+

RfbU
Vfb
6
RfbL
- ±20 mA
Vcontrol VREF +
OTA +
VCONTROL(min)
5
CP RZ
CZ
To Vm Pin

Figure 38. Vcontrol Low−Pass Filtering

Refer to Figure 38, the Operational Trans−conductance From (Equation 7) − (Equation 11), the input impedance
Amplifier (OTA) senses Vout via the feedback resistor Zin is re−formulated in (Equation 13).
dividers, RfbU and RfbL. The OTA constructs a control Ǹ2 R R (eq. 13)
voltage, Vcontrol, depending on the output power and hence M SENSEV outV acK BOI L
Z in +
2pR CS @ (V control * V CONTROL(min)) @ V REFI L*50
Vout. The operating range of Vcontrol is from VCONTROL(min)
to VCONTROL(max). The signal used for PFC duty When IL is equal to IL−50, (Equation 13) is re−formulated
modulation is after decreasing a offset voltage, in (Equation 14)
VCONTROL(min), i.e. Vcontrol−VCONTROL(min). Ǹ2 R R
This control current Icontrol is a roughly constant current M SENSEV outV acK BO
Z in + (eq. 14)
2pR CS @ (V control * V CONTROL(min)) @ V REF
that comes from the PFC output voltage Vout that is a slowly
varying signal. The bandwidth of Icontrol can be additionally The multiplier capacitor CM is the one to filter the
limited by inserting the external type−2 compensation high−frequency component of the multiplier voltage Vm.
components (that are RZ, CZ, and CP as shown in Figure 38). The high−frequency component is basically coming from
It is recommended to limit fcontrol, that is the bandwidth of the inductor current IL. On the other hand, the filter capacitor
Vcontrol (or Icontrol), below 20 Hz typically to achieve power Cfilter similarly removes the high−frequency component of
factor correction purpose. inductor current IL. If the capacitors CM and Cfilter match
The transformer of Vout to Vcontrol is as described in with each other in terms of filtering capability, IL becomes
(Equation 12) if CZ is >> CP. GEA is the error amplifier gain. IL−50. Input impedance Zin is roughly constant over the
V control R @ G EAR Z 1 ) sR ZC Z bandwidth of 50 or 60 Hz and power factor is corrected.
+ fbL @ (eq. 12)
V out R fbL ) R fbU sR ZC Z(1 ) sR ZC P)

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14
 NCP1654

Input and output power (Pin and Pout) are derived in (Equation 15) when the circuit efficiency η is obtained or assumed. The
variable Vac stands for the rms input voltage.
V ac 2 2pR CS @ (V control * V CONTROL(min)) @ V REF @ V ac
P in + + (eq. 15)
Z in Ǹ2 R R V K
M SENSE out BO

(V control * V CONTROL(min))V ac
T
V out

2pR CS @ (V control * V CONTROL(min)) @ V REF @ V ac

P out + h P in + h (eq. 16)
Ǹ2 R R
M SENSEV outK BO

(V control * V CONTROL(min))V ac
T
V out
Follower Boost VCONTROL(max). Re−formulate (Equation 16) to become
The “Follower Boost” is an operation mode where the (Equation 17) and (Equation 18) by replace Vcontrol by
pre−converter output voltage stabilizes at a level that varies VCONTROL(max). If Vcontrol is constant based on
linearly versus the ac line amplitude. This technique aims at (Equation 15), for a constant load or power demand the
reducing the gap between the output and input voltages to output voltage Vout of the converter is proportional to the
optimize the boost efficiency and minimize the cost of the rms input voltage Vac. It means the output voltage Vout
PFC stage (refer to MC33260 data sheet for more details at becomes lower when the rms input voltage Vac becomes
http://www.onsemi.com). lower. On the other hand, the output voltage Vout becomes
The NCP1654 operates in follower boost mode when lower when the load or power demand becomes higher.
Vcontrol is constant, i.e. Vcontrol raises to its maximum value
2pR CS @ (V CONTROL(max) * V CONTROL(min)) @ V REF @ V ac
P out + h (eq. 17)
Ǹ2 R R
M SENSEV outK BO

2pR CS @ DV CONTROL @ V REF @ V ac

+h
Ǹ2 R R V K
M SENSE out BO

2pR CS @ DV CONTROL @ V REF V ac

V out + h @ (eq. 18)
Ǹ2 R R K P out
M SENSE BO
where the output voltage Vout will always be higher than the input
VCONTROL(max) is the maximum control voltage. voltage Vin even though Vout is reduced in follower boost
operation. As a result, the on time t1 is reduced. Reduction
DVCONTROL is the gap between VCONTROL(max) and
of on time makes the loss of the inductor and power
VCONTROL(min).
MOSFET smaller. Hence, it allows cheaper cost in the
It is illustrated in Figure 39. inductor and power MOSFET or allows the circuit
components to operate at a lower stress condition in most of
Vout (Traditional Boost) the time.

Reference Section
Vout (Follower Boost) The internal reference voltage (VREF) is trimmed to be
Vin ±2% accurate over the temperature range (the typical value
is 2.5 V). VREF is the reference used for the regulation. VREF
Time also serves to build the thresholds of the fast transient
response, Overvoltage (OVP), brown out (BO), and
Pout Undervoltage protections (UVP).
Time
Output Feedback
Figure 39. Follower Boost Characteristics The output voltage Vout of the PFC circuits is sensed at Vfb
pin via the resistor divider (RfbL and RfbU) as shown in
Follower Boost Benefits Figure 38. Vout is regulated as described in (Equation 19).
The follower boost circuit offers and opportunity to
R fbU ) R fbL
reduce the output voltage Vout whenever the rms input V out + V REF (eq. 19)
R fbL
voltage Vac is lower or the power demand Pout is higher.
Because of the step−up characteristics of boost converter,

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 NCP1654

The feedback signal Vfb represents the output voltage Vout Fast Transient Response
and will be used in the output voltage regulation, Given the low bandwidth of the regulation block, the
Overvoltage protection (OVP), fast transient response, and output voltage of PFC stages may exhibit excessive over or
Undervoltage protection (UVP) under−shoots because of abrupt load or input voltage
variations (such as start−up duration). As shown in
Output Voltage Regulation Figure 40, if the output voltage is out of regulation,
NCP1654 uses a high gain Operational Trans− NCP1654 has 2 functions to maintain the output voltage
conductance Amplifier (OTA) as error amplifier. Refer to regulation.
Figure 38, the output of OTA Vcontrol operating range is
from VCONTROL(min) to VCONTROL(max).
Vout
+

Vdd

OVP
- 200 mA
RfbU 105% +
Vfb VREF
-
CFB 6 95% +
RfbL Vout Low Detect
VREF
- ±20 mA
Vcontrol VREF +
OTA

Figure 40. OVP and Fast Transient Response

• Overvoltage Protection: When Vfb is higher than 105% below 95% of its regulation level. Under normal
of VREF (i.e. Vout > 105% of nominal output voltage), condition, the maximum sink and source of output
the Driver output of the device goes low for protection. current capability of OTA is around 28 mA. Thanks to
The circuit automatically resumes operation when Vfb the “Vout low detect” block, when the Vfb is below 95%
becomes lower than 105% of VREF. If the nominal Vout VREF, an extra 200 mA current source will raise Vcontrol
is set at 390 V, then the maximum output voltage is rapidly. Hence prevent the PFC output from dropping
105% of 390 V = 410 V. Hence a cost & size effective too low and improve the transient response
bulk capacitor of lower voltage rating is suitable for performance. The relationship between current flowing
this application, in/out Vcontrol pin and Vfb is as shown in Figure 41.
• Dynamic response enhancer: NCP1654 drastically It is recommended to add a typical 100 pF capacitor CFB
speeds up the regulation loop by its internal 200 mA decoupling capacitor next to feedback pin to prevent from
enhanced current source when the output voltage is noise impact.
VCONTROL PIN CURRENT (mA)

50
200 mA raises
0 Vcontrol rapidly
−50 when Vfb is below
95% VREF
−100
No DRV when
−150
Vfb is above
−200 105% VREF
−250
2 2.2 2.4 2.6 2.8 3
Vfb
Figure 41. Vfb vs. Current Flowing in/out from Vcontrol Pin

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 NCP1654

Soft Start
The block diagram and timing diagram of soft start Off BO UVLO UVP
Vdd
function are as shown in Figure 42 and Figure 43. The device
provides no output (or no duty ratio) when the Vcontrol is Bias
lower than VCONTROL(min). Vcontrol is pulled low when:
• Brown−out, or
• Undervoltage Protection Vdd
When the IC recovers from one of the following S Q
conditions; Undervoltage Lockout, Brown−out or 200 mA
R Q
Undervoltage Protection, the 200 mA current source block
keeps off. Hence only the Operating Trans−conductance
Vfb -
Amplifier (OTA) raises the Vcontrol. And Vcontrol rises
6 95% +
slowly. This is to obtain a slow increasing duty cycle and Vout Low Detect
VREF
hence reduce the voltage and current stress on the MOSFET. - ±20 mA
A soft−start operation is obtained. VREF +
Vcontrol OTA

5 BO UVLO

Figure 42. Soft Start Block Diagram

Period I Period II
UVLO, BO, or UVP

Vdd

Vdd Rising

Vfb
95% VREF

Vout Low Detect

Set

Reset

Figure 43. Soft Start Timing Diagram

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 NCP1654

Undervoltage Protection (UVP) for Open Loop Over−Current Protection (OCP)

Protection or Shutdown Over−Current Protection is reached when Ics is larger than
IS(OCP) (200 mA typical). The offset voltage of the CS pin is
typical 10 mV and it is neglected in the calculation. Hence,
the maximum OCP inductor current threshold IL(OCP) is
ISTDN obtained in (Equation 20).
Shutdown Operating
R CSI S(OCP) R CS
I L(OCP) + + @ 200 mA (eq. 20)
ICC2 R SENSE R SENSE
Vfb When over−current protection threshold is reached, the
8% VREF 12% VREF Drive Output of the device goes low. The device
automatically resumes operation when the inductor current
Figure 44. Undervoltage Protection goes below the threshold.

As shown in Figure 44, when Vfb is less than 8% of VREF, Input Voltage Sense
the device is shut down and consumes less than 400 mA. The The device senses the rms input voltage Vac by the sensing
device automatically starts operation when the output scheme in Figure 45. Vbo senses the average rectified input
voltage goes above 12% of VREF. In normal situation of voltage Vin via the resistor divider. An external capacitor
boost converter configuration, the output voltage Vout is CBO is to maintain the Vbo the average value of Vin. Vbo is
always greater than the input voltage Vin and the feedback used for Brown−Out Protection, PFC duty modulation and
signal Vfb is always greater than 8% and 12% of VREF to over−power limitation (OPL).
enable NCP1654 to operate.
Brown−Out Protection
This Undervoltage Protection function has 2 purposes.
The device uses the Vbo signal to protect the PFC stage
• Open Loop Protection − Protect the power stage from from operating as the input voltage is lower than expected.
damage at feedback loop abnormal, such as Vfb is Re−formulate (Equation 9) to get (Equation 21). Refer to
shorted to ground or the feedback resistor RfbU is open. Figure 45, Vin is different before and after the device
• Shutdown mode − Disables the PFC stage and forces a operating.
low consumption mode. This feature helps to meet • Before the device operates, Vin is equal to the peak
stringent stand−by specifications. Power Factor being value of rms input voltage, Vac. Hence Vbo is as
not necessary in stand−by, the PFC stage is generally described in (Equation 21).
inhibited to save the pre−converter losses. To further
R boL R boL Ǹ2 V (eq. 21)
improve the stand−by performance, the PFC controller V bo + (V ) + ac
should consume minimum current in this mode. R boL ) R boU in R boL ) R boU
• After device operates, Vin is the rectified sinusoidal
Current Sense
input voltage. Thanks to CBO, Vbo is the average of
The device senses the inductor current IL by the current
rectified input voltage. Hence Vbo decays to 2/p of the
sense scheme in Figure 37. The device maintains the voltage
peak value of rms input voltage Vac as described in
at CS pin to be zero voltage (i.e., Vcs ≈ 0 V) so that
(Equation 22).
(Equation 11),
R SENSE R boL 2 Ǹ2
I cs + IL , V bo + V ac (eq. 22)
R CS R boL ) R boU p

can be formulated.
This scheme has the advantage of the minimum number
of components for current sensing. The sense current Ics
represents the inductor current IL and will be used in the PFC
duty modulation to generate the multiplier voltage Vm,
Over−Power Limitation (OPL), and Over−Current
Protection. (Equation 11) would insist in the fact that it
provides the flexibility in the RSENSE choice and that it
allows to detect in−rush currents.

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 NCP1654

Before Device Operates After Device Operates

Vin
+
Vac IN +

RboU
Vbo
- BO
4
+
RboL CBO
VboH / VboL
VboH = 1.3 V, VboL = 0.7 V

Figure 45. Brown−Out Protection

Hence a larger hysteresis of the brown out comparator is Overpower Limitation (OPL)
needed, which is 0.7 V typical in this device. When Vbo goes This is a second OCP with a threshold that is line
below than VBOL (0.7 V typical), the device turns off the dependent. Sense current Ics represents the inductor current
Drive output and keeps it off till Vbo exceeds VBOH (1.3 V IL and hence represents the input current approximately.
typical). When the device awakes after an off−state Input voltage signal Vbo represents the rms input voltage.
(Undervoltage lockout or shutdown), the default threshold The product (Ics ⋅ Vbo) represents an approximated input
is VBOH. power (IL ⋅ Vac). It is illustrated in Figure 46.
Vin

RSENSE IL

R SENSE
I CS + I L
RCS CS R CS
ICS OPL
Current Mirror
3
4
>200 mVA?
Vbo

Figure 46. Over−Power Limitation

When the product (Ics ⋅ Vbo) is greater than a permissible Bias the Controller
level 200 mVA, the device turns off the drive output so that It is recommended to add a typical 1 nF to 100 nF
the input power is limited. The OPL is automatically decoupling capacitor next to the Vcc pin for proper
deactivated when the product (Ics ⋅ Vbo) is lower than the operation. When the NCP1654 operates in follower boost
200 mVA level. This 200 mVA level corresponds to the mode, the PFC output voltage is not always regulated at a
approximated input power (IL ⋅ Vac) to be smaller than the particular level under all application range of input voltage
particular expression in (Equation 23). and load power. It is not recommended to make a
I csV bo t 200 mVA low−voltage bias supply voltage by adding an auxiliary
(eq. 23) winding on the PFC boost inductor. Alternatively, it is
ǒ R
I L SENSE @
R CS
Ǔǒ 2 Ǹ2 K BO
p @ V ac Ǔ t 200 mVA
recommended to get the Vcc biasing supply from the
2nd−stage power conversion stage.

R CS @ p
I L @ V ac t @ 50 Ǹ2 mVA
R SENSE @ K BO

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 NCP1654

Vcc Undervoltage LockOut (UVLO)

The device incorporates an Undervoltage Lockout block incorporates some hysteresis (1.5 V) to prevent erratic
to prevent the circuit from operating when Vcc is too low in operation as the Vcc crosses the threshold. When Vcc goes
order to ensure a proper operation. An UVLO comparator below the UVLO comparator lower threshold (9 V
monitors Vcc pin voltage to allow the NCP1654 to operate typically), the circuit turns off. It is illustrated in Figure 47.
when Vcc exceeds 10.5 V typically. The comparator After startup, the operating range is between 9 V and 20 V.

ON
State

OFF
VCC

6 mA
ICC

<75 mA
VCC
VCC(OFF) VCC(ON)

Figure 47. Vcc Undervoltage LockOut (UVLO)

Thermal Shutdown enabled once the temperature drops below typically 120°C
An internal thermal circuitry disables the circuit gate drive (i.e., 30°C hysteresis). The thermal shutdown is provided to
and then keeps the power switch off when the junction prevent possible device failures that could result from an
temperature exceeds 150°C. The output stage is then accidental overheating.

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20
 NCP1654

TB2

1 2
390 V

C4 TB3
180 mF, 450 V
+

D1 MSR860G 1 2

SPP20N60S5
Q1 +15 V C8
+
R1 1.8 M R4 1N4148
C9 22 mF
10 k D2
C10
0.1 mF
R2 1.8 M R5 10
100 pF
R3

23.2 k
2.2 mF

Vcontrol
R12 C12

VCC
DRV
12 k C5

FB
5
8 7 6 5 220 nF

NCP1654
L1 650 mH R6 0.1
IC1
1 2 3 4
GND

CS

BO
VM

2 R8

R7 47 k

3.6 k 1 nF C6

R9 R13 R10 R11

0.1 mF 3.3 M 3.3 M 0 82.5 k
GBU8J
600 V + C7
8A C3

0.47 mF
−
DB1
C2

0.47 mF

L2 2 x 6.8 mH

L3 150 mH
C1

0.47 mF
5 A Fuse
F1
1 2 3
L N
AC Inlet TB1

Figure 48. Application Schematic − 300 W 65 kHz

Power Factor Correction Circuit

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21
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS

SOIC−8 NB
8 CASE 751−07
1 ISSUE AK
SCALE 1:1 DATE 16 FEB 2011

NOTES:
1. DIMENSIONING AND TOLERANCING PER
−X− ANSI Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
8 5 PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
1 IN EXCESS OF THE D DIMENSION AT
4 MAXIMUM MATERIAL CONDITION.
−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS INCHES
G
DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
C N X 45 _ B 3.80 4.00 0.150 0.157
SEATING C 1.35 1.75 0.053 0.069
PLANE D 0.33 0.51 0.013 0.020
−Z− G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
0.10 (0.004) J 0.19 0.25 0.007 0.010
H M J K 0.40 1.27 0.016 0.050
D
M 0_ 8_ 0 _ 8 _
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
0.25 (0.010) M Z Y S X S

GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
8 8 8 8
XXXXX XXXXX XXXXXX XXXXXX
ALYWX ALYWX AYWW AYWW
1.52
G G
0.060
1 1 1 1
IC IC Discrete Discrete
(Pb−Free) (Pb−Free)
7.0 4.0
XXXXX = Specific Device Code XXXXXX = Specific Device Code
0.275 0.155
A = Assembly Location A = Assembly Location
L = Wafer Lot Y = Year
Y = Year WW = Work Week
W = Work Week G = Pb−Free Package
G = Pb−Free Package

0.6 1.270 *This information is generic. Please refer to

0.024 0.050 device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
SCALE 6:1 ǒinches
mm Ǔ or may not be present. Some products may
not follow the Generic Marking.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

STYLES ON PAGE 2

Electronic versions are uncontrolled except when accessed directly from the Document Repository.
DOCUMENT NUMBER: 98ASB42564B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DESCRIPTION: SOIC−8 NB PAGE 1 OF 2

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

 SOIC−8 NB
CASE 751−07
ISSUE AK
DATE 16 FEB 2011
STYLE 1: STYLE 2: STYLE 3: STYLE 4:
PIN 1. EMITTER PIN 1. COLLECTOR, DIE, #1 PIN 1. DRAIN, DIE #1 PIN 1. ANODE
2. COLLECTOR 2. COLLECTOR, #1 2. DRAIN, #1 2. ANODE
3. COLLECTOR 3. COLLECTOR, #2 3. DRAIN, #2 3. ANODE
4. EMITTER 4. COLLECTOR, #2 4. DRAIN, #2 4. ANODE
5. EMITTER 5. BASE, #2 5. GATE, #2 5. ANODE
6. BASE 6. EMITTER, #2 6. SOURCE, #2 6. ANODE
7. BASE 7. BASE, #1 7. GATE, #1 7. ANODE
8. EMITTER 8. EMITTER, #1 8. SOURCE, #1 8. COMMON CATHODE
STYLE 5: STYLE 6: STYLE 7: STYLE 8:
PIN 1. DRAIN PIN 1. SOURCE PIN 1. INPUT PIN 1. COLLECTOR, DIE #1
2. DRAIN 2. DRAIN 2. EXTERNAL BYPASS 2. BASE, #1
3. DRAIN 3. DRAIN 3. THIRD STAGE SOURCE 3. BASE, #2
4. DRAIN 4. SOURCE 4. GROUND 4. COLLECTOR, #2
5. GATE 5. SOURCE 5. DRAIN 5. COLLECTOR, #2
6. GATE 6. GATE 6. GATE 3 6. EMITTER, #2
7. SOURCE 7. GATE 7. SECOND STAGE Vd 7. EMITTER, #1
8. SOURCE 8. SOURCE 8. FIRST STAGE Vd 8. COLLECTOR, #1
STYLE 9: STYLE 10: STYLE 11: STYLE 12:
PIN 1. EMITTER, COMMON PIN 1. GROUND PIN 1. SOURCE 1 PIN 1. SOURCE
2. COLLECTOR, DIE #1 2. BIAS 1 2. GATE 1 2. SOURCE
3. COLLECTOR, DIE #2 3. OUTPUT 3. SOURCE 2 3. SOURCE
4. EMITTER, COMMON 4. GROUND 4. GATE 2 4. GATE
5. EMITTER, COMMON 5. GROUND 5. DRAIN 2 5. DRAIN
6. BASE, DIE #2 6. BIAS 2 6. DRAIN 2 6. DRAIN
7. BASE, DIE #1 7. INPUT 7. DRAIN 1 7. DRAIN
8. EMITTER, COMMON 8. GROUND 8. DRAIN 1 8. DRAIN

STYLE 13: STYLE 14: STYLE 15: STYLE 16:

PIN 1. N.C. PIN 1. N−SOURCE PIN 1. ANODE 1 PIN 1. EMITTER, DIE #1
2. SOURCE 2. N−GATE 2. ANODE 1 2. BASE, DIE #1
3. SOURCE 3. P−SOURCE 3. ANODE 1 3. EMITTER, DIE #2
4. GATE 4. P−GATE 4. ANODE 1 4. BASE, DIE #2
5. DRAIN 5. P−DRAIN 5. CATHODE, COMMON 5. COLLECTOR, DIE #2
6. DRAIN 6. P−DRAIN 6. CATHODE, COMMON 6. COLLECTOR, DIE #2
7. DRAIN 7. N−DRAIN 7. CATHODE, COMMON 7. COLLECTOR, DIE #1
8. DRAIN 8. N−DRAIN 8. CATHODE, COMMON 8. COLLECTOR, DIE #1

STYLE 17: STYLE 18: STYLE 19: STYLE 20:

PIN 1. VCC PIN 1. ANODE PIN 1. SOURCE 1 PIN 1. SOURCE (N)
2. V2OUT 2. ANODE 2. GATE 1 2. GATE (N)
3. V1OUT 3. SOURCE 3. SOURCE 2 3. SOURCE (P)
4. TXE 4. GATE 4. GATE 2 4. GATE (P)
5. RXE 5. DRAIN 5. DRAIN 2 5. DRAIN
6. VEE 6. DRAIN 6. MIRROR 2 6. DRAIN
7. GND 7. CATHODE 7. DRAIN 1 7. DRAIN
8. ACC 8. CATHODE 8. MIRROR 1 8. DRAIN
STYLE 21: STYLE 22: STYLE 23: STYLE 24:
PIN 1. CATHODE 1 PIN 1. I/O LINE 1 PIN 1. LINE 1 IN PIN 1. BASE
2. CATHODE 2 2. COMMON CATHODE/VCC 2. COMMON ANODE/GND 2. EMITTER
3. CATHODE 3 3. COMMON CATHODE/VCC 3. COMMON ANODE/GND 3. COLLECTOR/ANODE
4. CATHODE 4 4. I/O LINE 3 4. LINE 2 IN 4. COLLECTOR/ANODE
5. CATHODE 5 5. COMMON ANODE/GND 5. LINE 2 OUT 5. CATHODE
6. COMMON ANODE 6. I/O LINE 4 6. COMMON ANODE/GND 6. CATHODE
7. COMMON ANODE 7. I/O LINE 5 7. COMMON ANODE/GND 7. COLLECTOR/ANODE
8. CATHODE 6 8. COMMON ANODE/GND 8. LINE 1 OUT 8. COLLECTOR/ANODE

STYLE 25: STYLE 26: STYLE 27: STYLE 28:

PIN 1. VIN PIN 1. GND PIN 1. ILIMIT PIN 1. SW_TO_GND
2. N/C 2. dv/dt 2. OVLO 2. DASIC_OFF
3. REXT 3. ENABLE 3. UVLO 3. DASIC_SW_DET
4. GND 4. ILIMIT 4. INPUT+ 4. GND
5. IOUT 5. SOURCE 5. SOURCE 5. V_MON
6. IOUT 6. SOURCE 6. SOURCE 6. VBULK
7. IOUT 7. SOURCE 7. SOURCE 7. VBULK
8. IOUT 8. VCC 8. DRAIN 8. VIN
STYLE 29: STYLE 30:
PIN 1. BASE, DIE #1 PIN 1. DRAIN 1
2. EMITTER, #1 2. DRAIN 1
3. BASE, #2 3. GATE 2
4. EMITTER, #2 4. SOURCE 2
5. COLLECTOR, #2 5. SOURCE 1/DRAIN 2
6. COLLECTOR, #2 6. SOURCE 1/DRAIN 2
7. COLLECTOR, #1 7. SOURCE 1/DRAIN 2
8. COLLECTOR, #1 8. GATE 1

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DESCRIPTION: SOIC−8 NB PAGE 2 OF 2

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