NCP1654

Power Factor Controller for

Compact and Robust,
Continuous Conduction
Mode Pre-Converters
The NCP1654 is a controller for Continuous Conduction Mode www.onsemi.com
(CCM) Power Factor Correction step−up pre−converters. It controls
the power switch conduction time (PWM) in a fixed frequency mode
8
and in dependence on the instantaneous coil current.
Housed in a SO8 package, the circuit minimizes the number of 1
external components and drastically simplifies the PFC SO−8
implementation. It also integrates high safety protection features that D SUFFIX
make the NCP1654 a driver for robust and compact PFC stages like CASE 751
an effective input power runaway clamping circuitry.
MARKING DIAGRAM
Features
• IEC61000−3−2 Compliant 8

• Average Current Continuous Conduction Mode 54Bxx

ALYW
• Fast Transient Response G
• Very Few External Components 1

• Very Low Startup Currents (< 75 mA) xx = 65, 133 or 200

• Very Low Shutdown Currents (< 400 mA) A = Assembly Location
• Low Operating Consumption L
Y
= Wafer Lot
= Year
• ±1.5 A Totem Pole Gate Drive W = Work Week
• Accurate Fully Integrated 65/133/200 kHz Oscillator G = Pb−Free Package

• Latching PWM for cycle−by−cycle Duty−Cycle Control

• Internally Trimmed Internal Reference PIN CONNECTIONS
• Undervoltage Lockout with Hysteresis
• Soft−Start for Smoothly Startup Operation Ground 1 8 Driver

• Shutdown Function VM 2 7 VCC

• Pin to Pin Compatible with Industry Standard CS 3 6 Feedback
• This is a Pb−Free Device
Brown−Out 4 5 Vcontrol
Safety Features (Top View)
• Inrush Currents Detection
• Overvoltage Protection ORDERING INFORMATION
• Undervoltage Detection for Open Loop Detection or Shutdown
Shipping†
• Brown−Out Detection
Device Package

• Soft−Start NCP1654BD65R2G SO−8 2500 / Tape &

(Pb−Free) Reel
• Accurate Overcurrent Limitation
• Overpower Limitation
NCP1654BD133R2G SO−8
(Pb−Free)
2500 / Tape &
Reel

Typical Applications NCP1654BD200R2G SO−8 2500 / Tape &

• Flat TVs, PC Desktops (Pb−Free) Reel

• AC Adapters †For information on tape and reel specifications,

• White Goods, other Off−line SMPS including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

© Semiconductor Components Industries, LLC, 2016 1 Publication Order Number:

January, 2016 − Rev. 5 NCP1654/D
 NCP1654

MAXIMUM RATINGS TABLE

Symbol Pin Rating Value Unit
DRV 8 Output Drive Capability − Source −1.5 A
Output Drive Capability − Sink +1.5

VCC 7 Power Supply Voltage, VCC pin, continuous voltage −0.3, +20 V
7 Transient Power Supply Voltage, duration < 10 ms, IVCC < 10 mA +25 V
Vin 2, 3, 4, 5, 6 Input Voltage −0.3, +10 V
Power Dissipation and Thermal Characteristics
D suffix, Plastic Package, Case 751
PD(SO) Maximum Power Dissipation @ TA = 70°C 450 MW
RqJA(SO) Thermal Resistance Junction−to−Air 178 °C/W
TJ Operating Junction Temperature Range −40 to +125 °C
TJmax Maximum Junction Temperature 150 °C
TSmax Storage Temperature Range −65 to +150 °C
TLmax Lead Temperature (Soldering, 10 s) 300 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) 2000 V per JEDEC standard JESD22, Method A114E
Machine Model (MM) 200 V (except pin#7 which complies 150 V) per JEDEC standard JESD22, Method A115A.
2. This device contains Latch−up Protection and exceeds ±100 mA per JEDEC Standard JESD78.

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 NCP1654

TYPICAL ELECTRICAL CHARACTERISTICS TABLE (VCC = 15 V, TJ from −40°C to +125°C, unless otherwise specified) (Note 3)
Symbol Rating Min Typ Max Unit
GATE DRIVE SECTION

ROH Source Resistance @ Isource = 100 mA − 9.0 20 W

ROL Sink Resistance @ Isink = −100 mA − 6.6 18 W

Tr Gate Drive Voltage Rise Time from 1.5 V to 13.5 V (CL = 2.2 nF) − 60 − ns

Tf Gate Drive Voltage Fall Time from 13.5 V to 1.5 V (CL = 2.2 nF) − 40 − ns

REGULATION BLOCK

VREF Voltage Reference 2.425 2.5 2.575 V

IEA Error Amplifier Current Capability − ±28 − mA
GEA Error Amplifier Gain 100 200 300 mS
IBpin6 Pin 6 Bias Current @ VFB = VREF −500 − 500 nA
Vcontrol Pin5 Voltage V
Vcontrol(max) Maximum Control Voltage @ VFB = 2 V − 3.6 −
Vcontrol(min) Minimum Control Voltage @ VFB = 3 V − 0.6 −
DVcontrol DVcontrol = Vcontrol(max) − Vcontrol(min) 2.7 3.0 3.3
VOUTL / VREF Ratio (VOUT Low Detect Thresold / VREF) 94 95 96 %
HOUTL / VREF Ratio (VOUT Low Detect Hysteresis / VREF) − 0.5 − %
IBOOST Pin 5 Source Current when (VOUT Low Detect) is activated 190 228 260 mA
CURRENT SENSE BLOCK
VS Current Sense Pin Offset Voltage, (ICS = 100 mA) − 10 − mV
IS(OCP) Overcurrent Protection Threshold 185 200 215 mA
POWER LIMITATION BLOCK
ICS x VBO Overpower Limitation Threshold − 200 − mVA
ICS(OPL1) Overpower Current Threshold (VBO = 0.9 V, VM = 3 V) 186 222 308 mA
ICS(OPL2) Overpower Current Threshold (VBO = 2.67 V, VM = 3 V) 62 75 110

PWM BLOCK
Dcycle Duty Cycle Range − 0−97 − %
OSCILLATOR / RAMP GENERATOR BLOCK
fsw Switching Frequency kHz
65 kHz 58 65 72
133 kHz 120 133 146
200 kHz 180 200 220
BROWN−OUT DETECTION BLOCK
VBOH Brown−Out Voltage Threshold (rising) 1.22 1.30 1.38 V
VBOL Brown−Out Voltage Threshold (falling) 0.65 0.7 0.75 V
IIB Pin 4 Input Bias Current @ VBO = 1 V −500 − 500 nA
CURRENT MODULATION BLOCK
IM1 Multiplier Output Current (Vcontrol = Vcontrol(max), VBO = 0.9 V, ICS = 25 mA) − 1.9 − mA
IM2 Multiplier Output Current (Vcontrol = Vcontrol(max), VBO = 0.9 V, ICS = 75 mA)
(@ 0  125°C) 1.5 4.7 8.8
(@ −40  125°C) 1.5 4.7 9.8
IM3 Multiplier Output Current (Vcontrol = Vcontrol(min) + 0.2 V, VBO = 0.9 V, ICS = 25 mA − 28.1 −
IM4 Multiplier Output Current (Vcontrol = Vcontrol(min) + 0.2 V, VBO = 0.9 V, ICS = 75 mA − 84.4 −

OVERVOLTAGE PROTECTION
VOVP / VREF Ratio (Overvoltage Threshold / VREF) 103 105 107 %
TOVP Propagation Delay (VFB – 107% VREF) to Drive Low − 500 − ns

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 NCP1654

TYPICAL ELECTRICAL CHARACTERISTICS TABLE (VCC = 15 V, TJ from −40°C to +125°C, unless otherwise specified) (Note 3)
Symbol Rating Min Typ Max Unit
UNDERVOLTAGE PROTECTION / SHUTDOWN
VUVP(on)/VREF UVP Activate Threshold Ratio (TJ = 0°C to +105°C) 4 8 12 %
VUVP(off)/VREF UVP Deactivate Threshold Ratio (TJ = 0°C to +105°C) 6 12 18 %
VUVP(H) UVP Lockout Hysteresis − 4 − %
TUVP Propagation Delay (VFB < 8% VREF) to Drive Low − 500 − ns
THERMAL SHUTDOWN
TSD Thermal Shutdown Threshold 150 − − °C
HSD Thermal Shutdown Hysteresis − 30 − °C
VCC UNDERVOLTAGE LOCKOUT SECTION
VCC(on) Start−Up Threshold (Undervoltage Lockout Threshold, VCC rising) 9.6 10.5 11.4 V
VCC(off) Disable Voltage after Turn−On (Undervoltage Lockout Threshold, VCC falling) 8.25 9.0 9.75 V
VCC(H) Undervoltage Lockout Hysteresis 1.0 1.5 − V
DEVICE CONSUMPTION
Power Supply Current:
ISTUP Start−Up (@ VCC = 9.4 V) − − 75 mA
ICC1 Operating (@ VCC = 15 V, no load, no switching) − 3.7 5.0 mA
ICC2 Operating (@ VCC = 15 V, no load, switching) − 4.7 6.0 mA
ISTDN Shutdown Mode (@ VCC = 15 V and VFB = 0 V) − 300 400 mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. The above specification gives the targeted values of the parameters. The final specification will be available once the complete circuit
characterization has been performed.
Ics V BO
NOTE: IM +
4 ǒVcontrol * Vcontrol(min)Ǔ

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 NCP1654

DETAILED PIN DESCRIPTIONS

Pin Symbol Name Function
1 GND Ground −

2 Vin Multiplier This pin provides a voltage VM for the PFC duty cycle modulation. The input impedance of the
Voltage PFC circuits is proportional to the resistor RM externally connected to this pin. The device
operates in average current mode if an external capacitor CM is connected to the pin.
Otherwise, it operates in peak current mode.
3 CS Current Sense This pin sources a current ICS which is proportional to the inductor current IL. The sense
Input current ICS is for overcurrent protection (OCP), overpower limitation (OPL) and PFC duty cycle
modulation. When ICS goes above 200 mA, OCP is activated and the Drive Output is disabled.
4 VBO Brown−Out / In Connect a resistor network among the rectified input voltage, BO pin, and ground. And connect
a capacitor between BO pin and ground. BO pin detects a voltage signal proportional to the
average input voltage.
When VBO goes below VBOL, the circuit that detects too low input voltage conditions
(brown−out), turns off the output driver and keeps it in low state until VBO exceeds VBOH.
This signal which is proportional to the RMS input voltage Vac is also for overpower limitation
(OPL) and PFC duty cycle modulation.
5 Vcontrol Control Voltage / The voltage of this pin Vcontrol directly controls the input impedance. This pin is connected to
Soft−Start external type−2 compensation components to limit the Vcontrol bandwidth typically below 20 Hz
to achieve near unity power factor.
The device provides no output when Vcontrol < Vcontrol(min). When it starts operation, the power
increases slowly (soft−start).
6 VFB Feed−Back / This pin receives a feedback signal VFB that is proportional to the PFC circuits output voltage.
Shutdown This information is used for both the output regulation, the overvoltage protection (OVP), and
output undervoltage protection (UVP) to protect the system from damage at feedback
abnormal situation.
When VFB goes above 105% VREF, OVP is activated and the Drive Output is disabled.
When VFB goes below 8% VREF, the device enters a low−consumption shutdown mode.

7 VCC Supply Voltage This pin is the positive supply of the IC. The circuit typically starts to operate when VCC
exceeds 10.5 V and turns off when VCC goes below 9 V. After start−up, the operating range is
9 V up to 20 V.
8 DRV Drive Output The high current capability of the totem pole gate drive (±1.5 A) makes it suitable to effectively
drive high gate charge power MOSFET.

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 NCP1654

Iin Vin
+ L IL
IN + Output
AC EMI
Cfilter Cbulk Voltage
Input Filter
(VOUT)
−
RSENSE IL

OVP
+
-
105% Vref
- UVP
RboU + BO
OPL Vdd
8% Vref with 4% Vref
Vdd Hysteresis
UVLO Undervoltage
RfbU Soft Start 200 mA
Lock−Out

FB 6 Reference
Q
R Block
Vref
RfbL
- Off
+ Bias Block
95% Vref Vout Low Detect UVP BO
- OTA Iref Vdd
Vref +
Vcontrol ±28 mA Vcc

5 7
RZ + Output
CP Vcontrol(min) Buffer 8
DRV
CZ 1
GND
Thermal
Shutdown

BO
Q
4 Fault PWM
RboL R
- BO Latch
CBO +
VboH / VboL R S
OL OVP
VboH = 1.3 V, VboL = 0.7 V
Vref -
+
Vdd Vramp
Vdd Vdd
Current Mirror + -
Ics Ics
Vbo Iref Vref/10% Vref

Ics Division + Vm
RCS RM
CS C1 2
Ics*Vbo > 200 mVA S1
65/133/200 kHz CM
3
Oscillator
OPL
OL
Ics > 200 mA Im = (Ics*Vbo) / (4*(Vcontrol − Vcontrol(min))
OCP

Figure 1. Functional Block Diagram

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 NCP1654

TYPICAL CHARACTERISTICS

10 2.60
ROH & ROL, GATE DRIVE

8
2.55
RESISTANCE (W)

ROH
6

VREF (V)
2.50
4

ROL
2.45
2

0 2.40
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 2. Gate Drive Resistance vs. Figure 3. Reference Voltage vs. Temperature
Temperature

32 −20

30 −22

28 −24
IEA_source (A)

IEA_sink (A)

26 −26

24 −28

22 −30

20 −32
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 4. Source Current Capability of the Figure 5. Sink Current Capability of the Error
Error Amplifier vs. Temperature Amplifier vs. Temperature

300 150

100
250
50
IBpin6 (nA)
GEA (mS)

200 0

−50
150
−100

100 −150
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 6. Error Amplifier Gain vs. Temperature Figure 7. Feedback Pin Current vs.
Temperature (@Vfb = VREF)

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 NCP1654

TYPICAL CHARACTERISTICS

4.0 3.3

3.9 3.2

3.8
VCONTROL(max) (V)

DVCONTROL (V)
3.1
3.7
3.0
3.6
2.9
3.5

3.4 2.8

3.3 2.7
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 8. Vcontrol Maximum Voltage vs. Figure 9. Vcontrol Maximum Swing (DVCONTROL)
Temperature vs. Temperature

95.1 260

95.0 250
94.9
240
VoutL / VREF (%)

94.8
IBoost (mA)

230
94.7
220
94.6
210
94.5

94.4 200

94.3 190
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 10. Ratio (VOUT Low Detect Threshold / Figure 11. Pin 5 Source Current when (VOUT
VREF) vs. Temperature Low Detect) is Activated vs. Temperature

215 306

210 286

205 266
ICS(OPL1) (mA)
IS(OCP) (mA)

200 246

195 226

190 206

185 186
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 12. Over−Current Protection Threshold Figure 13. Over−Power Current Threshold
vs. Temperature (@VBO = 0.9 V & Vm = 3 V) vs. Temperature

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 NCP1654

TYPICAL CHARACTERISTICS

110 100

MAXIMUM DUTY CYCLE (%)

100 99
ICS(OPL2) (mA)

90 98

80 97

70 96

60 95
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 14. Over−Power Current Threshold Figure 15. Maximum Duty Cycle vs.
(@VBO = 2.67 V & Vm = 3 V) vs. Temperature Temperature

72 140

70 138

68 136
fSW (kHz)

fSW (kHz)

66 134

64 132

62 130

60 128

58 126
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 16. Switching Frequency vs. Figure 17. Switching Frequency vs.
Temperature (65 kHz Version) Temperature (133 kHz Version)
210

205

200
fSW (kHz)

195

190

185

180
−50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C)
Figure 18. Switching Frequency vs.
Temperature (200 kHz Version)

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 NCP1654

TYPICAL CHARACTERISTICS

1.40 0.75

1.35
VBOH (V)

VBOL (L)
1.30 0.70

1.25

1.20 0.65
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 19. Brown−Out Voltage Threshold Figure 20. Brown−Out Voltage Threshold
(Rising) vs. Temperature (Falling) vs. Temperature
7.5 2.66

6.5
2.64

5.5
VOVP (V)
Im2 (mA)

2.62
4.5

2.60
3.5

2.5 2.58
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 21. Multiplier Output Current (Vcontrol = Figure 22. Over Voltage Threshold vs.
VCONTROL(max), Vbo = 0.9 V, ICS = 75 mA) vs. Temperature
Temperature
107 16
VUVP(on) / VREF and VUVP(off) / VREF (%)

14

106 12
VOVP / VREF (%)

10

105 8

104 4

2
103 0
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 23. Ratio (Over Voltage Threshold / Figure 24. UVP Activate and Deactivate
VREF) vs. Temperature Threshold Ratio vs. Temperature

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 NCP1654

TYPICAL CHARACTERISTICS

11.4 9.7
11.2
9.5
11.0
9.3
10.8

VCC(off) (V)
VCC(on) (V)

10.6 9.1

10.4 8.9
10.2
8.7
10.0
8.5
9.8
9.6 8.3
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 25. VCC Start−Up Threshold (VCC Figure 26. VCC Disable Voltage after Turn−On
Rising) vs. Temperature (VCC Falling) vs. Temperature
2.0 50

1.8 40
ISTUP (mA)
VCC(H) (V)

1.6 30

1.4 20

1.2 10

1.0 0
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 27. VCC UVLO Hysteresis vs. Figure 28. Supply Current in Startup Mode vs.
Temperature Temperature

400 4
OPERATING CURRENT (mA)

350 3 ICC2, No Load, Switching

ISTDN (mA)

ICC1, No Load, No Switching

300 2

250 1

200 0
−50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)

Figure 29. Supply Current in Shutdown Mode Figure 30. Operating Supply Current vs.
vs. Temperature Temperature

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 NCP1654

Detailed Operating Description regulation level. In this case, the circuit turns off and
its consumption drops to a very low value. This
Introduction feature protects the PFC stage from starting
The NCP1654 is a PFC driver designed to operate in operation in case of low AC line conditions or in
fixed frequency, continuous conduction mode. The fixed case of a failure in the feed−back network (i.e. bad
frequency operation eases the compliance with EMI connection).
standard and the limitation of the possible radiated noise − Fast Transient Response: given the low bandwidth
that may pollute surrounding systems. In addition, of the regulation block, the output voltage of PFC
continuous conduction operation reduces the application stages may exhibit excessive over or under−shoots
di/dt and their resulting interference. More generally, the because of abrupt load or input voltage variations
NCP1654 is an ideal candidate in systems where (e.g. at start up). If the output voltage is too far from
cost−effectiveness, reliability and high power factor are the the regulation level:
key parameters. It incorporates all the necessary features to Overvoltage Protection: NCP1654 turns off the
build a compact and rugged PFC stage: power switch as soon as Vout exceeds the OVP
• Compactness and Flexibility: housed in a SO8 threshold (105% of the regulation level). Hence
package, the NCP1654 requires a minimum of a cost & size effective bulk capacitor of lower
external components. In particular, the circuit scheme voltage rating is suitable for this application,
simplifies the PFC stage design and eliminates the Dynamic Response Enhancer: NCP1654
need for any input voltage sensing. In addition, the drastically speeds up the regulation loop by its
circuit offers some functions like the Brown−Out or internal 200ĂmA enhanced current source when the
the true power limiting that enable the optimizations output voltage is below 95% of its regulation level.
of the PFC design, − Brown−Out Detection: the circuit detects low AC
• Low Consumption and Shutdown Capability: the line conditions and disables the PFC stage in this
NCP1654 is optimized to exhibit consumption as case. This protection mainly protects the power
small as possible in all operation modes. The switch from the excessive stress that could damage it
consumed current is particularly reduced during the in such conditions,
start−up phase and in shutdown mode so that the PFC − Over−Power Limitation: the NCP1654 computes the
stage power losses are extremely minimized when the maximum permissible current in dependence of the
circuit is disabled. This feature helps meet the more average input voltage measured by the brown−out
stringent stand−by low power specifications. Just block. It is the second OCP with a threshold that is
ground the Feed−back pin to force the NCP1654 in line dependent. When the circuit detects an
shutdown mode, excessive power transfer, it resets the driver output
• Safety Protections: the NCP1654 permanently monitors immediately,
the output voltage, the coil current and the die − Thermal Shutdown: an internal thermal circuitry
temperature to protect the system from possible disables the circuit gate drive and then keeps the
power switch off when the junction temperature
over−stresses. Integrated protections (Overvoltage
exceeds 150°C typically. The circuit resumes
protection, coil current limitation, thermal shutdown...)
operation once the temperature drops below about
make the PFC stage extremely robust and reliable:
120°C (30°C hysteresis),
− Maximum Current Limit: the circuit permanently
− Soft Start: Vcontrol is pulled low brown−out detection
senses the coil current and immediately turns off the
activates, or Undervoltage protection activates, and
power switch if it is higher than the set current limit.
no drive is provided.
The NCP1654 also prevents any turn on of the
At start up, the “200 mA enhanced current source” is
power switch as long as the coil current is not below
disabled. So there is only 28 mA to charge the
its maximum permissible level. This feature protects
compensation components, and makes Vcontrol raise
the MOSFET from possible excessive stress that
gradually. This is to obtain a slow increasing duty
could result from the switching of a current higher
cycle and hence reduce the voltage and current
than the one the power switch is dimensioned for. In
stress on the MOSFET. Hence it provides a soft−start
particular, this scheme effectively protects the PFC
feature.
stage during the start−up phase when large in−rush
currents charge the output capacitor. • Output Stage Totem Pole: the NCP1654 incorporates
− Undervoltage Protection for Open Loop Protection a ±1.5A gate driver to efficiently drive TO220 or
or Shut−down: the circuit detects when the TO247 power MOSFETs.
feed−back voltage goes below than about 8% of the

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 NCP1654

PRINCIPLE OF NCP1654 SCHEME The input filter capacitor Cfilter and the front−ended EMI
filter absorbs the high−frequency component of inductor
CCM PFC Boost
current IL. It makes the input current Iin a low−frequency
A CCM PFC boost converter is shown in Figure 31. The
signal only of the inductor current.
input voltage is a rectified 50 ro 60 Hz sinusoidal signal.
The MOSFET is switching at a high frequency (typically Iin + I L*50 (eq. 2)
65/133/200 kHz in NCP1654) so that the inductor current where
IL basically consists of high and low−frequency
Iin is the input AC current.
components.
Filter capacitor Cfilter is an essential and very small value IL is the inductor current.
capacitor in order to eliminate the high−frequency IL−50 supposes a 50 Hz operation. The suffix 50 means
component of the inductor IL. This filter capacitor cannot it is with a 50 Hz bandwidth of the original IL.
be too bulky because it can pollute the power factor by From (Equation 1) and (Equation 2), the input
distorting the rectified sinusoidal input voltage. impedance Zin is formulated.
V in T * t1 Vout
L Zin + + (eq. 3)
Iin IL Vout Iin T IL*50
Vin
Output where Zin is input impedance.
+
Cfilter Voltage
Power factor is corrected when the input impedance Zin
Cbulk
in (Equation 3) is constant or varies slowly in the 50 or 60
RSENSE Hz bandwidth.

VM Vref
Figure 31. CCM PFC Boost Converter
Ich PFC Modulation
-
PFC Methodology R Q
+ +
The NCP1654 uses a proprietary PFC methodology Vramp
0 1 S
particularly designed for CCM operation. The PFC Cramp
methodology is described in this section.
IL Clock
Iin
Vref

Vramp
VM
t1 t2 Time
VM without
T Filtering
Clock

Figure 32. Inductor Current in CCM Latch Set

Latch Reset
As shown in Figure 32, the inductor current IL in a
switching period T includes a charging phase for duration Output
t1 and a discharging phase for duration t2. The voltage
conversion ratio is obtained in (Equation 1).
Inductor
Vout t ) t2
+ T
Current
+ 1
Vin t2 T * t1
T * t1 Figure 33. PFC Duty Modulation and Timing Diagram
Vin + Vout (eq. 1)
T
The PFC modulation and timing diagram is shown in
where
Figure 33. The MOSFET on time t1 is generated by the
Vout is the output voltage of PFC stage, intersection of reference voltage VREF and ramp voltage
Vin is the rectified input voltage, Vramp. A relationship in (Equation 4) is obtained.
T is the switching period, Icht1
Vramp + V m ) + V REF (eq. 4)
t1 is the MOSFET on time, and C ramp
t2 is the MOSFET off time. where

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 NCP1654

Vramp is the internal ramp voltage, the positive input of the R MIcsVbo Vm Im
PFC modulation comparator, Vm +
4(Vcontrol * VCONTROL(min))
2
Vm is the multiplier voltage appearing on Vm pin, RM CM
Ich is the internal charging current, PFC Duty
Cramp is the internal ramp capacitor, and Modulation

VREF is the internal reference voltage, the negative input of Figure 35. External Connection on the Multiplier
the PFC modulation comparator. Voltage Pin
Ich, Cramp, and VREF also act as the ramp signal of
switching frequency. Hence the charging current Ich is The multiplier voltage Vm is generated according to
specially designed as in (Equation 5). The multiplier (Equation 8).
voltage Vm is therefore expressed in terms of t1 in RMI csVbo
(Equation 6). Vm + (eq. 8)
4(V control * V CONTROL(min))
C rampVREF
Ich + (eq. 5) Where,
T
RM is the external multiplier resistor connected to Vm pin,
t1 CrampV REF T * t1
Vm + V REF * + VREF (eq. 6) which is constant.
C ramp T T
Vbo is the input voltage signal appearing on the BO pin,
From (Equation 3) and (Equation 6), the input impedance which is proportional to the rms input voltage,
Zin is re−formulated in (Equation 7).
Ics is the sense current proportional to the inductor current
V Vout IL as described in (Equation 11).
Zin + m (eq. 7)
V REF IL*50
Vcontrol is the control voltage signal, the output voltage of
Because VREF and Vout are roughly constant versus time, Operational Trans−conductance Amplifier (OTA), as
the multiplier voltage Vm is designed to be proportional to described in (Equation 12).
the IL−50 in order to have a constant Zin for PFC purpose. RM directly limits the maximum input power capability
It is illustrated in Figure 34. and hence its value affects the NCP1654 to operate in either
“follower boost mode” or “constant output voltage mode”.

Vin Vin
+

Iin Time
RboU
IL
Vbo
Time
4 BO
VM RboL -
Time CBO +

VboH / VboL
Figure 34. Multiplier Voltage Timing Diagram VboH = 1.3 V, VboL = 0.7 V

Figure 36. External Connection on the Brown Out Pin

It can be seen in the timing diagram in Figure 33 that Vm
originally consists of a switching frequency ripple coming Refer to Figure 36,
from the inductor current IL. The duty ratio can be
2 Ǹ2
inaccurately generated due to this ripple. This modulation Vbo + K BO(Vin) + KBO @ p V ac (eq. 9)
is the so−called “peak current mode”. Hence, an external
RboL
capacitor CM connected to the multiplier voltage Vm pin is KBO + (eq. 10)
R boU ) R boL
essential to bypass the high−frequency component of Vm.
The modulation becomes the so−called “average current where
mode” with a better accuracy for PFC.
Vbo is the voltage on BO pin.
KBO is the decay ratio of Vin to Vbo.
<Vin> is the average voltage signal of Vin, the voltage
appearing on Cfilter.
Vac is the RMS input voltage.

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 NCP1654

RboL is low side resistor of the dividing resistors between Refer to Figure 37, sense current Ics is proportional to the
Vin and BO pin. inductor current IL as described in (Equation 11). IL
RboU is upper side resistor of the dividing resistors between consists of the high−frequency component (that depends on
Vin and BO pin. di/dt or inductor L) and low−frequency component (that is
IL−50).
IL
R SENSE
Ics + I (eq. 11)
RCS L

ICS CS + where
NCP1654
RCS + RSENSE is the sense resistor to sense IL.
VCS
Gnd RCS is the offset resistor between CS pin and RSENSE.
−

RSENSE IL

Figure 37. Current Sensing

Vin Vout
+

RfbU
Vfb
6
RfbL
- ±20 mA
VREF + +
Vcontrol OTA
VCONTROL(min)
5
CP RZ
CZ
To Vm Pin

Figure 38. Vcontrol Low−Pass Filtering

Refer to Figure 38, the Operational Trans−conductance From (Equation 7) − (Equation 11), the input impedance
Amplifier (OTA) senses Vout via the feedback resistor Zin is re−formulated in (Equation 13).
dividers, RfbU and RfbL. The OTA constructs a control Ǹ2 R R (eq. 13)
M SENSEV outV acK BOI L
voltage, Vcontrol, depending on the output power and hence Zin +
2pR CS @ (V control * V CONTROL(min)) @ V REFIL*50
Vout. The operating range of Vcontrol is from
VCONTROL(min) to VCONTROL(max). The signal used for When IL is equal to IL−50, (Equation 13) is re−formulated
PFC duty modulation is after decreasing a offset voltage, in (Equation 14)
VCONTROL(min), i.e. Vcontrol−VCONTROL(min). Ǹ2 R R
M SENSEV outV acK BO
This control current Icontrol is a roughly constant current Zin + (eq. 14)
2pR CS @ (V control * V CONTROL(min)) @ V REF
that comes from the PFC output voltage Vout that is a slowly
varying signal. The bandwidth of Icontrol can be The multiplier capacitor CM is the one to filter the
additionally limited by inserting the external type−2 high−frequency component of the multiplier voltage Vm.
compensation components (that are RZ, CZ, and CP as The high−frequency component is basically coming from
shown in Figure 38). It is recommended to limit fcontrol, that the inductor current IL. On the other hand, the filter
is the bandwidth of Vcontrol (or Icontrol), below 20 Hz capacitor Cfilter similarly removes the high−frequency
typically to achieve power factor correction purpose. component of inductor current IL. If the capacitors CM and
The transformer of Vout to Vcontrol is as described in Cfilter match with each other in terms of filtering capability,
(Equation 12) if CZ is >> CP. GEA is the error amplifier gain. IL becomes IL−50. Input impedance Zin is roughly constant
Vcontrol R @ G EARZ 1 ) sRZC Z over the bandwidth of 50 or 60 Hz and power factor is
+ fbL @ (eq. 12) corrected.
V out RfbL ) RfbU sRZC Z(1 ) sR ZCP)

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 NCP1654

Input and output power (Pin and Pout) are derived in (Equation 15) when the circuit efficiency η is obtained or assumed.
The variable Vac stands for the rms input voltage.
V ac 2 2pRCS @ (V control * V CONTROL(min)) @ V REF @ V ac
Pin + + (eq. 15)
Z in Ǹ2 R R V K
M SENSE out BO

(V control * V CONTROL(min))Vac
T
V out

2pRCS @ (Vcontrol * VCONTROL(min)) @ VREF @ Vac

Pout + h P in + h (eq. 16)
Ǹ2 R R V K
M SENSE out BO

(V control * V CONTROL(min))Vac
T
V out
Follower Boost VCONTROL(max). Re−formulate (Equation 16) to become
The “Follower Boost” is an operation mode where the (Equation 17) and (Equation 18) by replace Vcontrol by
pre−converter output voltage stabilizes at a level that varies VCONTROL(max). If Vcontrol is constant based on
linearly versus the ac line amplitude. This technique aims (Equation 15), for a constant load or power demand the
at reducing the gap between the output and input voltages output voltage Vout of the converter is proportional to the
to optimize the boost efficiency and minimize the cost of rms input voltage Vac. It means the output voltage Vout
the PFC stage (refer to MC33260 data sheet for more becomes lower when the rms input voltage Vac becomes
details at http://www.onsemi.com ). lower. On the other hand, the output voltage Vout becomes
The NCP1654 operates in follower boost mode when lower when the load or power demand becomes higher.
Vcontrol is constant, i.e. Vcontrol raises to its maximum value
2pR CS @ (VCONTROL(max) * VCONTROL(min)) @ VREF @ Vac
Pout + h (eq. 17)
Ǹ2 R R V K
M SENSE out BO

2pRCS @ DVCONTROL @ VREF @ Vac

+h
Ǹ2 R R V K
M SENSE out BO

2pR CS @ DVCONTROL @ VREF V ac

Vout + h @ (eq. 18)
Ǹ2 R R K Pout
M SENSE BO
where the output voltage Vout will always be higher than the input
VCONTROL(max) is the maximum control voltage. voltage Vin even though Vout is reduced in follower boost
operation. As a result, the on time t1 is reduced. Reduction
DVCONTROL is the gap between VCONTROL(max) and
of on time makes the loss of the inductor and power
VCONTROL(min).
MOSFET smaller. Hence, it allows cheaper cost in the
It is illustrated in Figure 39. inductor and power MOSFET or allows the circuit
components to operate at a lower stress condition in most
Vout (Traditional Boost) of the time.

Reference Section
Vout (Follower Boost)
The internal reference voltage (VREF) is trimmed to be
Vin ±2% accurate over the temperature range (the typical value
is 2.5 V). VREF is the reference used for the regulation.
Time
VREF also serves to build the thresholds of the fast transient
response, Overvoltage (OVP), brown out (BO), and
Pout Undervoltage protections (UVP).
Time
Output Feedback
Figure 39. Follower Boost Characteristics The output voltage Vout of the PFC circuits is sensed at
Vfb pin via the resistor divider (RfbL and RfbU) as shown in
Follower Boost Benefits Figure 38. Vout is regulated as described in (Equation 19).
The follower boost circuit offers and opportunity to
RfbU ) RfbL
reduce the output voltage Vout whenever the rms input Vout + V REF (eq. 19)
R fbL
voltage Vac is lower or the power demand Pout is higher.
Because of the step−up characteristics of boost converter,

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 NCP1654

The feedback signal Vfb represents the output voltage Fast Transient Response
Vout and will be used in the output voltage regulation, Given the low bandwidth of the regulation block, the
Overvoltage protection (OVP), fast transient response, and output voltage of PFC stages may exhibit excessive over or
Undervoltage protection (UVP) under−shoots because of abrupt load or input voltage
variations (such as start−up duration). As shown in
Output Voltage Regulation Figure 40, if the output voltage is out of regulation,
NCP1654 uses a high gain Operational Trans− NCP1654 has 2 functions to maintain the output voltage
conductance Amplifier (OTA) as error amplifier. Refer to regulation.
Figure 38, the output of OTA Vcontrol operating range is
from VCONTROL(min) to VCONTROL(max).
Vout
+

Vdd

OVP
- 200 mA
RfbU 105% +
Vfb VREF
-
CFB 6 95% +
RfbL Vout Low Detect
VREF
- ±20 mA
VREF +
Vcontrol OTA

Figure 40. OVP and Fast Transient Response

• Overvoltage Protection: When Vfb is higher than condition, the maximum sink and source of output
105% of VREF (i.e. Vout > 105% of nominal output current capability of OTA is around 28 mA. Thanks to
voltage), the Driver output of the device goes low for the “Vout low detect” block, when the Vfb is below
protection. The circuit automatically resumes 95% VREF, an extra 200 mA current source will raise
operation when Vfb becomes lower than 105% of Vcontrol rapidly. Hence prevent the PFC output from
VREF. If the nominal Vout is set at 390 V, then the dropping too low and improve the transient response
maximum output voltage is 105% of 390 V = 410 V. performance. The relationship between current
Hence a cost & size effective bulk capacitor of lower flowing in/out Vcontrol pin and Vfb is as shown in
voltage rating is suitable for this application, Figure 41.
• Dynamic response enhancer: NCP1654 drastically It is recommended to add a typical 100 pF capacitor CFB
speeds up the regulation loop by its internal 200 mA decoupling capacitor next to feedback pin to prevent from
enhanced current source when the output voltage is noise impact.
below 95% of its regulation level. Under normal
VCONTROL PIN CURRENT (mA)

50
200 mA raises
0 Vcontrol rapidly
−50 when Vfb is below
95% VREF
−100
No DRV when
−150
Vfb is above
−200 105% VREF
−250
2 2.2 2.4 2.6 2.8 3
Vfb
Figure 41. Vfb vs. Current Flowing in/out from Vcontrol Pin

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 NCP1654

Soft Start
The block diagram and timing diagram of soft start Off BO UVLO UVP
Vdd
function are as shown in Figure 42 and Figure 43. The
device provides no output (or no duty ratio) when the Bias
Vcontrol is lower than VCONTROL(min). Vcontrol is pulled low
when:
• Brown−out, or Vdd
• Undervoltage Protection S Q
When the IC recovers from one of the following 200 mA
R Q
conditions; Undervoltage Lockout, Brown−out or
Undervoltage Protection, the 200 mA current source block
Vfb -
keeps off. Hence only the Operating Trans−conductance
6 95% +
Amplifier (OTA) raises the Vcontrol. And Vcontrol rises Vout Low Detect
VREF
slowly. This is to obtain a slow increasing duty cycle and - ±20 mA
hence reduce the voltage and current stress on the VREF +
Vcontrol OTA
MOSFET. A soft−start operation is obtained.
5 BO UVLO

Figure 42. Soft Start Block Diagram

Period I Period II
UVLO, BO, or UVP

Vdd

Vdd Rising

Vfb
95% VREF

Vout Low Detect

Set

Reset

Figure 43. Soft Start Timing Diagram

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 NCP1654

Undervoltage Protection (UVP) for Open Loop PFC duty modulation to generate the multiplier voltage
Protection or Shutdown Vm, Over−Power Limitation (OPL), and Over−Current
Protection. (Equation 11) would insist in the fact that it
provides the flexibility in the RSENSE choice and that it
allows to detect in−rush currents.
ISTDN
Shutdown Operating Over−Current Protection (OCP)
Over−Current Protection is reached when Ics is larger
ICC2 than IS(OCP) (200 mA typical). The offset voltage of the CS
Vfb pin is typical 10 mV and it is neglected in the calculation.
8% VREF 12% VREF Hence, the maximum OCP inductor current threshold
IL(OCP) is obtained in (Equation 20).
Figure 44. Undervoltage Protection
R CSIS(OCP) R CS
IL(OCP) + + @ 200 mA (eq. 20)
As shown in Figure 44, when Vfb is less than 8% of VREF, R SENSE RSENSE
the device is shut down and consumes less than 400 mA. When over−current protection threshold is reached, the
The device automatically starts operation when the output Drive Output of the device goes low. The device
voltage goes above 12% of VREF. In normal situation of automatically resumes operation when the inductor current
boost converter configuration, the output voltage Vout is goes below the threshold.
always greater than the input voltage Vin and the feedback
signal Vfb is always greater than 8% and 12% of VREF to Input Voltage Sense
enable NCP1654 to operate. The device senses the rms input voltage Vac by the
This Undervoltage Protection function has 2 purposes. sensing scheme in Figure 45. Vbo senses the average
rectified input voltage Vin via the resistor divider. An
• Open Loop Protection − Protect the power stage from external capacitor CBO is to maintain the Vbo the average
damage at feedback loop abnormal, such as Vfb is
value of Vin. Vbo is used for Brown−Out Protection, PFC
shorted to ground or the feedback resistor RfbU is
duty modulation and over−power limitation (OPL).
open.
• Shutdown mode − Disables the PFC stage and forces a Brown−Out Protection
low consumption mode. This feature helps to meet The device uses the Vbo signal to protect the PFC stage
stringent stand−by specifications. Power Factor being from operating as the input voltage is lower than expected.
not necessary in stand−by, the PFC stage is generally Re−formulate (Equation 9) to get (Equation 21). Refer to
inhibited to save the pre−converter losses. To further Figure 45, Vin is different before and after the device
improve the stand−by performance, the PFC controller operating.
should consume minimum current in this mode. • Before the device operates, Vin is equal to the peak
value of rms input voltage, Vac. Hence Vbo is as
Current Sense described in (Equation 21).
The device senses the inductor current IL by the current
RboL RboL Ǹ2 V
sense scheme in Figure 37. The device maintains the Vbo + (V ) + ac (eq. 21)
voltage at CS pin to be zero voltage (i.e., Vcs ≈ 0 V) so that R boL ) R boU in R boL ) R boU
(Equation 11), • After device operates, Vin is the rectified sinusoidal
R input voltage. Thanks to CBO, Vbo is the average of
Ics + SENSE IL ,
RCS rectified input voltage. Hence Vbo decays to 2/p of the
can be formulated. peak value of rms input voltage Vac as described in
This scheme has the advantage of the minimum number (Equation 22).
of components for current sensing. The sense current Ics RboL 2 Ǹ2
Vbo + Vac (eq. 22)
represents the inductor current IL and will be used in the R boL ) R boU p

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 NCP1654

Before Device Operates After Device Operates

Vin
+
Vac IN +

RboU
Vbo
- BO
4
+
RboL CBO
VboH / VboL
VboH = 1.3 V, VboL = 0.7 V

Figure 45. Brown−Out Protection

Hence a larger hysteresis of the brown out comparator is Overpower Limitation (OPL)
needed, which is 0.7 V typical in this device. When Vbo This is a second OCP with a threshold that is line
goes below than VBOL (0.7 V typical), the device turns off dependent. Sense current Ics represents the inductor current
the Drive output and keeps it off till Vbo exceeds VBOH IL and hence represents the input current approximately.
(1.3 V typical). When the device awakes after an off−state Input voltage signal Vbo represents the rms input voltage.
(Undervoltage lockout or shutdown), the default threshold The product (Ics ⋅ Vbo) represents an approximated input
is VBOH. power (IL ⋅ Vac). It is illustrated in Figure 46.
Vin

RSENSE IL

RSENSE
ICS + I L
CS
R CS
RCS ICS OPL
Current Mirror
3
4
>200 mVA?
Vbo

Figure 46. Over−Power Limitation

When the product (Ics ⋅ Vbo) is greater than a permissible Bias the Controller
level 200 mVA, the device turns off the drive output so that It is recommended to add a typical 1 nF to 100 nF
the input power is limited. The OPL is automatically decoupling capacitor next to the Vcc pin for proper
deactivated when the product (Ics ⋅ Vbo) is lower than the operation. When the NCP1654 operates in follower boost
200 mVA level. This 200 mVA level corresponds to the mode, the PFC output voltage is not always regulated at a
approximated input power (IL ⋅ Vac) to be smaller than the particular level under all application range of input voltage
particular expression in (Equation 23). and load power. It is not recommended to make a
IcsV bo t 200 mVA low−voltage bias supply voltage by adding an auxiliary

Ǔǒ Ǔ
(eq. 23) winding on the PFC boost inductor. Alternatively, it is
ǒ R
IL SENSE @
R CS
2 Ǹ2 K BO
p @ V ac t 200 mVA
recommended to get the Vcc biasing supply from the
2nd−stage power conversion stage.
RCS @ p
IL @ V ac t @ 50 Ǹ2 mVA
R SENSE @ K BO

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 NCP1654

Vcc Undervoltage LockOut (UVLO) comparator incorporates some hysteresis (1.5 V) to prevent
The device incorporates an Undervoltage Lockout block erratic operation as the Vcc crosses the threshold. When Vcc
to prevent the circuit from operating when Vcc is too low goes below the UVLO comparator lower threshold (9 V
in order to ensure a proper operation. An UVLO typically), the circuit turns off. It is illustrated in Figure 47.
comparator monitors Vcc pin voltage to allow the NCP1654 After startup, the operating range is between 9 V and 20 V.
to operate when Vcc exceeds 10.5 V typically. The

ON
State

OFF
VCC

6 mA
ICC

<75 mA
VCC
VCC(OFF) VCC(ON)

Figure 47. Vcc Undervoltage LockOut (UVLO)

Thermal Shutdown enabled once the temperature drops below typically 120°C
An internal thermal circuitry disables the circuit gate (i.e., 30°C hysteresis). The thermal shutdown is provided
drive and then keeps the power switch off when the junction to prevent possible device failures that could result from an
temperature exceeds 150°C. The output stage is then accidental overheating.

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 NCP1654

TB2

1 2
390 V

C4 TB3
180 mF, 450 V
+

D1 MSR860G 1 2

SPP20N60S5
Q1 +15 V C8
+
R1 1.8 M R4 1N4148
C9 22 mF
10 k D2
C10
0.1 mF
R2 1.8 M R5 10
100 pF
R3

23.2 k
2.2 mF

Vcontrol
R12 C12

VCC
DRV
12 k C5

FB
5
8 7 6 5 220 nF

NCP1654
L1 650 mH R6 0.1
IC1
1 2 3 4
GND

CS

BO
VM

2 R8

R7 47 k

3.6 k 1 nF C6

R9 R13 R10 R11

0.1 mF 3.3 M 3.3 M 0 82.5 k
GBU8J
600 V + C7
8A C3

0.47 mF
−
DB1
C2

0.47 mF

L2 2 x 6.8 mH

L3 150 mH
C1

0.47 mF
5 A Fuse
F1
1 2 3
L N
AC Inlet TB1

Figure 48. Application Schematic − 300 W 65 kHz

Power Factor Correction Circuit

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 NCP1654

PACKAGE DIMENSIONS

SO−8
D SUFFIX
CASE 751−07
ISSUE AJ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
−X− ANSI Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
8 5 PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
1 IN EXCESS OF THE D DIMENSION AT
4 MAXIMUM MATERIAL CONDITION.
−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.

G MILLIMETERS INCHES
DIM MIN MAX MIN MAX
C N X 45 _ A 4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
SEATING
PLANE C 1.35 1.75 0.053 0.069
−Z− D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
0.10 (0.004) H 0.10 0.25 0.004 0.010
H M J J 0.19 0.25 0.007 0.010
D K 0.40 1.27 0.016 0.050
M 0 _ 8 _ 0 _ 8 _
N 0.25 0.50 0.010 0.020
0.25 (0.010) M Z Y S X S
S 5.80 6.20 0.228 0.244

SOLDERING FOOTPRINT*

1.52
0.060

7.0 4.0
0.275 0.155

0.6 1.270
0.024 0.050

SCALE 6:1 ǒinches

mm Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent− Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product
or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in
SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must
be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products
are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or
for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products
for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against
all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended
or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action
Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

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www.onsemi.com NCP1654/D
23