1. A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
B
1 49Monday, May 04, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
B
1 49Monday, May 04, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
B
1 49Monday, May 04, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
AMD L310/L110 Processor with RS780MN/SB710/M92-S2/S3 LP
NAL00 Schematics Document
REV:0.2
Compal Confidential
2009-04-24
hexainf@hotmail.com
2. A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
B
2 49Monday, May 04, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
B
2 49Monday, May 04, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
B
2 49Monday, May 04, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Power On/Off CKT.
CRT Conn.
LPC BUS
page 36
uFCBGA-528
page 23
Int.KB
page 34
USB conn
X 2A link Express2
DC/DC Interface CKT.
AMD S1G1 Processor
3.3V 48MHz
Hyper Transport Link
16 x 16
page 33
Fan Control
Power Circuit
uPGA-638 Package
page 35
page 38
ATI RS780MN
BIOS
page 4,5,6,7
page 34
HD Audio
page 4
page 10,11,12,13
ATI SB710
page 24,25,26,27,28
ENE KB926
LVDS Conn.
BT Conn
3.3V 24.576MHz/48Mhz
RTC CKT.
page 24
page 21
page 37
page 39,40,41,42,43,44,4546,47
page 29
SATA HDD
Conn.
port 0
CameraPort 1
Port 6USB
CDROM
Conn.page 29
page 22
PCI-Express 1x
port 1
Port 3 Port 12 Port 5
page 32
page 21
page 32
MINI Card 1
WLANpage 31
Port 0
Dual Channel BANK 0, 1, 2, 3
200pin DDRII-SO-DIMM X2
1.8V DDRII 667/800
Memory BUS(DDRII)
page 8,9
Clock Generator
SLG8SP626VTR
page 6 page 20
Thermal Sensor
ADM1032
ATI M92-S2 LP
VRAM 512MB
64M16 x 4
PCI-Express 8x
DDR3
page 18
Page 14,15,16,17,19
uFCBGA-528
uFCBGA-631
HDMI Conn.
HDA Codec
ALC269X-GR
Phone Jack x2
Digital MIC
page 37
page 33
LID SW/Cap sensor Board
Gen1
5 in 1 socket
page 30
page 30
Card Reader
RTS5159
Port 4
page 31
Port 8
Mini Card 1
(WLAN)
Mini Card 2
(WWAN)
page 31
page 31
To IO Board
USB conn X 2
Port 0
Port 2
S-ATA
MINI Card 2
WWANpage 31
Port 2
page 31
Port 1
Realtek RTL8111CA
To IO board
LAN(GbE)
IO Board
page 31
PWR Board
page 35
TP Board
page 34
page 35
LED
Model Name : NAL00
Compal Confidential
3. A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
B
3 49Monday, May 04, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
B
3 49Monday, May 04, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
B
3 49Monday, May 04, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
STATE
SIGNAL
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
ON
ON
ON
ON
ON
ON
ON ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
LOW
LOW LOW LOW LOW
LOWLOWLOW
LOW
LOW
LOW
HIGH HIGH HIGH HIGH
HIGHHIGHHIGH
HIGH
HIGH
HIGH
Board ID / SKU ID Table for AD channel
Vcc 3.3V +/- 5%
100K +/- 5%Ra/Rc/Re
Board ID Rb / Rd / Rf V min
0
1
2
3
0
8.2K +/- 5%
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
0.503 V
0.819 V
0.538 V
0.875 V
AD_BID V typAD_BID VAD_BID max
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
3.300 V
0 V 0 V
4
5
6
7 NC
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
2.200 V
3.300 V
2.341 V
1.185 V 1.264 V
Board ID
0
1
2
3
4
5
6
7
PCB Revision
0.1
BOARD ID Table BTO Option Table
BTO Item BOM Structure
Discrete
UMA UMA@
VGA@
0.2
0.3
1.0
1101 001Xb
OFF OFF
+0.9V 0.9V switched power rail for DDR terminator
+RTCVCC RTC power
+1.5VS
+1.8VS 1.8V switched power rail
+2.5VS
+5VS
+3VS
+5VALW
+1.8V
2.5V for CPU_VDDA
+3VALW
1.8V power rail for CPU VDDIO and DDR
3.3V always on power rail
5V always on power rail
3.3V switched power rail
5V switched power rail
+VSB VSB always on power rail ON ON*
ONON
ON
ON
EC SM Bus1 address
Device
SB700
SM Bus 1 address
ON
OFF
OFF
DDR DIMM1 1001 000Xb
DDR DIMM2 1001 010Xb
1.5V power rail for PCIE Card
+CPU_CORE
SB710
SM Bus 0 address
Device
Clock Generator
(SILEGO SLG8SP626)
Address
Address Address
Voltage Rails
VIN
B+
+1.1VS
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU (0.7-1.2V)
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts
ON
+VGA_CORE OFFOFFON
1.1V switched power rail for NB VDDC & VGA
ON
ADI ADM1032 (CPU)
+1.2V_HT 1.2V switched power rail ON OFF OFF
ON ON*
ON OFF OFF
+3V_LAN 3.3V power rail for LAN ON ON ON
S1 S3 S5
ON OFF
ON
N/A N/A N/A
N/AN/AN/A
Power Plane Description
EC SM Bus2 address
Device
Smart Battery
OFF
OFF
ON
OFF
OFF
OFF
ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
OFFON
ON
ON
ON
OFF
ON*
OFF
OFF
ON
New card
Device Address
ON
1001 100X b0001 011X b
0.90-0.95V switched power rail
HEX
98H16H
HEX
D2
HEX
90
94
Mini card
PX_GPIO0
X
LVDS / CRTPowerXpress mode
PX_GPIO2
DISPLAY OUTPUT
PX_GPIO1
IGP only mode
RS780MNSB700 SB700
dGPU_ResetFunction Description dGPU_PWR_Enable PX Mode Switch
XX
H : EnableH : Enable L : iGPU(DC) / H : dGPU(AC)
PX_GPIO1
X
PowerXpress mode
PX_+3VSPX_GPIO2
IGP only mode
KB926
Enable +1.1VS_PXFunction Description PX MODE SWITCH Enable +3VS_DELAY
XX
H : Enable Reserved H : Enable
X
PX_+1.8VS
Enable +1.8VS_PX
PX_+VGA_CORE
X
Enable +VGA_CORE
H : Enable
PX_GPIO1_SB
PowerXpress mode
PX_GPIO2_NB
IGP only mode
KB926
Trigger from SB to Enable (PX_GPIO1/PX_+3VS/PX_+1.8VS/PX_+VGA_CORE)Function Description
X
X
H : Enable
Reserved
Trigger from SB
H : Enable
9CHSB-Temp Sensor
+NB_CORE 1.0V switched power rail ON OFFOFF
UMA_HDMI UMA_H@
JM51
HM52
JM@
HM@
Side port SP@
hexainf@hotmail.com
4. 5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_CADIN14
H_CADIN15
H_CADIP12
H_CADIN13
H_CADIP13
H_CADIP14
H_CADIN12
H_CADIP11
H_CADIN10
H_CADIN11
H_CADIP10
H_CADIN9
H_CADIN7
H_CADIN8
H_CADIN6
H_CADIP7
H_CADIP9
H_CADIP8
H_CADIN5
H_CADIP5
H_CADIN4
H_CADIP4
H_CADIP6
H_CADIN2
H_CADIN3
H_CADIP1
H_CADIP3
H_CADIN1
H_CADIP15
H_CADIN0
H_CADIP0
H_CADIP2
H_CADON9
H_CADON1
H_CADON10
H_CADON3
H_CADOP15
H_CADOP12
H_CADOP14
H_CADOP11
H_CADOP13
H_CADOP7
H_CADOP10
H_CADOP9
H_CADOP8
H_CADOP1
H_CADOP3
H_CADOP2
H_CADOP0
H_CADOP6
H_CADOP5
H_CADOP4
H_CADON11
H_CADON13
H_CADON12
H_CADON15
H_CADON14
H_CADON8
H_CADON6
H_CADON7
H_CADON4
H_CADON5
H_CADON2
H_CADON0
H_CTLIP0
H_CTLON0H_CTLIN0
H_CTLOP0
H_CADIN[0..15]
H_CADOP[0..15]
H_CADON[0..15]
H_CADIP[0..15]
+VCC_FAN1
+VCC_FAN1
H_CTLON1_R
H_CTLOP1_R
H_CTLIN1_R
H_CTLIP1_R
H_CTLIN1_R
H_CTLIP1_R
H_CADON[0..15] <10>H_CADIN[0..15]<10>
H_CADOP[0..15] <10>
H_CLKIN1<10>
H_CLKIN0<10>
H_CLKIP0<10>
H_CTLIN0<10>
H_CLKIP1<10>
H_CTLIP0<10> H_CTLOP0 <10>
H_CLKOP0 <10>
H_CADIP[0..15]<10>
H_CLKOP1 <10>
H_CLKON1 <10>
H_CLKON0 <10>
H_CTLON0 <10>
EN_DFAN1<33>
FAN_SPEED1<33>
H_CTLIN1<10>
H_CTLIP1<10> H_CTLOP1 <10>
H_CTLON1 <10>
+1.2V_HT
+1.2V_HT
+5VS
+3VS
+5VS
+1.2V_HT
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
4 49Monday, May 04, 2009
2007/5/18 2009/06/11
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
4 49Monday, May 04, 2009
2007/5/18 2009/06/11
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
4 49Monday, May 04, 2009
2007/5/18 2009/06/11
Compal Electronics, Inc.
250 mil
VLDT=500mA
Athlon 64 S1
Processor Socket
Near CPU Socket
VLDT CAP.
FAN1 Conn
40mil
AMD : 49.9 1%
ATI : 51 1%
R226 0_0402_5%R226 0_0402_5%
1 2
R250 0_0402_5%R250 0_0402_5%
1 2
C914
180P_0402_50V8J
C914
180P_0402_50V8J
1
2
C108 10U_0805_10V4ZC108 10U_0805_10V4Z
1 2
U10
APL5607KI-TRG_SO8
U10
APL5607KI-TRG_SO8
EN1
VIN2
VOUT3
VSET4
GND 8
GND 7
GND 6
GND 5
C910
4.7U_0805_10V4Z
<BOM Structure>
C910
4.7U_0805_10V4Z
<BOM Structure>
1
2
R225 0_0402_5%R225 0_0402_5%
1 2
C904 4.7U_0805_10V4ZC904 4.7U_0805_10V4Z
1 2
D12
BAS16_SOT23-3@
D12
BAS16_SOT23-3@
1 2
C913
0.22U_0603_16V4Z
C913
0.22U_0603_16V4Z
1
2
R298
10K_0402_5%
R298
10K_0402_5%
12
JP13
ACES_85205-03001
CONN@
JP13
ACES_85205-03001
CONN@
1
2
3
R62 300_0402_5%R62 300_0402_5%
12
R814 51_0402_1%@R814 51_0402_1%@12
C119
1000P_0402_50V7K
C119
1000P_0402_50V7K
1 2
R227 0_0402_5%R227 0_0402_5%
1 2
D11
1SS355_SOD323-2
@
D11
1SS355_SOD323-2
@
12
C912
0.22U_0603_16V4Z
C912
0.22U_0603_16V4Z
1
2
C911
4.7U_0805_10V4Z
<BOM Structure>
C911
4.7U_0805_10V4Z
<BOM Structure>
1
2
C105
0.1U_0402_16V4Z
C105
0.1U_0402_16V4Z
1
2
C915
180P_0402_50V8J
C915
180P_0402_50V8J
1
2
HTTInterface
JCPU1A
FOX_PZ63823-284S-41F
CONN@
HTTInterface
JCPU1A
FOX_PZ63823-284S-41F
CONN@
VLDT_A3D4
VLDT_A2D3
VLDT_A1D2
VLDT_A0D1
VLDT_B3 AE5
VLDT_B2 AE4
VLDT_B1 AE3
VLDT_B0 AE2
L0_CADIN_H15N5
L0_CADIN_L15P5
L0_CADIN_H14M3
L0_CADIN_L14M4
L0_CADIN_H13L5
L0_CADIN_L13M5
L0_CADIN_H12K3
L0_CADIN_L12K4
L0_CADIN_H11H3
L0_CADIN_L11H4
L0_CADIN_H10G5
L0_CADIN_L10H5
L0_CADIN_H9F3
L0_CADIN_L9F4
L0_CADIN_H8E5
L0_CADIN_L8F5
L0_CADIN_H7N3
L0_CADIN_L7N2
L0_CADIN_H6L1
L0_CADIN_L6M1
L0_CADIN_H5L3
L0_CADIN_L5L2
L0_CADIN_H4J1
L0_CADIN_L4K1
L0_CADIN_H3G1
L0_CADIN_L3H1
L0_CADIN_H2G3
L0_CADIN_L2G2
L0_CADIN_H1E1
L0_CADIN_L1F1
L0_CADIN_H0E3
L0_CADIN_L0E2
L0_CADOUT_H15 T4
L0_CADOUT_L15 T3
L0_CADOUT_H14 V5
L0_CADOUT_L14 U5
L0_CADOUT_H13 V4
L0_CADOUT_L13 V3
L0_CADOUT_H12 Y5
L0_CADOUT_L12 W5
L0_CADOUT_H11 AB5
L0_CADOUT_L11 AA5
L0_CADOUT_H10 AB4
L0_CADOUT_L10 AB3
L0_CADOUT_H9 AD5
L0_CADOUT_L9 AC5
L0_CADOUT_H8 AD4
L0_CADOUT_L8 AD3
L0_CADOUT_H7 T1
L0_CADOUT_L7 R1
L0_CADOUT_H6 U2
L0_CADOUT_L6 U3
L0_CADOUT_H5 V1
L0_CADOUT_L5 U1
L0_CADOUT_H4 W2
L0_CADOUT_L4 W3
L0_CADOUT_H3 AA2
L0_CADOUT_L3 AA3
L0_CADOUT_H2 AB1
L0_CADOUT_L2 AA1
L0_CADOUT_H1 AC2
L0_CADOUT_L1 AC3
L0_CADOUT_H0 AD1
L0_CADOUT_L0 AC1
L0_CLKIN_H1J5
L0_CLKIN_L1K5
L0_CLKIN_H0J3
L0_CLKIN_L0J2
L0_CTLIN_H0N1
L0_CTLIN_L0P1
L0_CTLOUT_H0 R2
L0_CTLOUT_L0 R3
L0_CLKOUT_H0 Y1
L0_CLKOUT_L0 W1
L0_CLKOUT_H1 Y4
L0_CLKOUT_L1 Y3
L0_CTLIN_H1P3
L0_CTLIN_L1P4
L0_CTLOUT_H1 T5
L0_CTLOUT_L1 R5
R829 51_0402_1%@R829 51_0402_1%@12
C121
10U_0805_10V4Z
C121
10U_0805_10V4Z
1 2
C670
1000P_0402_50V7K
C670
1000P_0402_50V7K
1
2
5. A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
VTT_SENSE
M_ZP
DDR_A_MA0
DDR_A_MA3
DDR_A_MA1
DDR_A_MA2
DDR_A_MA4
DDR_A_MA5
DDR_B_MA1
DDR_B_MA5
DDR_A_CLK#1
DDR_B_RAS#
M_ZN
DDR_B_D35
DDR_B_D47
DDR_B_D41
DDR_B_D44
DDR_B_D54
DDR_B_D13
DDR_B_D28
DDR_B_D17
DDR_B_D58
DDR_B_D26
DDR_B_D37
DDR_B_D60
DDR_B_D55
DDR_B_D34
DDR_B_D49
DDR_B_D56
DDR_B_D4
DDR_B_D12
DDR_B_D53
DDR_B_D46
DDR_B_D19
DDR_B_D22
DDR_B_D25
DDR_B_D16
DDR_B_D0
DDR_B_D31
DDR_B_D43
DDR_B_D11
DDR_B_D33
DDR_B_D10
DDR_B_D23
DDR_B_D36
DDR_B_D18
DDR_B_D8
DDR_B_D7
DDR_B_D52
DDR_B_D15
DDR_B_D63
DDR_B_D24
DDR_B_D62
DDR_B_D21
DDR_B_D27
DDR_B_D1
DDR_B_D61
DDR_B_D5
DDR_B_D30
DDR_B_D32
DDR_B_D42
DDR_B_D9
DDR_B_D39
DDR_B_D48
DDR_B_D3
DDR_B_D51
DDR_B_D14
DDR_B_D20
DDR_B_D45
DDR_B_D2
DDR_B_D29
DDR_B_D59
DDR_B_DM1
DDR_B_DM3
DDR_B_DM5
DDR_B_DM7
DDR_B_DM2
DDR_B_DM4
DDR_B_DM6
DDR_B_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
DDR_A_DM0
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_D4
DDR_A_D23
DDR_A_D60
DDR_A_D34
DDR_A_D50
DDR_A_D3
DDR_A_D7
DDR_A_D27
DDR_A_D44
DDR_A_D35
DDR_A_D40
DDR_A_D43
DDR_A_D29
DDR_A_D59
DDR_A_D48
DDR_A_D2
DDR_A_D63
DDR_A_D10
DDR_A_D30
DDR_A_D16
DDR_A_D20
DDR_A_D39
DDR_A_D41
DDR_A_D12
DDR_A_D24
DDR_A_D17
DDR_A_D54
DDR_A_D58
DDR_A_D56
DDR_A_D32
DDR_A_D57
DDR_A_D55
DDR_A_D9
DDR_A_D37
DDR_A_D42
DDR_A_D6
DDR_A_D51
DDR_A_D13
DDR_A_D38
DDR_A_D0
DDR_A_D19
DDR_A_D21
DDR_A_D1
DDR_A_D15
DDR_A_D62
DDR_A_D61
DDR_A_D5
DDR_A_D31
DDR_A_D46
DDR_A_D53
DDR_A_D36
DDR_A_D52
DDR_A_D8
DDR_A_D25
DDR_A_D11
DDR_A_D14
DDR_A_D22
DDR_A_D49
DDR_A_D45
DDR_A_D47
DDR_A_D33
DDR_A_D28
DDR_A_D26
DDR_B_D57
DDR_A_D18
DDR_B_D38
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_D40
DDR_B_D6
DDR_B_D50
DDR_B_CLK#2
DDR_A_CLK#2
DDR_B_MA8
DDR_B_ODT1
DDR_B_CLK2
DDR_B_MA14
DDR_B_MA3
DDR_B_CLK1
DDR_A_CLK2
DDR_B_MA9
DDR_B_MA4
DDR_B_MA15
DDR_A_ODT0
DDR_B_MA6
DDR_B_ODT0
DDR_B_MA0
DDR_B_MA12
DDR_A_ODT1
DDR_B_MA10
DDR_A_CLK1
DDR_B_MA7
DDR_B_MA2
DDR_B_MA13
DDR_B_MA11
DDR_B_CLK#1
DDR_CS2_DIMMA#
DDR_CS1_DIMMB#
DDR_A_MA9
DDR_CS0_DIMMA#
DDR_A_MA14
DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
DDR_A_MA8
DDR_CS3_DIMMA#
DDR_A_MA13
DDR_CKE0_DIMMB
DDR_CKE1_DIMMA
DDR_A_MA12
DDR_A_MA7
DDR_CKE1_DIMMB
DDR_CKE0_DIMMA
DDR_A_MA10
DDR_A_MA11
DDR_A_MA6
DDR_CS0_DIMMB#
DDR_CS1_DIMMA#
DDR_A_BS#0
DDR_A_WE#
DDR_A_CAS#
DDR_A_RAS#
DDR_A_BS#1
DDR_A_BS#2
DDR_A_MA15
DDR_B_BS#2
DDR_B_BS#1
DDR_B_BS#0
DDR_B_CAS#
DDR_B_WE#
DDR_A_CLK1
DDR_A_CLK#1
DDR_A_CLK2
DDR_A_CLK#2
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK1
DDR_B_CLK#1
DDR_A_CLK2 <8>
DDR_A_CLK#2 <8>
DDR_A_CLK1 <8>
DDR_A_CLK#1 <8>
DDR_B_CLK2 <9>
DDR_B_CLK#2 <9>
DDR_B_CLK1 <9>
DDR_B_CLK#1 <9>
DDR_B_ODT1 <9>
DDR_B_ODT0 <9>
DDR_A_ODT1 <8>
DDR_A_ODT0 <8>
DDR_B_MA[15..0] <9>
DDR_B_BS#2 <9>
DDR_B_BS#1 <9>
DDR_B_BS#0 <9>
DDR_B_RAS# <9>
DDR_B_CAS# <9>
DDR_B_WE# <9>
DDR_A_BS#2<8>
DDR_A_BS#1<8>
DDR_A_BS#0<8>
DDR_A_RAS#<8>
DDR_A_CAS#<8>
DDR_A_WE#<8>
DDR_CS3_DIMMA#<8>
DDR_CS2_DIMMA#<8>
DDR_CS1_DIMMA#<8>
DDR_CS0_DIMMA#<8>
DDR_CS3_DIMMB#<9>
DDR_CS2_DIMMB#<9>
DDR_CS1_DIMMB#<9>
DDR_CS0_DIMMB#<9>
DDR_CKE1_DIMMB<9>
DDR_CKE0_DIMMB<9>
DDR_CKE1_DIMMA<8>
DDR_CKE0_DIMMA<8>
DDR_A_MA[15..0]<8>
DDR_B_D[63..0]<9>
DDR_B_DQS7<9>
DDR_B_DQS#7<9>
DDR_B_DQS6<9>
DDR_B_DQS5<9>
DDR_B_DQS4<9>
DDR_B_DQS3<9>
DDR_B_DQS2<9>
DDR_B_DQS1<9>
DDR_B_DQS0<9>
DDR_B_DQS#6<9>
DDR_B_DQS#5<9>
DDR_B_DQS#4<9>
DDR_B_DQS#3<9>
DDR_B_DQS#2<9>
DDR_B_DQS#1<9>
DDR_B_DQS#0<9>
DDR_B_DM[7..0]<9> DDR_A_DM[7..0] <8>
DDR_A_DQS7 <8>
DDR_A_DQS6 <8>
DDR_A_DQS5 <8>
DDR_A_DQS4 <8>
DDR_A_DQS3 <8>
DDR_A_DQS2 <8>
DDR_A_DQS1 <8>
DDR_A_DQS0 <8>
DDR_A_DQS#7 <8>
DDR_A_DQS#6 <8>
DDR_A_DQS#5 <8>
DDR_A_DQS#4 <8>
DDR_A_DQS#3 <8>
DDR_A_DQS#2 <8>
DDR_A_DQS#1 <8>
DDR_A_DQS#0 <8>
DDR_A_D[63..0] <8>
+CPU_M_VREF
+0.9V
+CPU_M_VREF
+1.8V
+1.8V
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
5 49Monday, May 04, 2009
2007/5/18 2009/06/11 Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
5 49Monday, May 04, 2009
2007/5/18 2009/06/11 Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
5 49Monday, May 04, 2009
2007/5/18 2009/06/11
Compal Electronics, Inc.
Athlon 64 S1
Processor
Socket
Athlon 64 S1
Processor Socket
Processor DDR2 Memory Interface
PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH
TP1TP1
C920
1.5P_0402_50V8C
C920
1.5P_0402_50V8C
1
2
C917
1000P_0402_50V7K
C917
1000P_0402_50V7K
1
2
C918
1.5P_0402_50V8C
C918
1.5P_0402_50V8C
1
2
DDRIICmd/Ctrl//Clk
JCPU1B
CONN@ FOX_PZ63823-284S-41F
DDRIICmd/Ctrl//Clk
JCPU1B
CONN@ FOX_PZ63823-284S-41F
VTT1 D10
VTT2 C10
VTT3 B10
VTT4 AD10
VTT6 AC10
VTT7 AB10
VTT8 AA10
VTT9 A10
M_VREFW17
VTT_SENSEY10
M_ZNAE10
M_ZPAF10
MA0_CS_L3V19
MA0_CS_L2J22
MA0_CS_L1V22
MA0_CS_L0T19
MB_CKE1H26
MB_CKE0J23
MA_CKE1J20
MA_CKE0J21
MA_ADD13V24
MA_ADD12K24
MA_ADD11L20
MA_ADD10R19
MA_ADD9L19
MA_ADD8L22
MA_ADD7L21
MA_ADD6M19
MA_ADD5M20
MA_ADD4M24
MA_ADD3M22
MA_ADD2N22
MA_ADD1N21
MA_ADD0R21
MA_BANK1R20
MA_BANK0T22
MA_RAS_LT20
MA_CAS_LU20
MA_WE_LU21
MB_RAS_L U24
MB_CAS_L V26
MB_WE_L U22
MB_BANK1 T26
MB_BANK0 U26
MB_ADD13 W25
MB_ADD12 L23
MB_ADD11 L25
MB_ADD10 U25
MB_ADD9 L24
MB_ADD8 M26
MB_ADD7 L26
MB_ADD6 N23
MB_ADD5 N24
MB_ADD4 N25
MB_ADD3 N26
MB_ADD2 P24
MB_ADD1 P26
MB_ADD0 T24
MA0_CLK_H2 Y16
MA0_CLK_L2 AA16
MA0_CLK_H1 E16
MA0_CLK_L1 F16
MB0_CLK_H2 AF18
MB0_CLK_L2 AF17
MB0_CLK_H1 A17
MB0_CLK_L1 A18
MB0_CS_L3Y26
MB0_CS_L2J24
MB0_CS_L1W24
MB0_CS_L0U23
MA0_ODT0 U19
MA0_ODT1 V20
MA_BANK2K22
MA_ADD15K19
MA_ADD14K20
MB0_ODT0 W26
MB0_ODT1 W23
MB_BANK2 K26
MB_ADD14 J26
MB_ADD15 J25
VTT5 W10
DDRIIData
JCPU1C
CONN@ FOX_PZ63823-284S-41F
DDRIIData
JCPU1C
CONN@ FOX_PZ63823-284S-41F
MB_DM7AD12
MB_DM6AC16
MB_DM5AE22
MB_DM4AB26
MB_DM3E25
MB_DM2A22
MB_DM1B16
MB_DM0A12
MA_DM7 Y13
MA_DM6 AB16
MA_DM5 Y19
MA_DM4 AC24
MA_DM3 F24
MA_DM2 E19
MA_DM1 C15
MA_DM0 E12
MA_DATA0 G12
MA_DATA1 F12
MA_DATA2 H14
MA_DATA3 G14
MA_DATA4 H11
MA_DATA5 H12
MA_DATA6 C13
MA_DATA7 E13
MA_DATA8 H15
MA_DATA9 E15
MA_DATA10 E17
MA_DATA11 H17
MA_DATA12 E14
MA_DATA13 F14
MA_DATA14 C17
MA_DATA15 G17
MA_DATA16 G18
MA_DATA17 C19
MA_DATA18 D22
MA_DATA19 E20
MA_DATA20 E18
MA_DATA21 F18
MA_DATA22 B22
MA_DATA23 C23
MA_DATA24 F20
MA_DATA25 F22
MA_DATA26 H24
MA_DATA27 J19
MA_DATA28 E21
MA_DATA29 E22
MA_DATA30 H20
MA_DATA31 H22
MA_DATA32 Y24
MA_DATA33 AB24
MA_DATA34 AB22
MA_DATA35 AA21
MA_DATA36 W22
MA_DATA37 W21
MA_DATA38 Y22
MA_DATA39 AA22
MA_DATA40 Y20
MA_DATA41 AA20
MA_DATA42 AA18
MA_DATA43 AB18
MA_DATA44 AB21
MA_DATA45 AD21
MA_DATA46 AD19
MA_DATA47 Y18
MA_DATA48 AD17
MA_DATA49 W16
MA_DATA50 W14
MA_DATA51 Y14
MA_DATA52 Y17
MA_DATA53 AB17
MA_DATA54 AB15
MA_DATA55 AD15
MA_DATA56 AB13
MA_DATA57 AD13
MA_DATA58 Y12
MA_DATA59 W11
MA_DATA60 AB14
MA_DATA61 AA14
MA_DATA62 AB12
MA_DATA63 AA12
MA_DQS_L0 H13
MA_DQS_L1 G15
MA_DQS_L2 C21
MA_DQS_L3 G21
MA_DQS_L4 AC23
MA_DQS_L5 AB20
MA_DQS_L6 W15
MA_DQS_L7 W13
MA_DQS_H0 G13
MA_DQS_H1 G16
MA_DQS_H2 C22
MA_DQS_H3 G22
MA_DQS_H4 AD23
MA_DQS_H5 AB19
MA_DQS_H6 Y15
MA_DQS_H7 W12
MB_DATA0C11
MB_DATA1A11
MB_DATA2A14
MB_DATA3B14
MB_DATA4G11
MB_DATA5E11
MB_DATA6D12
MB_DATA7A13
MB_DATA8A15
MB_DATA9A16
MB_DATA10A19
MB_DATA11A20
MB_DATA12C14
MB_DATA13D14
MB_DATA14C18
MB_DATA15D18
MB_DATA16D20
MB_DATA17A21
MB_DATA18D24
MB_DATA19C25
MB_DATA20B20
MB_DATA21C20
MB_DATA22B24
MB_DATA23C24
MB_DATA24E23
MB_DATA25E24
MB_DATA26G25
MB_DATA27G26
MB_DATA28C26
MB_DATA29D26
MB_DATA30G23
MB_DATA31G24
MB_DATA32AA24
MB_DATA33AA23
MB_DATA34AD24
MB_DATA35AE24
MB_DATA36AA26
MB_DATA37AA25
MB_DATA38AD26
MB_DATA39AE25
MB_DATA40AC22
MB_DATA41AD22
MB_DATA42AE20
MB_DATA43AF20
MB_DATA44AF24
MB_DATA45AF23
MB_DATA46AC20
MB_DATA47AD20
MB_DATA48AD18
MB_DATA49AE18
MB_DATA50AC14
MB_DATA51AD14
MB_DATA52AF19
MB_DATA53AC18
MB_DATA54AF16
MB_DATA55AF15
MB_DATA56AF13
MB_DATA57AC12
MB_DATA58AB11
MB_DATA59Y11
MB_DATA60AE14
MB_DATA61AF14
MB_DATA62AF11
MB_DATA63AD11
MB_DQS_L0B12
MB_DQS_L1C16
MB_DQS_L2A23
MB_DQS_L3E26
MB_DQS_L4AC26
MB_DQS_L5AF22
MB_DQS_L6AD16
MB_DQS_L7AE12
MB_DQS_H0C12
MB_DQS_H1D16
MB_DQS_H2A24
MB_DQS_H3F26
MB_DQS_H4AC25
MB_DQS_H5AF21
MB_DQS_H6AE16
MB_DQS_H7AF12
C921
1.5P_0402_50V8C
C921
1.5P_0402_50V8C
1
2
C919
1.5P_0402_50V8C
C919
1.5P_0402_50V8C
1
2
R803
39.2_0402_1%
R803
39.2_0402_1%
12
R800
1K_0402_1%
R800
1K_0402_1%
12
R801
1K_0402_1%
R801
1K_0402_1%
12
C916
0.1U_0402_16V4Z
C916
0.1U_0402_16V4Z
1
2
R802
39.2_0402_1%
R802
39.2_0402_1%
1 2
hexainf@hotmail.com
6. 5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CPU_HTREF0
CPU_HTREF1
CPU_TEST25_L_BYPASSCLK_L
CPU_DBRDY
CPU_TMS
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST19_PLLTEST0
CPU_TEST21_SCANEN
CPU_PRESENT#
CPU_CLKIN_SC_P
CPU_THERMTRIP#_R
CPU_SIC
LDT_STOP#
CPU_DBRDY
CPU_TDO
CPU_TMS
CPU_TCK
CPU_TDI
CPU_TRST#
CPU_DBREQ#
HDT_RST#
LDT_RST#
CPU_TEST29_L_FBCLKOUT_N
CPU_TEST29_H_FBCLKOUT_P
CPU_TDI
CPU_TRST#
CPU_TCK CPU_TDO
CPU_DBREQ#
CPU_TEST26_BURNIN#
CPU_CLKIN_SC_N
CPU_THERMDC
CPU_THERMDA
H_PWRGD
LDT_RST#
CPU_THERMDA
CPU_THERMDC
CPU_PROCHOT#_1.8
CPU_TEST18_PLLTEST1
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST18_PLLTEST1
CPU_TEST19_PLLTEST0
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST26_BURNIN#
CPU_PRESENT#
CPU_TEST21_SCANEN
CPU_VID1
CPU_THERMTRIP#_R H_THERMTRIP#
LDT_RST#
H_PWRGD
LDT_STOP#
SB_PWRGD <25,35>
CLK_CPU_BCLK#<20>
CLK_CPU_BCLK<20>
PSI_L <46>CPU_VSS_SENSE<46>
CPU_VCC_SENSE<46>
CPU_VID0 <46>
CPU_VID1 <46>
CPU_VID2 <46>
CPU_VID3 <46>
CPU_VID4 <46>
CPU_VID5 <46>
EC_SMB_CK2 <19,33>
EC_SMB_DA2 <19,33>
MAINPWON <42,45>
H_THERMTRIP# <25>
H_PROCHOT_R# <24>
H_PWRGD<24>
LDT_STOP#<11,24>
LDT_RST#<24>
+1.8V
+3VS
+1.2V_HT
+2.5VDDA
+2.5VS
+3VS
+1.8V
+1.8V
+1.8V
+1.8V
+3VALW
+3VALW
+1.8VS
+1.8VS
+1.8VS
+1.8V
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
6 49Monday, May 04, 2009
2007/5/18 2009/06/11
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
6 49Monday, May 04, 2009
2007/5/18 2009/06/11
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
6 49Monday, May 04, 2009
2007/5/18 2009/06/11
Compal Electronics, Inc.
HDT Connector
NOTE: HDT TERMINATION IS REQUIRED
FOR REV. Ax SILICON ONLY.
R61&R16 close to CPU within 1"
PLACE IT CLOSE TO CPU WITHIN 1"
ROUTE AS 80 Ohm DIFFERENTIAL PAIR
VDDA=300mA
SMBus Address: 1001110X (b)
F75383M_MSOP8
A:Need to re-Link "SGN00000200"
VID1: For compatibility
with future processors
AMD: suggest DBREQ need pull high
C923
4.7U_0805_10V4Z
C923
4.7U_0805_10V4Z
1
2
R817 300_0402_5%R817 300_0402_5%
12
R812 44.2_0402_1%R812 44.2_0402_1%1 2
TP7TP7
C719
0.01U_0402_25V4Z
@
C719
0.01U_0402_25V4Z
@
1
2
R806 1K_0402_5%R806 1K_0402_5%
1 2
R822
300_0402_5%
R822
300_0402_5%
12
U56
NC7SZ08P5X_NL_SC70-5
@U56
NC7SZ08P5X_NL_SC70-5
@
B 2
A 1
Y4
P5G3
L91
FCM2012CF-800T06_2P
L91
FCM2012CF-800T06_2P
1 2
TP10TP10
TP9TP9
E
B
C
Q69
MMBT3904_NL_SOT23-3
E
B
C
Q69
MMBT3904_NL_SOT23-3
2
3 1
TP2TP2
R824220_0402_5%@R824220_0402_5%@
12
R826220_0402_5%@R826220_0402_5%@
12
R339
300_0402_5%
R339
300_0402_5%
12
C928
0.1U_0402_16V4Z
C928
0.1U_0402_16V4Z
1 2
C929
2200P_0402_50V7K
C929
2200P_0402_50V7K
1
2
R823
10K_0402_5%
R823
10K_0402_5%
12
TP12TP12
TP8TP8
SAMTEC_ASP-68200-07
JP18
@SAMTEC_ASP-68200-07
JP18
@
2
4
6
8
10
12
14
16
18
20
22
2423
21
19
17
15
13
11
9
7
5
3
1
26
TP3TP3
C927 3900P_0402_50V7KC927 3900P_0402_50V7K
1 2
C720
0.01U_0402_25V4Z
@
C720
0.01U_0402_25V4Z
@
1
2
R827220_0402_5%@R827220_0402_5%@
12
R338
300_0402_5%
R338
300_0402_5%
12
R337
300_0402_5%
R337
300_0402_5%
12
R805 300_0402_5%R805 300_0402_5%
1 2
R821
1K_0402_5%@
R821
1K_0402_5%@
12
TP6TP6
TP5TP5
+ C391
150U_B2_6.3VM
+ C391
150U_B2_6.3VM
1
2
R372
0_0402_5%
R372
0_0402_5%
1 2
R813 510_0402_5%R813 510_0402_5%
12
R820
1K_0402_5%
R820
1K_0402_5%
12
R815 510_0402_5%R815 510_0402_5%
12
R825220_0402_5%@R825220_0402_5%@
12
TP4TP4
R811 44.2_0402_1%R811 44.2_0402_1%1 2
R807 300_0402_5%R807 300_0402_5%
1 2
R818 300_0402_5%R818 300_0402_5%
12
R819
80.6_0402_1%
R819
80.6_0402_1%
1 2
MISC
JCPU1D
CONN@
FOX_PZ63823-284S-41F
MISC
JCPU1D
CONN@
FOX_PZ63823-284S-41F
VDDA2F8
VDDA1F9
RESET_LB7
PWROKA7
LDTSTOP_LF10
HTREF1P6
HTREF0R6
VDDIO_FB_HW9
VDDIO_FB_LY9
CLKIN_HA9
CLKIN_LA8
DBRDYG10
TMSAA9
TCKAC9
TRST_LAD9
TDIAF9
TDO AE9
DBREQ_L E10
VID4 C6
VID3 A6
VID2 A4
VID1 C5
VID0 B5
THERMTRIP_L AF6
CPU_PRESENT_L AC6
SICAF4
SIDAF5
VDD_FB_HF6
VDD_FB_LE6
VID5 A5
PROCHOT_L AC7
PSI_L A3
TEST2AB6
TEST3Y6
THERMDAW8
THERMDCW7
TEST6AA6
TEST7C3
TEST8 C4
TEST10 K8
TEST26 AE6
TEST27 AF8
TEST28_L H8
TEST28_H J7
TEST20 AF7
TEST21 AB8
TEST22 AE8
TEST23 AD7
TEST24 AE7
TEST12AC8
TEST14C7
TEST15F7
TEST16E7
TEST17D7
TEST9C2
TEST13AA7
TEST18H10
TEST19G9
TEST25_LE8
TEST25_HE9 TEST29_H C9
TEST29_L C8
RSVD0P20
RSVD1P19
RSVD2N20
RSVD3N19
RSVD4R26
RSVD5R25
RSVD6P22
RSVD7R22
RSVD8 H16
RSVD9 B18
RSVD10 B3
RSVD11 C1
RSVD12 H6
RSVD13 G6
RSVD14 D5
RSVD15 R24
RSVD16 W18
RSVD17 R23
RSVD18 AA8
RSVD19 H18
RSVD20 H19
R809 300_0402_5%R809 300_0402_5%
1 2
TP11TP11
C924
3300P_0402_50V7K
C924
3300P_0402_50V7K
1
2
E
B
C
Q70
MMBT3904_NL_SOT23-3
@
E
B
C
Q70
MMBT3904_NL_SOT23-3
@
2
3 1
C721
0.01U_0402_25V4Z
@
C721
0.01U_0402_25V4Z
@
1
2
R828220_0402_5%R828220_0402_5%
12
R808 300_0402_5%R808 300_0402_5%
12
U55
ADM1032ARMZ-2REEL_MSOP8
U55
ADM1032ARMZ-2REEL_MSOP8
VDD1
ALERT# 6
THERM#4 GND 5
D+2
D-3
SCLK 8
SDATA 7
C925
0.22U_0603_16V4Z
C925
0.22U_0603_16V4Z
1
2
C926
3900P_0402_50V7K
C926
3900P_0402_50V7K1 2
R830
300_0402_5%
R830
300_0402_5%
12
R816
169_0402_1%
R816
169_0402_1%
12
7. 5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+CPU_CORE +CPU_CORE
+1.8V
+0.9V
+CPU_CORE
+CPU_CORE
+CPU_CORE
+1.8V
+CPU_CORE +CPU_CORE
+1.8V
+1.8V
+1.8V
+1.8V +1.8V
+0.9V
+0.9V
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
7 49Monday, May 04, 2009
2007/5/18 2009/06/11
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
7 49Monday, May 04, 2009
2007/5/18 2009/06/11
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
7 49Monday, May 04, 2009
2007/5/18 2009/06/11
Compal Electronics, Inc.
Between CPU Socket and DIMM
180PF Qt'y follow the distance between
CPU socket and DIMM0. <2.5inch>
Under CPU Socket
Near CPU Socket
VTT decoupling.
VDD(+CPU_CORE) decoupling.
VDDIO decoupling.
C: Change to NBO CAP
Under CPU Socket
Near CPU Socket Right side.
Near CPU Socket Left side.
Near Power Supply
Athlon 64 S1
Processor Socket
Athlon 64 S1
Processor Socket
C961
0.22U_0603_16V4Z
C961
0.22U_0603_16V4Z
1
2
C980
4.7U_0805_10V4Z
C980
4.7U_0805_10V4Z
1
2
+ C935
330U_D2E_2.5VM_R9M
+ C935
330U_D2E_2.5VM_R9M
1
2
C955
0.22U_0603_16V4Z
C955
0.22U_0603_16V4Z
1
2
C957
0.22U_0603_16V4Z
C957
0.22U_0603_16V4Z
1
2
C978
180P_0402_50V8J
C978
180P_0402_50V8J
1
2
C965
180P_0402_50V8J
C965
180P_0402_50V8J
1
2
C946
0.22U_0603_16V4Z
C946
0.22U_0603_16V4Z
1
2
C941
22U_0805_6.3V6M
C941
22U_0805_6.3V6M
1
2
C982
4.7U_0805_10V4Z
C982
4.7U_0805_10V4Z
1
2
C975
0.22U_0603_16V4Z
C975
0.22U_0603_16V4Z
1
2
C936
22U_0805_6.3V6M
C936
22U_0805_6.3V6M
1
2
C967
0.01U_0402_25V7K
C967
0.01U_0402_25V7K
1
2
C939
22U_0805_6.3V6M
C939
22U_0805_6.3V6M
1
2
C948
180P_0402_50V8J
C948
180P_0402_50V8J
1
2
C945
0.22U_0603_16V4Z
C945
0.22U_0603_16V4Z
1
2
C947
0.01U_0402_25V7K
C947
0.01U_0402_25V7K
1
2
C944
22U_0805_6.3V6M
C944
22U_0805_6.3V6M
1
2
C950
22U_0805_6.3V6M
C950
22U_0805_6.3V6M
1
2
C940
22U_0805_6.3V6M
C940
22U_0805_6.3V6M
1
2
C966
0.01U_0402_25V7K
C966
0.01U_0402_25V7K
1
2
+ C934
330U_D2E_2.5VM_R9M
+ C934
330U_D2E_2.5VM_R9M
1
2
C971
180P_0402_50V8J
C971
180P_0402_50V8J
1
2
C949
22U_0805_6.3V6M
C949
22U_0805_6.3V6M
1
2
C937
22U_0805_6.3V6M
C937
22U_0805_6.3V6M
1
2
C960
0.22U_0603_16V4Z
C960
0.22U_0603_16V4Z
1
2
C952
0.22U_0603_16V4Z
C952
0.22U_0603_16V4Z
1
2
C968
180P_0402_50V8J
C968
180P_0402_50V8J
1
2
C964
180P_0402_50V8J
C964
180P_0402_50V8J
1
2
C969
180P_0402_50V8J
C969
180P_0402_50V8J
1
2
C979
180P_0402_50V8J
C979
180P_0402_50V8J
1
2
C981
4.7U_0805_10V4Z
C981
4.7U_0805_10V4Z
1
2
+ C931
330U_D2E_2.5VM_R9M
+ C931
330U_D2E_2.5VM_R9M
1
2
C951
0.22U_0603_16V4Z
C951
0.22U_0603_16V4Z
1
2
C942
22U_0805_6.3V6M
C942
22U_0805_6.3V6M
1
2
C963
1000P_0402_50V7K
C963
1000P_0402_50V7K
1
2
+ C930
330U_D2E_2.5VM_R9M
+ C930
330U_D2E_2.5VM_R9M
1
2
C962
1000P_0402_50V7K
C962
1000P_0402_50V7K
1
2
C943
22U_0805_6.3V6M
C943
22U_0805_6.3V6M
1
2
C938
22U_0805_6.3V6M
C938
22U_0805_6.3V6M
1
2
Power
JCPU1E
CONN@
FOX_PZ63823-284S-41F
Power
JCPU1E
CONN@
FOX_PZ63823-284S-41F
VDD1AC4
VDD2AD2
VDD3G4
VDD4H2
VDD5J9
VDD6J11
VDD7J13
VDD8K6
VDD9K10
VDD10K12
VDD11K14
VDD12L4
VDD13L7
VDD14L9
VDD15L11
VDD16L13
VDD17M2
VDD18M6
VDD19M8
VDD20M10
VDD21N7
VDD22N9
VDD23N11
VDD24P8
VDD25P10
VDD26R4
VDD27R7
VDD28R9
VDD29R11
VDD30T2
VDD31T6
VDD32T8
VDD33T10
VDD34T12
VDD35T14
VDD36U7
VDD37U9
VDD38U11
VDD39U13
VDD40V6
VDD41V8
VDD42V10
VDD43 V12
VDD44 V14
VDD45 W4
VDD46 Y2
VDD47 J15
VDD48 K16
VDD49 L15
VDD50 M16
VDD51 P16
VDD52 T16
VDD53 U15
VDD54 V16
VDDIO1 H25
VDDIO2 J17
VDDIO3 K18
VDDIO4 K21
VDDIO5 K23
VDDIO6 K25
VDDIO7 L17
VDDIO8 M18
VDDIO9 M21
VDDIO10 M23
VDDIO11 M25
VDDIO12 N17
VDDIO13 P18
VDDIO14 P21
VDDIO15 P23
VDDIO16 P25
VDDIO17 R17
VDDIO18 T18
VDDIO19 T21
VDDIO20 T23
VDDIO21 T25
VDDIO22 U17
VDDIO23 V18
VDDIO24 V21
VDDIO25 V23
VDDIO26 V25
VDDIO27 Y25
C974
0.22U_0603_16V4Z
C974
0.22U_0603_16V4Z
1
2
C958
4.7U_0805_10V4Z
C958
4.7U_0805_10V4Z
1
2
C976
1000P_0402_50V7K
C976
1000P_0402_50V7K
1
2
C959
4.7U_0805_10V4Z
C959
4.7U_0805_10V4Z
1
2
C956
0.22U_0603_16V4Z
C956
0.22U_0603_16V4Z
1
2
C954
0.22U_0603_16V4Z
C954
0.22U_0603_16V4Z
1
2
C972
4.7U_0805_10V4Z
C972
4.7U_0805_10V4Z
1
2
+ C536
220U_B2_2.5VM_R35
+ C536
220U_B2_2.5VM_R35
1
2
C970
180P_0402_50V8J
C970
180P_0402_50V8J
1
2
+ C392
150U_B2_6.3VM
+ C392
150U_B2_6.3VM
1
2
C977
1000P_0402_50V7K
C977
1000P_0402_50V7K
1
2
C983
4.7U_0805_10V4Z
C983
4.7U_0805_10V4Z
1
2
Ground
JCPU1F
CONN@
FOX_PZ63823-284S-41F
Ground
JCPU1F
CONN@
FOX_PZ63823-284S-41F
VSS1AA4
VSS2AA11
VSS3AA13
VSS4AA15
VSS5AA17
VSS6AA19
VSS7AB2
VSS8AB7
VSS9AB9
VSS10AB23
VSS11AB25
VSS12AC11
VSS13AC13
VSS14AC15
VSS15AC17
VSS16AC19
VSS17AC21
VSS18AD6
VSS19AD8
VSS20AD25
VSS21AE11
VSS22AE13
VSS23AE15
VSS24AE17
VSS25AE19
VSS26AE21
VSS27AE23
VSS28B4
VSS29B6
VSS30B8
VSS31B9
VSS32B11
VSS33B13
VSS34B15
VSS35B17
VSS36B19
VSS37B21
VSS38B23
VSS39B25
VSS40D6
VSS41D8
VSS42D9
VSS43D11
VSS44D13
VSS45D15
VSS46D17
VSS47D19
VSS48D21
VSS49D23
VSS50D25
VSS51E4
VSS52F2
VSS53F11
VSS54F13
VSS55F15
VSS56F17
VSS57F19
VSS58F21
VSS59F23
VSS60F25
VSS61H7
VSS62H9
VSS63H21
VSS64H23
VSS65J4
VSS66 J6
VSS67 J8
VSS68 J10
VSS69 J12
VSS70 J14
VSS71 J16
VSS72 J18
VSS73 K2
VSS74 K7
VSS75 K9
VSS76 K11
VSS77 K13
VSS78 K15
VSS79 K17
VSS80 L6
VSS81 L8
VSS82 L10
VSS83 L12
VSS84 L14
VSS85 L16
VSS86 L18
VSS87 M7
VSS88 M9
VSS89 M11
VSS90 M17
VSS91 N4
VSS92 N8
VSS93 N10
VSS94 N16
VSS95 N18
VSS96 P2
VSS97 P7
VSS98 P9
VSS99 P11
VSS101 R8
VSS102 R10
VSS103 R16
VSS104 R18
VSS105 T7
VSS106 T9
VSS107 T11
VSS108 T13
VSS123 V13
VSS124 V15
VSS125 V17
VSS126 W6
VSS127 Y21
VSS128 Y23
VSS129 N6
VSS109 T15
VSS110 T17
VSS111 U4
VSS112 U6
VSS113 U8
VSS114 U10
VSS115 U12
VSS116 U14
VSS117 U16
VSS118 U18
VSS119 V2
VSS120 V7
VSS121 V9
VSS122 V11
VSS100 P17
C973
4.7U_0805_10V4Z
C973
4.7U_0805_10V4Z
1
2
hexainf@hotmail.com
8. 5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_A_BS#0
DDR_A_D26
DDR_A_D29
DDR_A_D27
DDR_A_D30
DDR_A_D33
DDR_A_D31
DDR_A_D32
DDR_A_D28
DDR_A_D34
DDR_A_D35
DDR_A_D38
DDR_A_D36
DDR_A_D39
DDR_A_D37
DDR_A_D41
DDR_A_D42
DDR_A_D44
DDR_A_D40
DDR_A_D43 DDR_A_D47
DDR_A_D48
DDR_A_D45
DDR_A_D46
DDR_A_D49 DDR_A_D53
DDR_A_D51 DDR_A_D55
DDR_A_D50
DDR_A_D52
DDR_A_D56
DDR_A_D54
DDR_A_D59
DDR_A_D57
DDR_A_D58
DDR_A_D61
DDR_A_D63
DDR_A_D60
DDR_A_D3
DDR_A_D8
DDR_A_D6
DDR_A_D7
DDR_A_D5
DDR_A_D14
DDR_A_D9
DDR_A_D11
DDR_A_D10
DDR_A_D13
DDR_A_D16
DDR_A_D15
DDR_A_D12
DDR_A_D17
DDR_A_D20
DDR_A_D18 DDR_A_D22
DDR_A_D19
DDR_A_D24
DDR_A_D21
DDR_A_D23
DDR_A_BS#2
DDR_A_BS#1
DDR_A_D25
DDR_A_D62
DDR_A_DM7
DDR_A_DM2
DDR_A_DM4
DDR_A_DM3
DDR_A_DM1
DDR_A_DM0
DDR_A_DM6
DDR_A_DM5
DDR_A_MA4
DDR_A_D0
DDR_A_D2
DDR_A_D1
DDR_A_D4
DDR_A_MA11
DDR_A_MA10
DDR_A_MA12
DDR_A_MA9
DDR_A_MA6DDR_A_MA8
DDR_A_MA5
DDR_A_MA7
DDR_A_MA3
DDR_A_MA0
DDR_A_MA13
DDR_A_MA15
DDR_A_MA2
DDR_A_MA1
DDR_A_MA14
DDR_A_DQS2
DDR_A_DQS#0
DDR_A_DQS4
DDR_A_DQS0
DDR_A_DQS#1
DDR_A_DQS5
DDR_A_DQS7
DDR_A_DQS3
DDR_A_DQS6
DDR_A_DQS#7
DDR_A_DQS#4
DDR_A_DQS#2
DDR_A_DQS#6
DDR_A_DQS#3
DDR_A_DQS1
DDR_A_DQS#5
DDR_A_ODT1
DDR_CKE0_DIMMA
DDR_CS1_DIMMA#
DDR_A_RAS#
DDR_A_WE#
DDR_CKE1_DIMMA
DDR_A_CAS#
DDR_CS0_DIMMA#
DDR_A_CLK#2
DDR_A_ODT0
DDR_A_CLK#1
DDR_A_CLK1
DDR_A_CLK2
DDR_CS3_DIMMA#
DDR_CS2_DIMMA#
SB_CK_SDAT
SB_CK_SCLK
DDR_A_D[0..63]
DDR_A_MA[0..15]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_DQS#[0..7]
DDR_A_BS#1
DDR_A_MA0
DDR_CS0_DIMMA#
DDR_CKE0_DIMMA
DDR_CS2_DIMMA#
DDR_A_BS#2
DDR_A_MA12
DDR_A_MA5
DDR_A_MA8
DDR_A_MA9
DDR_A_MA3
DDR_A_BS#0
DDR_A_MA10
DDR_A_MA1
DDR_A_WE#
DDR_A_ODT1
DDR_CS1_DIMMA#
DDR_A_CAS#
DDR_A_MA13
DDR_CS3_DIMMA#
DDR_A_ODT0
DDR_A_RAS#
DDR_A_MA2
DDR_A_MA4
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA14
DDR_CKE1_DIMMA
DDR_A_MA15
DDR_A_MA[0..15]<5>
DDR_A_D[0..63]<5>
DDR_A_DQS[0..7]<5>
DDR_A_DM[0..7]<5>
DDR_A_DQS#[0..7]<5>
DDR_A_CLK1 <5>
DDR_A_CLK#1 <5>
DDR_CKE0_DIMMA<5>
DDR_CS2_DIMMA#<5>
DDR_A_BS#2<5>
DDR_A_BS#0<5>
DDR_A_WE#<5>
DDR_A_CAS#<5>
DDR_CS1_DIMMA#<5>
DDR_A_ODT1<5>
DDR_A_CLK2 <5>
DDR_A_CLK#2 <5>
DDR_CS3_DIMMA# <5>
DDR_CS0_DIMMA# <5>
DDR_A_ODT0 <5>
DDR_A_RAS# <5>
DDR_A_BS#1 <5>
DDR_CKE1_DIMMA <5>
SB_CK_SCLK<9,20,25,31>
SB_CK_SDAT<9,20,25,31>
+1.8V+DIMM_VREF
+1.8V
+1.8V
+3VS
+1.8V+0.9V
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
8 49Monday, May 04, 2009
2007/5/18 2009/06/11
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
8 49Monday, May 04, 2009
2007/5/18 2009/06/11
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
8 49Monday, May 04, 2009
2007/5/18 2009/06/11
Compal Electronics, Inc.
JAWD0 used
DIMM1 REV H:5.2mm (BOT)
RP28
47_0804_8P4R_5%
RP28
47_0804_8P4R_5%
18
27
36
45
RP24
47_0804_8P4R_5%
RP24
47_0804_8P4R_5%
18
27
36
45
C1002 0.1U_0402_16V4ZC1002 0.1U_0402_16V4Z
1 2
C992 0.1U_0402_16V4Z
<BOM Structure>
C992 0.1U_0402_16V4Z
<BOM Structure>
1 2
R832
1K_0402_1%
R832
1K_0402_1%
12
R835 10K_0402_5%R835 10K_0402_5%1 2
C993 0.1U_0402_16V4ZC993 0.1U_0402_16V4Z
1 2
C986
4.7U_0805_10V4Z
C986
4.7U_0805_10V4Z
1
2
C991 0.1U_0402_16V4Z
<BOM Structure>
C991 0.1U_0402_16V4Z
<BOM Structure>
1 2
C989 0.1U_0402_16V4Z
<BOM Structure>
C989 0.1U_0402_16V4Z
<BOM Structure>
1 2
RP30
47_0804_8P4R_5%
RP30
47_0804_8P4R_5%
18
27
36
45
C999 0.1U_0402_16V4ZC999 0.1U_0402_16V4Z
1 2
C990 0.1U_0402_16V4Z
<BOM Structure>
C990 0.1U_0402_16V4Z
<BOM Structure>
1 2
RP25
47_0804_8P4R_5%
RP25
47_0804_8P4R_5%
18
27
36
45
C994 0.1U_0402_16V4ZC994 0.1U_0402_16V4Z
1 2
RP31
47_0804_8P4R_5%
RP31
47_0804_8P4R_5%
18
27
36
45
JDIMM1
FOX_AS0A426-M2RN-7F
CONN@
JDIMM1
FOX_AS0A426-M2RN-7F
CONN@
VREF1
VSS3
DQ05
DQ17
VSS9
DQS0#11
DQS013
VSS15
DQ217
DQ319
VSS21
DQ823
DQ925
VSS27
DQS1#29
DQS131
VSS33
DQ1035
DQ1137
VSS39
VSS41
DQ1643
DQ1745
VSS47
DQS2#49
DQS251
VSS53
DQ1855
DQ1957
VSS59
DQ2461
DQ2563
VSS65
DM367
NC69
VSS71
DQ2673
DQ2775
VSS77
CKE079
VDD81
NC83
BA285
VDD87
A1289
A991
A893
VDD95
A597
A399
A1101
VDD103
A10/AP105
BA0107
WE#109
VDD111
CAS#113
NC/S1#115
VDD117
NC/ODT1119
VSS121
DQ32123
DQ33125
VSS127
DQS4#129
DQS4131
VSS133
DQ34135
DQ35137
VSS139
DQ40141
DQ41143
VSS145
DM5147
VSS149
DQ42151
DQ43153
VSS155
DQ48157
DQ49159
VSS161
NC,TEST163
VSS165
DQS6#167
DQS6169
VSS171
DQ50173
DQ51175
VSS177
DQ56179
DQ57181
VSS183
DM7185
VSS187
DQ58189
DQ59191
VSS193
SDA195
SCL197
VDDSPD199
VSS 2
DQ4 4
DQ5 6
VSS 8
DM0 10
VSS 12
DQ6 14
DQ7 16
VSS 18
DQ12 20
DQ13 22
VSS 24
DM1 26
VSS 28
CK0 30
CK0# 32
VSS 34
DQ14 36
DQ15 38
VSS 40
VSS 42
DQ20 44
DQ21 46
VSS 48
NC 50
DM2 52
VSS 54
DQ22 56
DQ23 58
VSS 60
DQ28 62
DQ29 64
VSS 66
DQS3# 68
DQS3 70
VSS 72
DQ30 74
DQ31 76
VSS 78
NC/CKE1 80
VDD 82
NC/A15 84
NC/A14 86
VDD 88
A11 90
A7 92
A6 94
VDD 96
A4 98
A2 100
A0 102
VDD 104
BA1 106
RAS# 108
S0# 110
VDD 112
ODT0 114
NC/A13 116
VDD 118
NC 120
VSS 122
DQ36 124
DQ37 126
VSS 128
DM4 130
VSS 132
DQ38 134
DQ39 136
VSS 138
DQ44 140
DQ45 142
VSS 144
DQS5# 146
DQS5 148
VSS 150
DQ46 152
DQ47 154
VSS 156
DQ52 158
DQ53 160
VSS 162
CK1 164
CK1# 166
VSS 168
DM6 170
VSS 172
DQ54 174
DQ55 176
VSS 178
DQ60 180
DQ61 182
VSS 184
DQS7# 186
DQS7 188
VSS 190
DQ62 192
DQ63 194
VSS 196
SAO 198
SA1 200
GND203 GND 204
R833
1K_0402_1%
R833
1K_0402_1%
12
R834 10K_0402_5%R834 10K_0402_5%1 2
C995 0.1U_0402_16V4ZC995 0.1U_0402_16V4Z
1 2
C985 0.1U_0402_16V4Z
<BOM Structure>
C985 0.1U_0402_16V4Z
<BOM Structure>
1 2
C1000 0.1U_0402_16V4ZC1000 0.1U_0402_16V4Z
1 2
C996 0.1U_0402_16V4ZC996 0.1U_0402_16V4Z
1 2
C987
0.1U_0402_16V4Z
C987
0.1U_0402_16V4Z
1
2
C1001 0.1U_0402_16V4ZC1001 0.1U_0402_16V4Z
1 2
RP27
47_0804_8P4R_5%
RP27
47_0804_8P4R_5%
18
27
36
45
C1003
0.1U_0402_16V4Z
C1003
0.1U_0402_16V4Z
1
2
C988 0.1U_0402_16V4Z
<BOM Structure>
C988 0.1U_0402_16V4Z
<BOM Structure>
1 2
RP26
47_0804_8P4R_5%
RP26
47_0804_8P4R_5%
18
27
36
45
RP29
47_0804_8P4R_5%
RP29
47_0804_8P4R_5%
18
27
36
45 C997 0.1U_0402_16V4ZC997 0.1U_0402_16V4Z
1 2
C998 0.1U_0402_16V4ZC998 0.1U_0402_16V4Z
1 2
9. 5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_B_BS#0
DDR_B_D26
DDR_B_D29
DDR_B_D27
DDR_B_D30
DDR_B_D33
DDR_B_D31
DDR_B_D32
DDR_B_D28
DDR_B_D34
DDR_B_D35
DDR_B_D38
DDR_B_D36
DDR_B_D39
DDR_B_D37
DDR_B_D41
DDR_B_D42
DDR_B_D44
DDR_B_D40
DDR_B_D43 DDR_B_D47
DDR_B_D48
DDR_B_D45
DDR_B_D46
DDR_B_D49 DDR_B_D53
DDR_B_D51 DDR_B_D55
DDR_B_D50
DDR_B_D52
DDR_B_D56
DDR_B_D54
DDR_B_D59
DDR_B_D57
DDR_B_D58
DDR_B_D61
DDR_B_D63
DDR_B_D60
DDR_B_D3
DDR_B_D8
DDR_B_D6
DDR_B_D7
DDR_B_D5
DDR_B_D14
DDR_B_D9
DDR_B_D11
DDR_B_D10
DDR_B_D13
DDR_B_D16
DDR_B_D15
DDR_B_D12
DDR_B_D17
DDR_B_D20
DDR_B_D18 DDR_B_D22
DDR_B_D19
DDR_B_D24
DDR_B_D21
DDR_B_D23
DDR_B_BS#2
DDR_B_BS#1
DDR_B_D25
DDR_B_D62
DDR_B_DM7
DDR_B_DM2
DDR_B_DM4
DDR_B_DM3
DDR_B_DM1
DDR_B_DM0
DDR_B_DM6
DDR_B_DM5
DDR_B_MA4
DDR_B_D0
DDR_B_D2
DDR_B_D1
DDR_B_D4
DDR_B_MA11
DDR_B_MA10
DDR_B_MA12
DDR_B_MA9
DDR_B_MA6DDR_B_MA8
DDR_B_MA5
DDR_B_MA7
DDR_B_MA3
DDR_B_MA0
DDR_B_MA13
DDR_B_MA15
DDR_B_MA2
DDR_B_MA1
DDR_B_MA14
DDR_B_DQS2
DDR_B_DQS#0
DDR_B_DQS4
DDR_B_DQS0
DDR_B_DQS#1
DDR_B_DQS5
DDR_B_DQS7
DDR_B_DQS3
DDR_B_DQS6
DDR_B_DQS#7
DDR_B_DQS#4
DDR_B_DQS#2
DDR_B_DQS#6
DDR_B_DQS#3
DDR_B_DQS1
DDR_B_DQS#5
DDR_B_ODT1
DDR_CKE0_DIMMB
DDR_CS1_DIMMB#
DDR_B_RAS#
DDR_B_WE#
DDR_CKE1_DIMMB
DDR_B_CAS#
DDR_CS0_DIMMB#
DDR_B_CLK#2
DDR_B_ODT0
DDR_B_CLK#1
DDR_B_CLK1
DDR_B_CLK2
DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
SB_CK_SDAT
SB_CK_SCLK
DDR_B_D[0..63]
DDR_B_MA[0..15]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_DQS#[0..7]
DDR_B_MA12
DDR_B_WE#
DDR_B_ODT1
DDR_B_CAS#
DDR_CS1_DIMMB#
DDR_B_MA5
DDR_B_MA8
DDR_B_MA9
DDR_B_BS#0
DDR_B_MA10
DDR_B_MA3
DDR_B_MA1
DDR_CS2_DIMMB#
DDR_B_BS#2
DDR_CKE0_DIMMB
DDR_B_MA14
DDR_CKE1_DIMMB
DDR_B_MA15
DDR_B_BS#1
DDR_B_MA2
DDR_B_MA0
DDR_CS0_DIMMB#
DDR_B_MA6
DDR_B_MA4
DDR_B_MA11
DDR_B_MA7
DDR_B_ODT0
DDR_B_MA13
DDR_B_RAS#
DDR_CS3_DIMMB#
DDR_B_MA[0..15]<5>
DDR_B_D[0..63]<5>
DDR_B_DQS[0..7]<5>
DDR_B_DM[0..7]<5>
DDR_B_DQS#[0..7]<5>
DDR_B_CLK1 <5>
DDR_B_CLK#1 <5>
DDR_CKE0_DIMMB<5>
DDR_CS2_DIMMB#<5>
DDR_B_BS#2<5>
DDR_B_BS#0<5>
DDR_B_WE#<5>
DDR_B_CAS#<5>
DDR_CS1_DIMMB#<5>
DDR_B_ODT1<5>
DDR_B_CLK2 <5>
DDR_B_CLK#2 <5>
DDR_CS3_DIMMB# <5>
DDR_CS0_DIMMB# <5>
DDR_B_ODT0 <5>
DDR_B_RAS# <5>
DDR_B_BS#1 <5>
DDR_CKE1_DIMMB <5>
SB_CK_SCLK<8,20,25,31>
SB_CK_SDAT<8,20,25,31>
+DIMM_VREF
+1.8V
+1.8V
+3VS
+3VS
+0.9V +1.8V
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
9 49Monday, May 04, 2009
2007/5/18 2009/06/11
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
9 49Monday, May 04, 2009
2007/5/18 2009/06/11
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
9 49Monday, May 04, 2009
2007/5/18 2009/06/11
Compal Electronics, Inc.DIMM2 H:5.2mm (BOT)
KAV10 used
RP33
47_0804_8P4R_5%
RP33
47_0804_8P4R_5%
18
27
36
45
C1013 0.1U_0402_16V4ZC1013 0.1U_0402_16V4Z
12
C1007
0.1U_0402_16V4Z
C1007
0.1U_0402_16V4Z
1
2
RP37
47_0804_8P4R_5%
RP37
47_0804_8P4R_5%
18
27
36
45
C1005 0.1U_0402_16V4Z
<BOM Structure>
C1005 0.1U_0402_16V4Z
<BOM Structure>
12
C1016 0.1U_0402_16V4ZC1016 0.1U_0402_16V4Z
12
C1006
4.7U_0805_10V4Z
C1006
4.7U_0805_10V4Z
1
2
C1014 0.1U_0402_16V4ZC1014 0.1U_0402_16V4Z
12
RP39
47_0804_8P4R_5%
RP39
47_0804_8P4R_5%
18
27
36
45
RP38
47_0804_8P4R_5%
RP38
47_0804_8P4R_5%
18
27
36
45
R837 10K_0402_5%R837 10K_0402_5%1 2
C1012 0.1U_0402_16V4ZC1012 0.1U_0402_16V4Z
1 2
RP35
47_0804_8P4R_5%
RP35
47_0804_8P4R_5%
18
27
36
45
RP32
47_0804_8P4R_5%
RP32
47_0804_8P4R_5%
18
27
36
45 C1004 0.1U_0402_16V4Z
<BOM Structure>
C1004 0.1U_0402_16V4Z
<BOM Structure>
1 2
C1015 0.1U_0402_16V4ZC1015 0.1U_0402_16V4Z
1 2
RP34
47_0804_8P4R_5%
RP34
47_0804_8P4R_5%
18
27
36
45
JDIMM2
P-TWO_A5652C-A0G16
CONN@
JDIMM2
P-TWO_A5652C-A0G16
CONN@
VREF1
VSS3
DQ05
DQ17
VSS9
DQS0#11
DQS013
VSS15
DQ217
DQ319
VSS21
DQ823
DQ925
VSS27
DQS1#29
DQS131
VSS33
DQ1035
DQ1137
VSS39
VSS 2
DQ4 4
DQ5 6
VSS 8
DM0 10
VSS 12
DQ6 14
DQ7 16
VSS 18
DQ12 20
DQ13 22
VSS 24
DM1 26
VSS 28
CK0 30
CK0# 32
VSS 34
DQ14 36
DQ15 38
VSS 40
VSS41
DQ1643
DQ1745
VSS47
DQS2#49
DQS251
VSS53
DQ1855
DQ1957
VSS59
DQ2461
DQ2563
VSS65
DM367
NC69
VSS71
DQ2673
DQ2775
VSS77
CKE079
VDD81
NC83
BA285
VDD87
A1289
A991
A893
VDD95
A597
A399
A1101
VDD103
A10/AP105
BA0107
WE#109
VDD111
CAS#113
NC/S1#115
VDD117
NC/ODT1119
VSS121
DQ32123
DQ33125
VSS127
DQS4#129
DQS4131
VSS133
DQ34135
DQ35137
VSS139
DQ40141
DQ41143
VSS145
DM5147
VSS149
DQ42151
DQ43153
VSS155
DQ48157
DQ49159
VSS161
NC,TEST163
VSS165
DQS6#167
DQS6169
VSS171
DQ50173
DQ51175
VSS177
DQ56179
DQ57181
VSS183
DM7185
VSS187
DQ58189
DQ59191
VSS193
SDA195
SCL197
VDDSPD199
VSS 42
DQ20 44
DQ21 46
VSS 48
NC 50
DM2 52
VSS 54
DQ22 56
DQ23 58
VSS 60
DQ28 62
DQ29 64
VSS 66
DQS3# 68
DQS3 70
VSS 72
DQ30 74
DQ31 76
VSS 78
NC/CKE1 80
VDD 82
NC/A15 84
NC/A14 86
VDD 88
A11 90
A7 92
A6 94
VDD 96
A4 98
A2 100
A0 102
VDD 104
BA1 106
RAS# 108
S0# 110
VDD 112
ODT0 114
NC/A13 116
VDD 118
NC 120
VSS 122
DQ36 124
DQ37 126
VSS 128
DM4 130
VSS 132
DQ38 134
DQ39 136
VSS 138
DQ44 140
DQ45 142
VSS 144
DQS5# 146
DQS5 148
VSS 150
DQ46 152
DQ47 154
VSS 156
DQ52 158
DQ53 160
VSS 162
CK1 164
CK1# 166
VSS 168
DM6 170
VSS 172
DQ54 174
DQ55 176
VSS 178
DQ60 180
DQ61 182
VSS 184
DQS7# 186
DQS7 188
VSS 190
DQ62 192
DQ63 194
VSS 196
SAO 198
SA1 200
C1008 0.1U_0402_16V4Z
<BOM Structure>
C1008 0.1U_0402_16V4Z
<BOM Structure>
1 2
C1020 0.1U_0402_16V4ZC1020 0.1U_0402_16V4Z
12
C1009 0.1U_0402_16V4Z
<BOM Structure>
C1009 0.1U_0402_16V4Z
<BOM Structure>
12
C1017 0.1U_0402_16V4ZC1017 0.1U_0402_16V4Z
1 2
RP36
47_0804_8P4R_5%
RP36
47_0804_8P4R_5%
18
27
36
45
C1011 0.1U_0402_16V4Z
<BOM Structure>
C1011 0.1U_0402_16V4Z
<BOM Structure>
12
C1010 0.1U_0402_16V4Z
<BOM Structure>
C1010 0.1U_0402_16V4Z
<BOM Structure>
1 2
C1018 0.1U_0402_16V4ZC1018 0.1U_0402_16V4Z
12
C1021 0.1U_0402_16V4ZC1021 0.1U_0402_16V4Z
1 2
C1022
0.1U_0402_16V4Z
C1022
0.1U_0402_16V4Z
1
2
R836 10K_0402_5%R836 10K_0402_5%1 2
C1019 0.1U_0402_16V4ZC1019 0.1U_0402_16V4Z
1 2
hexainf@hotmail.com
10. A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SB_TX2P_C
SB_TX2N_C
SB_TX3P_C
SB_TX3N_C
SB_TX0P_C
SB_TX0N_C
SB_TX1P_C
H_CADIN[0..15]
H_CADIP[0..15]H_CADOP[0..15]
H_CADON[0..15]
SB_TX1N_C
H_CADIN0
H_CADIP1
H_CADIN1
H_CADIN2
H_CADIP2
H_CADIN3
H_CADIP3
H_CTLIN0
H_CTLIP0
H_CTLON0
H_CADIN4
H_CADIP4
H_CADIN5
H_CADIP5
H_CADIN6
H_CADIP6
H_CADIN7
H_CADIP7
H_CADIN8
H_CADIP8
H_CADIN9
H_CADIP9
H_CADIN10
H_CADIP10
H_CTLOP0
H_CADIP11
H_CADIN11
H_CADIP12
H_CADIN12
H_CADIN13
H_CADIP13
H_CADIN14
H_CADIP14
H_CADIN15
H_CADIP15
H_CADOP0
H_CADON0
H_CADOP1
H_CADON1
H_CADON2
H_CADOP2
H_CADOP3
H_CADON3
H_CADON4
H_CADOP4
H_CADOP5
H_CADON5
H_CADOP6
H_CADON6
H_CADOP7
H_CADON7
H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADON10
H_CADOP10
H_CADON9
H_CADOP9
H_CADOP8
H_CADON8
H_CADIP0
PCIE_MTX_GRX_N8 PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P10 PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_N11
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_GRX_N10
PCIE_MTX_C_GRX_P13
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P12
PCIE_MTX_GRX_N14
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_N13 PCIE_MTX_C_GRX_N13
PCIE_MTX_GRX_P15
PCIE_MTX_GRX_N15 PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_P15
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P0 PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0PCIE_MTX_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1 PCIE_MTX_C_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P3
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P5
PCIE_MTX_GRX_N4
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P6
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_N5 PCIE_MTX_C_GRX_N5
PCIE_MTX_GRX_N7 PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P7
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_P7
PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
PCIE_MTX_GRX_P[0..3]
PCIE_MTX_GRX_N[0..3]
H_CTLON1
H_CTLOP1 H_CTLIP1
H_CTLIN1
PCIE_ITX_PRX_P2
PCIE_ITX_PRX_N1
PCIE_ITX_PRX_N0
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P0
PCIE_ITX_PRX_P1
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P6
H_CADIP[0..15] <4>
H_CADON[0..15]<4> H_CADIN[0..15] <4>
H_CADOP[0..15]<4>
SB_RX1P<24>
SB_RX1N<24>
SB_RX0P<24>
SB_RX0N<24>
SB_TX0P <24>
SB_TX1N <24>
SB_TX0N <24>
SB_TX1P <24>
SB_RX3P<24>
SB_RX3N<24>
SB_RX2P<24>
SB_RX2N<24>
SB_TX2P <24>
SB_TX2N <24>
SB_TX3N <24>
SB_TX3P <24>
H_CLKIN0 <4>
H_CLKIP0 <4>
H_CTLIN0 <4>
H_CTLIP0 <4>
H_CLKON0<4>
H_CLKOP0<4>
H_CLKOP1<4>
H_CLKON1<4>
H_CTLOP0<4>
H_CTLON0<4>
H_CLKIN1 <4>
H_CLKIP1 <4>
PCIE_MTX_C_GRX_N[0..15] <14>
PCIE_MTX_C_GRX_P[0..15] <14>PCIE_GTX_C_MRX_P[0..15]<14>
PCIE_GTX_C_MRX_N[0..15]<14> PCIE_MTX_GRX_P[0..3] <22>
PCIE_MTX_GRX_N[0..3] <22>
H_CTLOP1<4>
H_CTLON1<4>
H_CTLIP1 <4>
H_CTLIN1 <4>
PCIE_PTX_C_IRX_N1<31>
PCIE_PTX_C_IRX_P1<31>
PCIE_PTX_C_IRX_N0<31>
PCIE_PTX_C_IRX_P0<31>
PCIE_PTX_C_IRX_N2<31>
PCIE_PTX_C_IRX_P2<31>
PCIE_ITX_C_PRX_N2 <31>
PCIE_ITX_C_PRX_P2 <31>
PCIE_ITX_C_PRX_N1 <31>
PCIE_ITX_C_PRX_P1 <31>
PCIE_ITX_C_PRX_N0 <31>
PCIE_ITX_C_PRX_P0 <31>
+1.1VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
10 49Monday, May 04, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
10 49Monday, May 04, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
10 49Monday, May 04, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
DP0
GFX_TX0,TX1,TX2 and TX3
RS780M Display Port Support (muxed on GFX)
DP1
GFX_TX4,TX5,TX6 and TX7
AUX0 and HPD0
AUX1 and HPD1
0718 Place within 1"
layout 1:2
0718 Place within 1"
layout 1:2
SA00002DR30 S IC 216-0674026 A13 RS780MN FCBGA 0FA
WWAN
GLAN
WLAN
For M92 S2-LP
disable PCIE GFX 0~7
( Remove 3G Function )
C650 0.1U_0402_16V7K@C650 0.1U_0402_16V7K@1 2
C649 0.1U_0402_16V7K@C649 0.1U_0402_16V7K@1 2
C634 0.1U_0402_16V7KVGA@C634 0.1U_0402_16V7KVGA@1 2
C615 0.1U_0402_16V7KC615 0.1U_0402_16V7K1 2
C648 0.1U_0402_16V7K@C648 0.1U_0402_16V7K@1 2
R56
301_0402_1%~D
R56
301_0402_1%~D
1 2
PART 2 OF 6
PCIEI/FGFX
PCIE I/F GPP
PCIE I/F SB
U3B
RS780M_FCBGA528
PART 2 OF 6
PCIEI/FGFX
PCIE I/F GPP
PCIE I/F SB
U3B
RS780M_FCBGA528
SB_TX3P AD5
SB_TX3N AE5
GPP_TX2P AA2
GPP_TX2N AA1
GPP_TX3P Y1
GPP_TX3N Y2
SB_RX3PW5
SB_RX3NY5
GPP_RX2PAD1
GPP_RX2NAD2
GPP_RX3PV5
GPP_RX3NW6
SB_TX0P AD7
SB_TX0N AE7
SB_TX1P AE6
SB_TX1N AD6
SB_RX0PAA8
SB_RX0NY8
SB_RX1PAA7
SB_RX1NY7
PCE_CALRP(PCE_BCALRP) AC8
PCE_CALRN(PCE_BCALRN) AB8
SB_TX2N AC6
SB_RX2PAA5
SB_RX2NAA6
SB_TX2P AB6
GPP_RX0PAE3
GPP_RX0NAD4
GPP_RX1PAE2
GPP_RX1NAD3
GPP_TX0P AC1
GPP_TX0N AC2
GPP_TX1P AB4
GPP_TX1N AB3
GFX_RX0PD4
GFX_RX0NC4
GFX_RX1PA3
GFX_RX1NB3
GFX_RX2PC2
GFX_RX2NC1
GFX_RX3PE5
GFX_RX3NF5
GFX_RX4PG5
GFX_RX4NG6
GFX_RX5PH5
GFX_RX5NH6
GFX_RX6PJ6
GFX_RX6NJ5
GFX_RX7PJ7
GFX_RX7NJ8
GFX_RX8PL5
GFX_RX8NL6
GFX_RX9PM8
GFX_RX9NL8
GFX_RX10PP7
GFX_RX10NM7
GFX_RX11PP5
GFX_RX11NM5
GFX_RX12PR8
GFX_RX12NP8
GFX_RX13PR6
GFX_RX13NR5
GFX_RX14PP4
GFX_RX14NP3
GFX_RX15PT4
GFX_RX15NT3
GFX_TX0P A5
GFX_TX0N B5
GFX_TX1P A4
GFX_TX1N B4
GFX_TX2P C3
GFX_TX2N B2
GFX_TX3P D1
GFX_TX3N D2
GFX_TX4P E2
GFX_TX4N E1
GFX_TX5P F4
GFX_TX5N F3
GFX_TX6P F1
GFX_TX6N F2
GFX_TX7P H4
GFX_TX7N H3
GFX_TX8P H1
GFX_TX8N H2
GFX_TX9P J2
GFX_TX9N J1
GFX_TX10P K4
GFX_TX10N K3
GFX_TX11P K1
GFX_TX11N K2
GFX_TX12P M4
GFX_TX12N M3
GFX_TX13P M1
GFX_TX13N M2
GFX_TX14P N2
GFX_TX14N N1
GFX_TX15P P1
GFX_TX15N P2
GPP_TX4P Y4
GPP_TX4N Y3
GPP_TX5P V1
GPP_TX5N V2
GPP_RX4PU5
GPP_RX4NU6
GPP_RX5PU8
GPP_RX5NU7
C38 0.1U_0402_16V7KC38 0.1U_0402_16V7K1 2
C659 0.1U_0402_16V7K@C659 0.1U_0402_16V7K@1 2
C657 0.1U_0402_16V7K@C657 0.1U_0402_16V7K@1 2
C617 0.1U_0402_16V7KC617 0.1U_0402_16V7K1 2
C629 0.1U_0402_16V7KVGA@C629 0.1U_0402_16V7KVGA@1 2
C656 0.1U_0402_16V7K@C656 0.1U_0402_16V7K@1 2
C651 0.1U_0402_16V7K@C651 0.1U_0402_16V7K@1 2
C46 0.1U_0402_16V7K@C46 0.1U_0402_16V7K@ 1 2
C637 0.1U_0402_16V7KVGA@C637 0.1U_0402_16V7KVGA@1 2
C658 0.1U_0402_16V7K@C658 0.1U_0402_16V7K@1 2
C635 0.1U_0402_16V7KVGA@C635 0.1U_0402_16V7KVGA@1 2
C623 0.1U_0402_16V7KVGA@C623 0.1U_0402_16V7KVGA@1 2
C636 0.1U_0402_16V7KVGA@C636 0.1U_0402_16V7KVGA@1 2
C630 0.1U_0402_16V7KVGA@C630 0.1U_0402_16V7KVGA@1 2
C37 0.1U_0402_16V7KC37 0.1U_0402_16V7K1 2
C42 0.1U_0402_16V7K@C42 0.1U_0402_16V7K@ 1 2
C646 0.1U_0402_16V7K@C646 0.1U_0402_16V7K@1 2
C641 0.1U_0402_16V7K@C641 0.1U_0402_16V7K@1 2
C653 0.1U_0402_16V7K@C653 0.1U_0402_16V7K@1 2
C610 0.1U_0402_16V7KC610 0.1U_0402_16V7K1 2
C647 0.1U_0402_16V7K@C647 0.1U_0402_16V7K@1 2
R51
301_0402_1%~D
R51
301_0402_1%~D
1 2
C627 0.1U_0402_16V7KVGA@C627 0.1U_0402_16V7KVGA@1 2
C609 0.1U_0402_16V7KC609 0.1U_0402_16V7K1 2
C32 0.1U_0402_16V7KC32 0.1U_0402_16V7K1 2
C616 0.1U_0402_16V7KC616 0.1U_0402_16V7K1 2
C642 0.1U_0402_16V7K@C642 0.1U_0402_16V7K@1 2
C654 0.1U_0402_16V7K@C654 0.1U_0402_16V7K@1 2
PART 1 OF 6
HYPERTRANSPORTCPUI/F
U3A
RS780M_FCBGA528
PART 1 OF 6
HYPERTRANSPORTCPUI/F
U3A
RS780M_FCBGA528
HT_RXCAD15PU19
HT_RXCAD15NU18
HT_RXCAD14PU20
HT_RXCAD14NU21
HT_RXCAD13PV21
HT_RXCAD13NV20
HT_RXCAD12PW21
HT_RXCAD12NW20
HT_RXCAD11PY22
HT_RXCAD11NY23
HT_RXCAD10PAA24
HT_RXCAD10NAA25
HT_RXCAD9PAB25
HT_RXCAD9NAB24
HT_RXCAD8PAC24
HT_RXCAD8NAC25
HT_RXCAD7PN24
HT_RXCAD7NN25
HT_RXCAD6PP25
HT_RXCAD6NP24
HT_RXCAD5PP22
HT_RXCAD5NP23
HT_RXCAD4PT25
HT_RXCAD4NT24
HT_RXCAD3PU24
HT_RXCAD3NU25
HT_RXCAD2PV25
HT_RXCAD2NV24
HT_RXCAD1PV22
HT_RXCAD1NV23
HT_RXCAD0PY25
HT_RXCAD0NY24
HT_RXCLK1PAB23
HT_RXCLK1NAA22
HT_RXCLK0PT22
HT_RXCLK0NT23
HT_RXCTL0PM22
HT_RXCTL0NM23
HT_RXCTL1PR21
HT_RXCTL1NR20
HT_RXCALPC23
HT_RXCALNA24
HT_TXCAD15P P18
HT_TXCAD15N M18
HT_TXCAD14P M21
HT_TXCAD14N P21
HT_TXCAD13P M19
HT_TXCAD13N L18
HT_TXCAD12P L19
HT_TXCAD12N J19
HT_TXCAD11P J18
HT_TXCAD11N K17
HT_TXCAD10P J20
HT_TXCAD10N J21
HT_TXCAD9P G20
HT_TXCAD9N H21
HT_TXCAD8P F21
HT_TXCAD8N G21
HT_TXCAD7P K23
HT_TXCAD7N K22
HT_TXCAD6P K24
HT_TXCAD6N K25
HT_TXCAD5P J25
HT_TXCAD5N J24
HT_TXCAD4P H23
HT_TXCAD4N H22
HT_TXCAD3P F23
HT_TXCAD3N F22
HT_TXCAD2P F24
HT_TXCAD2N F25
HT_TXCAD1P E24
HT_TXCAD1N E25
HT_TXCAD0P D24
HT_TXCAD0N D25
HT_TXCLK1P L21
HT_TXCLK1N L20
HT_TXCLK0P H24
HT_TXCLK0N H25
HT_TXCTL0P M24
HT_TXCTL0N M25
HT_TXCTL1P P19
HT_TXCTL1N R18
HT_TXCALP B24
HT_TXCALN B25
C614 0.1U_0402_16V7KC614 0.1U_0402_16V7K1 2
C618 0.1U_0402_16V7KC618 0.1U_0402_16V7K1 2
C619 0.1U_0402_16V7KVGA@C619 0.1U_0402_16V7KVGA@1 2
C620 0.1U_0402_16V7KVGA@C620 0.1U_0402_16V7KVGA@1 2
C33 0.1U_0402_16V7KC33 0.1U_0402_16V7K1 2
C613 0.1U_0402_16V7KC613 0.1U_0402_16V7K1 2
C631 0.1U_0402_16V7KVGA@C631 0.1U_0402_16V7KVGA@1 2
R267 2K_0402_1%R267 2K_0402_1%1 2
C621 0.1U_0402_16V7KVGA@C621 0.1U_0402_16V7KVGA@1 2
C655 0.1U_0402_16V7K@C655 0.1U_0402_16V7K@1 2
R32 1.27K_0402_1%R32 1.27K_0402_1%1 2
C638 0.1U_0402_16V7KVGA@C638 0.1U_0402_16V7KVGA@1 2
C624 0.1U_0402_16V7KVGA@C624 0.1U_0402_16V7KVGA@1 2
C652 0.1U_0402_16V7K@C652 0.1U_0402_16V7K@1 2
C632 0.1U_0402_16V7KVGA@C632 0.1U_0402_16V7KVGA@1 2
C625 0.1U_0402_16V7KVGA@C625 0.1U_0402_16V7KVGA@1 2
11. A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
NB_RESET#
GMCH_CRT_VSYNC
GMCH_CRT_HSYNC
NB_ALLOW_LDTSTOP
NB_LDTSTOP#
NB_LDTSTOP#
NB_ALLOW_LDTSTOP
+VDDLTP18
+VDDLT18
UMA_ENVDD
+VDDLT18
UMA_ENBKL
+AVDD2
+AVDDQ
+AVDD1
GMCH_CRT_R
GMCH_CRT_B
GMCH_CRT_G
GMCH_CRT_DATA
GMCH_CRT_CLK
+NB_HTPVDD
+NB_PLLVDD
GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B
GMCH_LCD_CLK
GMCH_LCD_CLK
GMCH_LCD_DATA
GMCH_LCD_DATA
POWER_SEL
+VDDLTP18
GMCH_HDMI_CLK_R1
GMCH_HDMI_DATA_R1
CLK_NB_14.318M
CLK_NB_14.318M
GMCH_HDMI_DATA_R1
GMCH_HDMI_CLK_R1
GMCH_HDMI_CLK_R2
GMCH_HDMI_DATA_R2
GMCH_HDMI_CLK_R2
GMCH_HDMI_DATA_R2
GMCH_HDMI_CLK
GMCH_HDMI_DATA
UMA_DPST
UMA_ENBKL
NB_PWRGD
UMA_ENVDD
UMA_DPST ENBKL
NB_PWRGD<25>
GMCH_CRT_HSYNC<13,23>
GMCH_CRT_VSYNC<13,23>
CLK_NB_14.318M<20>
CLK_NBGFX<20>
CLK_NBGFX#<20>
CLK_SBLINK_BCLK<20>
CLK_SBLINK_BCLK#<20>
CLK_NBHT<20>
CLK_NBHT#<20>
PLT_RST#<13,14,24,31,33>
AUX_CAL<13>
SUS_STAT# <25>
SUS_STAT_R# <13>
ALLOW_LDTSTOP<24>
LDT_STOP#<6,24>
GMCH_TXOUT0+ <21>
GMCH_TXOUT0- <21>
GMCH_TXOUT1+ <21>
GMCH_TXOUT1- <21>
GMCH_TXOUT2+ <21>
GMCH_TXOUT2- <21>
GMCH_TXCLK+ <21>
GMCH_TXCLK- <21>
UMA_ENBKL <21>
HDMI_DET <15,22>
GMCH_CRT_R<23>
GMCH_CRT_G<23>
GMCH_CRT_B<23>
GMCH_CRT_DATA<23>
GMCH_CRT_CLK<23>
GMCH_LCD_CLK<21>
GMCH_LCD_DATA<21>
POWER_SEL<43>
GMCH_HDMI_CLK<22>
GMCH_HDMI_DATA<22>
ENBKL <33>
UMA_ENVDD_R <21>
GMCH_TZOUT2+ <21>
GMCH_TZOUT2- <21>
GMCH_TZOUT0+ <21>
GMCH_TZOUT0- <21>
GMCH_TZOUT1+ <21>
GMCH_TZOUT1- <21>
GMCH_TZCLK- <21>
GMCH_TZCLK+ <21>
+1.8VS
+1.8VS
+VDDA18HTPLL
+VDDA18PCIEPLL
+1.1VS
+1.8VS
+1.8VS
+1.8VS
+1.8VS
+3VS
+1.8VS
+1.8VS
+NB_PLLVDD
+NB_HTPVDD
+VDDA18PCIEPLL
+VDDA18HTPLL
+NB_HTPVDD+1.8VS
+1.1VS
+3VS
+3VS
+NB_PLLVDD
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
11 49Monday, May 04, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
11 49Monday, May 04, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
11 49Monday, May 04, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Strap pin
Strap pin
For RS780M A13
RED: Connected to GND through two separate 140ohm 1% resistor
VDDLTP18=15mA
VDDLT18=0.3A
AVDD=0.11A
AVDDDI=20mA
AVDDQ=4mA
PLLVDD=65mA
PLLVDD18=20mA
VDDA18HTPLL=20mA
VDDA18PCIEPLL=0.12A
POWER_SEL
HIGH 1.0V
1.1VLOW
Change as 1K_5% ohm
for Tigris
Un-stuff for Tigris
DVT
DVT
DVT
AMD Vari bright function
C854
100P_0402_25V8K
@
C854
100P_0402_25V8K
@
1
2
C87
2.2U_0603_6.3V4Z
C87
2.2U_0603_6.3V4Z
1
2
C93
2.2U_0603_6.3V4Z
C93
2.2U_0603_6.3V4Z
1
2
L8
FBM-L11-201209-300LMA30T_0805
L8
FBM-L11-201209-300LMA30T_0805
1 2
C90
0.1U_0402_16V4Z
C90
0.1U_0402_16V4Z
1
2
C84
1U_0402_6.3V4Z
C84
1U_0402_6.3V4Z
1
2
R744 0_0402_5%R744 0_0402_5%
1 2
R491 0_0402_5%@R491 0_0402_5%@
1 2
R294
1.27K_0402_1%
UMA@
R294
1.27K_0402_1%
UMA@
12
R59 0_0402_5%R59 0_0402_5%
1 2
C86
1U_0402_6.3V4Z
C86
1U_0402_6.3V4Z
1
2
R45 140_0402_1%
UMA@
R45 140_0402_1%
UMA@ 1 2
L9
MBK2012221YZF 0805
L9
MBK2012221YZF 0805
1 2
R49 150_0402_1%
UMA@
R49 150_0402_1%
UMA@ 1 2
L59
MBK2012221YZF 0805
L59
MBK2012221YZF 0805
1 2
C645
2.2U_0603_6.3V4Z
C645
2.2U_0603_6.3V4Z
1
2
R293
4.7K_0402_5%
R293
4.7K_0402_5%
1 2
C61
2.2U_0603_6.3V4Z
C61
2.2U_0603_6.3V4Z
1
2
L56
MBC1608121YZF_0603
L56
MBC1608121YZF_0603
1 2
R489 0_0402_5%UMA@R489 0_0402_5%UMA@
1 2
C665
1U_0402_6.3V4Z
C665
1U_0402_6.3V4Z
1
2
R488 0_0402_5%UMA@R488 0_0402_5%UMA@
1 2
R42 715_0402_1%R42 715_0402_1%1 2
C663
1U_0402_6.3V4Z
C663
1U_0402_6.3V4Z
1
2
R492 0_0402_5%@R492 0_0402_5%@
1 2
R758 0_0402_5%@R758 0_0402_5%@
1 2
U48
NC7SZ08P5X_NL_SC70-5
@
U48
NC7SZ08P5X_NL_SC70-5
@
B2
A1
Y 4
P5G3
L10
FBM-L11-201209-300LMA30T_0805
L10
FBM-L11-201209-300LMA30T_0805
1 2
C94
2.2U_0603_6.3V4Z
C94
2.2U_0603_6.3V4Z
1
2
R289 4.7K_0402_5%R289 4.7K_0402_5%1 2
R290
4.7K_0402_5%
R290
4.7K_0402_5%
1 2
L15
FBM-L11-201209-300LMA30T_0805
L15
FBM-L11-201209-300LMA30T_0805
1 2
U49
NC7SZ08P5X_NL_SC70-5
UMA@
U49
NC7SZ08P5X_NL_SC70-5
UMA@
B2
A1
Y 4
P5G3
L12
MBC1608121YZF_0603
L12
MBC1608121YZF_0603
1 2
L14
MBK2012221YZF 0805
L14
MBK2012221YZF 0805
1 2
PART 3 OF 6
PMCLOCKsPLLPWR
MIS.
CRT/TVOUT
LVTM
U3C
RS780M_FCBGA528
PART 3 OF 6
PMCLOCKsPLLPWR
MIS.
CRT/TVOUT
LVTM
U3C
RS780M_FCBGA528
VDDA18HTPLLH17
SYSRESETbD8
POWERGOODA10
LDTSTOPbC10
ALLOW_LDTSTOPC12
REFCLK_P/OSCIN(OSCIN)E11
PLLVDD(NC)A12
HPD(NC) D10
DDC_CLK0/AUX0P(NC)A8
DDC_DATA0/AUX0N(NC)B8
THERMALDIODE_P AE8
THERMALDIODE_N AD8
I2C_CLKB9
STRP_DATAB10
GFX_REFCLKPT2
GFX_REFCLKNT1
GPP_REFCLKPU1
GPP_REFCLKNU2
PLLVDD18(NC)D14
PLLVSS(NC)B12
TXOUT_L0P(NC) A22
TXOUT_L0N(NC) B22
TXOUT_L1P(NC) A21
TXOUT_L1N(NC) B21
TXOUT_L2P(NC) B20
TXOUT_L2N(DBG_GPIO0) A20
TXOUT_L3P(NC) A19
TXOUT_U0P(NC) B18
TXOUT_L3N(DBG_GPIO2) B19
TXOUT_U0N(NC) A18
TXOUT_U1P(PCIE_RESET_GPIO3) A17
TXOUT_U1N(PCIE_RESET_GPIO2) B17
TXOUT_U2P(NC) D20
TXOUT_U2N(NC) D21
TXOUT_U3P(PCIE_RESET_GPIO5) D18
TXOUT_U3N(NC) D19
TXCLK_LP(DBG_GPIO1) B16
TXCLK_LN(DBG_GPIO3) A16
TXCLK_UP(PCIE_RESET_GPIO4) D16
TXCLK_UN(PCIE_RESET_GPIO1) D17
VDDLTP18(NC) A13
VSSLTP18(NC) B13
C_Pr(DFT_GPIO5)E17
Y(DFT_GPIO2)F17
COMP_Pb(DFT_GPIO4)F15
RED(DFT_GPIO0)G18
TMDS_HPD(NC) D9I2C_DATAA9
TESTMODE D13
HT_REFCLKNC24
HT_REFCLKPC25
SUS_STAT#(PWM_GPIO5) D12
GREEN(DFT_GPIO1)E18
BLUE(DFT_GPIO3)E19
DAC_VSYNC(PWM_GPIO6)B11
DAC_HSYNC(PWM_GPIO4)A11
DAC_RSET(PWM_GPIO1)G14
AVDD1(NC)F12
AVDD2(NC)E12
REDb(NC)G17
GREENb(NC)F18
AVDDDI(NC)F14
AVSSDI(NC)G15
AVDDQ(NC)H15
AVSSQ(NC)H14
VDDLT18_2(NC) B15
VDDLT33_1(NC) A14
VDDLT33_2(NC) B14
VSSLT1(VSS) C14
VSSLT2(VSS) D15
VDDLT18_1(NC) A15
VSSLT3(VSS) C16
VSSLT4(VSS) C18
VSSLT5(VSS) C20
LVDS_DIGON(PCE_TCALRP) E9
LVDS_BLON(PCE_RCALRP) F7
LVDS_ENA_BL(PWM_GPIO2) G12
VSSLT6(VSS) E20
VDDA18PCIEPLL1D7
VDDA18PCIEPLL2E7
BLUEb(NC)F19
AUX_CAL(NC)C8
GPPSB_REFCLKP(SB_REFCLKP)V4
GPPSB_REFCLKN(SB_REFCLKN)V3
DDC_DATA1/AUX1N(NC)A7
DDC_CLK1/AUX1P(NC)B7
DAC_SCL(PCE_RCALRN)F8
DAC_SDA(PCE_TCALRN)E8
REFCLK_N(PWM_GPIO3)F11
VSSLT7(VSS) C22
RSVDG11
R469
1.27K_0402_1%
@
R469
1.27K_0402_1%
@
12
R29
1.27K_0402_1%
UMA@
R29
1.27K_0402_1%
UMA@
12
R288 10K_0402_5%
@
R288 10K_0402_5%
@ 12
R50 150_0402_1%
UMA@
R50 150_0402_1%
UMA@ 1 2
R296 0_0402_5%R296 0_0402_5%
1 2
C857 0.1U_0402_16V4ZC857 0.1U_0402_16V4Z
C74
0.1U_0402_16V4Z
C74
0.1U_0402_16V4Z
1
2
R60
300_0402_5%
R60
300_0402_5%
12
R297 0_0402_5%R297 0_0402_5%
1 2
C644
2.2U_0603_6.3V4Z
C644
2.2U_0603_6.3V4Z
1
2
C66
2.2U_0603_6.3V4Z
C66
2.2U_0603_6.3V4Z
1
2
R279
1.8K_0402_5%
R279
1.8K_0402_5%
1 2
C72
1U_0402_6.3V4Z
C72
1U_0402_6.3V4Z
1
2
R295 4.7K_0402_5%R295 4.7K_0402_5%1 2
R280
0_0402_5%
R280
0_0402_5%
1 2
C95
4.7U_0805_10V4Z
C95
4.7U_0805_10V4Z
1
2
R283 300_0402_5%R283 300_0402_5%
12
R477
100_0402_5%
@
R477
100_0402_5%
@
12
L13
MBK2012221YZF 0805
L13
MBK2012221YZF 0805
1 2
hexainf@hotmail.com
12. A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+VDDA11PCIE
+VDDHTTX
+VDDHT
+VDDA18PCIE
+VDDHTRX
+1.8V_VDD_SP
+1.1VS
+1.8VS
+1.8VS
+1.2V_HT
+1.1VS
+3VS
+NB_CORE+1.1VS
+1.8VS
+1.8VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
12 49Monday, May 04, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
12 49Monday, May 04, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
12 49Monday, May 04, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
FOR Version A11 pop 1.35VS A12
use 1.2V_HT
VDDHTTX=0.68A
VDDA18PCIE=0.7A
VDDPCIE=1.1A
VDDC=7.6A
VDD33=60mA
VDDHTRX+VDDHT=0.68A
VDD18=10mA
DVT
VDD_MEM=70mA
VDD18_MEM=25mA
C340.1U_0402_16V4ZC340.1U_0402_16V4Z
1
2
C80
0.1U_0402_16V4Z
C80
0.1U_0402_16V4Z
1
2
R223
0_0402_5%
VGA@
R223
0_0402_5%
VGA@
12
L4
FBMA-L11-201209-221LMA30T_0805
L4
FBMA-L11-201209-221LMA30T_0805
12
C810.1U_0402_16V4ZC810.1U_0402_16V4Z
1
2C45
10U_0805_10V4Z
C45
10U_0805_10V4Z
1
2
C51
0.1U_0402_16V4Z
C51
0.1U_0402_16V4Z
1
2
C680.1U_0402_16V4ZC680.1U_0402_16V4Z
1
2
C599 0.1U_0402_16V4ZSP@C599 0.1U_0402_16V4ZSP@12
C54
0.1U_0402_16V4Z
C54
0.1U_0402_16V4Z
1
2
C85
0.1U_0402_16V4Z
C85
0.1U_0402_16V4Z
1
2
C430.1U_0402_16V4ZC430.1U_0402_16V4Z
1
2
C3610U_0603_6.3V6MC3610U_0603_6.3V6M
1
2
C53 1U_0402_6.3V4ZC53 1U_0402_6.3V4Z1 2
L3
FBMA-L11-201209-221LMA30T_0805
L3
FBMA-L11-201209-221LMA30T_0805
1 2
C89
1U_0402_6.3V4Z
C89
1U_0402_6.3V4Z
1
2
C597 0.1U_0402_16V4ZSP@C597 0.1U_0402_16V4ZSP@12
C760.1U_0402_16V4ZC760.1U_0402_16V4Z
1
2
C248 0.1U_0402_16V4ZSP@C248 0.1U_0402_16V4ZSP@12
C31
4.7U_0805_10V4Z
C31
4.7U_0805_10V4Z
1
2
C249 4.7U_0805_10V4ZSP@C249 4.7U_0805_10V4ZSP@12
C29 4.7U_0805_10V4ZC29 4.7U_0805_10V4Z1 2
C48
0.1U_0402_16V4Z
C48
0.1U_0402_16V4Z
1
2
C30 10U_0603_6.3V6MC30 10U_0603_6.3V6M1 2
C92
1U_0402_6.3V4Z
SP@
C92
1U_0402_6.3V4Z
SP@
1
2
R224 0_0402_5%SP@R224 0_0402_5%SP@
1 2
L5
FBMA-L11-201209-221LMA30T_0805
L5
FBMA-L11-201209-221LMA30T_0805
12
C71
0.1U_0402_16V4Z
C71
0.1U_0402_16V4Z
1
2
L6 0_1206_5%@L6 0_1206_5%@
1 2
C79 1U_0402_6.3V4ZC79 1U_0402_6.3V4Z1 2
C82
0.1U_0402_16V4Z
C82
0.1U_0402_16V4Z
1
2
C78
0.1U_0402_16V4Z
C78
0.1U_0402_16V4Z
1
2
+
C27330U_D2E_2.5VM_R9MUMA@
+
C27330U_D2E_2.5VM_R9MUMA@
1
2
L49
FBMA-L11-201209-221LMA30T_0805
L49
FBMA-L11-201209-221LMA30T_0805
12
C73
0.1U_0402_16V4Z
C73
0.1U_0402_16V4Z
1
2
C47
4.7U_0805_10V4Z
C47
4.7U_0805_10V4Z
1
2
C40
0.1U_0402_16V4Z
C40
0.1U_0402_16V4Z
1
2
C75
0.1U_0402_16V4Z
C75
0.1U_0402_16V4Z
1
2
C612
4.7U_0805_10V4Z
C612
4.7U_0805_10V4Z
1
2
C690.1U_0402_16V4ZC690.1U_0402_16V4Z
1
2
C640.1U_0402_16V4ZC640.1U_0402_16V4Z
1
2
C28 10U_0603_6.3V6MC28 10U_0603_6.3V6M1 2
L11
FBMA-L11-201209-221LMA30T_0805
L11
FBMA-L11-201209-221LMA30T_0805
12
C62
1U_0402_6.3V4Z
C62
1U_0402_6.3V4Z
1
2
PART 6/6
GROUND
U3F
RS780M_FCBGA528
PART 6/6
GROUND
U3F
RS780M_FCBGA528
VSSAHT1A25
VSSAHT2D23
VSSAHT3E22
VSSAHT4G22
VSSAHT5G24
VSSAHT6G25
VSSAHT7H19
VSSAHT8J22
VSSAHT9L17
VSSAHT10L22
VSSAHT11L24
VSSAHT12L25
VSSAHT13M20
VSSAHT14N22
VSSAHT15P20
VSSAHT16R19
VSSAHT17R22
VSSAHT18R24
VSSAHT19R25
VSSAHT21U22
VSSAHT22V19
VSSAHT23W22
VSSAHT24W24
VSSAHT25W25
VSSAHT26Y21
VSSAHT27AD25
VSS2 D11
VSS3 G8
VSS4 E14
VSS5 E15
VSS7 J12
VSS8 K14
VSS9 M11
VSS10 L15
VSS11L12
VSS12M14
VSS13N13
VSS14P12
VSS15P15
VSS16R11
VSS17R14
VSS18T12
VSS19U14
VSS20U11
VSS21U15
VSS22V12
VSS23W11
VSS24W15
VSS25AC12
VSS26AA14
VSS27Y18
VSS28AB11
VSS29AB15
VSS30AB17
VSS31AB19
VSS32AE20
VSSAPCIE1 A2
VSSAPCIE2 B1
VSSAPCIE3 D3
VSSAPCIE4 D5
VSSAPCIE5 E4
VSSAPCIE6 G1
VSSAPCIE7 G2
VSSAPCIE8 G4
VSSAPCIE9 H7
VSSAPCIE10 J4
VSSAPCIE11 R7
VSSAPCIE12 L1
VSSAPCIE13 L2
VSSAPCIE14 L4
VSSAPCIE15 L7
VSS34K11
VSSAPCIE16 M6
VSSAPCIE17 N4
VSSAPCIE18 P6
VSSAPCIE19 R1
VSSAPCIE20 R2
VSSAPCIE21 R4
VSSAPCIE22 V7
VSSAPCIE23 U4
VSSAPCIE24 V8
VSSAPCIE25 V6
VSSAPCIE26 W1
VSSAPCIE27 W2
VSSAPCIE28 W4
VSSAPCIE29 W7
VSSAPCIE30 W8
VSSAPCIE31 Y6
VSSAPCIE32 AA4
VSSAPCIE33 AB5
VSSAPCIE34 AB1
VSSAPCIE35 AB7
VSSAPCIE36 AC3
VSSAPCIE37 AC4
VSSAPCIE38 AE1
VSSAPCIE39 AE4
VSSAPCIE40 AB2
VSS1 AE14
VSSAHT20H20
VSS33AB21
VSS6 J15
C4410U_0603_6.3V6MC4410U_0603_6.3V6M
1
2
PART 5/6
POWER
U3E
RS780M_FCBGA528
PART 5/6
POWER
U3E
RS780M_FCBGA528
VDDHT_1J17
VDDHT_2K16
VDDHT_3L16
VDDHT_4M16
VDDHT_5P16
VDDHT_6R16
VDDHT_7T16
VDDHTTX_1AE25
VDDHTTX_2AD24
VDDHTTX_3AC23
VDDHTTX_4AB22
VDDHTTX_5AA21
VDDHTTX_6Y20
VDDHTTX_7W19
VDDHTTX_8V18
VDDHTRX_1H18
VDDHTRX_2G19
VDDHTRX_3F20
VDDHTRX_4E21
VDDHTRX_5D22
VDD18_1F9
VDD18_2G9
VDD18_MEM1(NC)AE11
VDD18_MEM2(NC)AD11
VDDA18PCIE_1J10
VDDA18PCIE_2P10
VDDA18PCIE_3K10
VDDA18PCIE_10Y9
VDDA18PCIE_11AA9
VDDA18PCIE_12AB9
VDDA18PCIE_13AD9
VDDA18PCIE_14AE9
VDDA18PCIE_6W9
VDDA18PCIE_7H9
VDDPCIE_1 A6
VDDPCIE_2 B6
VDDPCIE_3 C6
VDDPCIE_4 D6
VDDPCIE_5 E6
VDDPCIE_6 F6
VDDPCIE_7 G7
VDDPCIE_8 H8
VDDPCIE_9 J9
VDDA18PCIE_4M10
VDDA18PCIE_5L10
VDDC_1 K12
VDDC_2 J14
VDDC_3 U16
VDDPCIE_11 M9
VDDC_4 J11
VDDC_5 K15
VDDPCIE_10 K9
VDDC_6 M12
VDDC_7 L14
VDDC_8 L11
VDDC_9 M13
VDDC_10 M15
VDDC_11 N12
VDDC_12 N14
VDDC_13 P11
VDDC_14 P13
VDDC_15 P14
VDDC_16 R12
VDDC_17 R15
VDDC_18 T11
VDDC_19 T15
VDDC_20 U12
VDDC_21 T14
VDD33_1(NC) H11
VDD33_2(NC) H12
VDD_MEM1(NC) AE10
VDD_MEM2(NC) AA11
VDD_MEM3(NC) Y11
VDD_MEM4(NC) AD10
VDD_MEM6(NC) AC10
VDD_MEM5(NC) AB10
VDDA18PCIE_8T10
VDDC_22 J16
VDDPCIE_12 L9
VDDA18PCIE_9R10
VDDPCIE_13 P9
VDDPCIE_14 R9
VDDPCIE_15 T9
VDDPCIE_16 V9
VDDPCIE_17 U9
VDDA18PCIE_15U10
VDDHTRX_6B23
VDDHTRX_7A23
VDDHTTX_9U17
VDDHTTX_10T17
VDDHTTX_11R17
VDDHTTX_12P17
VDDHTTX_13M17
C52
1U_0402_6.3V4Z
C52
1U_0402_6.3V4Z
1
2
C49
0.1U_0402_16V4Z
C49
0.1U_0402_16V4Z
1
2
R407 0_0603_5%SP@R407 0_0603_5%SP@
12
C50
0.1U_0402_16V4Z
C50
0.1U_0402_16V4Z
1
2
C600.1U_0402_16V4ZC600.1U_0402_16V4Z
1
2
L7 0_1206_5%@L7 0_1206_5%@
1 2
C598 0.1U_0402_16V4ZSP@C598 0.1U_0402_16V4ZSP@12
C350.1U_0402_16V4ZC350.1U_0402_16V4Z
1
2
C83
4.7U_0805_10V4Z
C83
4.7U_0805_10V4Z
1
2 C88 0.1U_0402_16V4ZC88 0.1U_0402_16V4Z
1 2
C91
1U_0402_6.3V4Z
C91
1U_0402_6.3V4Z
1
2
R406 0_0603_5%VGA@R406 0_0603_5%VGA@
12
C57 0.1U_0402_16V4ZC57 0.1U_0402_16V4Z
1 2
13. A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+MEM_VREF +MEM_VREF1
MEM_A9
MEM_A2
MEM_DQ10
MEM_ODT
MEM_DQS_N0
+MEM_VREF
MEM_DQS_P0
MEM_DM1
MEM_DQS_P1
MEM_DQS_N1
MEM_DQ14
MEM_DQ7
MEM_CLKP
MEM_A8
MEM_DQ12
MEM_A1
MEM_DQ4
MEM_DQ1
MEM_DQ11
MEM_DQ6
MEM_DQ0
MEM_DQ5
MEM_DQ2
MEM_A11
MEM_A4
MEM_CLKN
MEM_DQ15
MEM_CAS#
MEM_CS#
MEM_DM0
MEM_WE#
MEM_RAS#
MEM_CKE
MEM_BA0
MEM_A7
MEM_DQ13
MEM_A10
MEM_A0
MEM_BA2
MEM_DQ8
MEM_A3
MEM_A6
MEM_BA1
MEM_DQ9
MEM_DQ3
MEM_A5
MEM_A12
MEM_DQS_P0
MEM_DQS_P1
MEM_DQS_N0
MEM_DQS_N1
MEM_DM1
MEM_DM0
+MEM_VREF1
MEM_DQ2
MEM_DQ0
MEM_DQ1
MEM_DQ3
MEM_DQ10
MEM_DQ7
MEM_DQ11
MEM_DQ8
MEM_DQ5
MEM_DQ6
MEM_DQ9
MEM_DQ15
MEM_DQ13
MEM_DQ14
MEM_DQ4
MEM_DQ12MEM_A12
MEM_A2
MEM_A0
MEM_A3
MEM_BA0
MEM_CS#
MEM_WE#
MEM_CKE
MEM_BA1
MEM_BA2
MEM_CAS#
MEM_RAS#
MEM_ODT
MEM_CLKN
MEM_CLKP
MEM_A10
MEM_A9
MEM_A8
MEM_A11
MEM_A6
MEM_A1
MEM_A4
MEM_A7
MEM_A5
MEM_COMP_N
MEM_COMP_P
GMCH_CRT_VSYNC<11,23>
AUX_CAL<11>
SUS_STAT_R#<11> PLT_RST# <11,14,24,31,33>
GMCH_CRT_HSYNC<11,23>
+3VS
+3VS
+1.8VS+1.8V_MEM_VDDQ
+1.8V_MEM_VDDQ+1.8V_MEM_VDDQ
+1.8V_MEM_VDDQ
+1.8V_MEM_VDDQ
+1.8VS
+1.1VS
+1.8V_MEM_VDDQ
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
13 49Monday, May 04, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
13 49Monday, May 04, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
Custom
13 49Monday, May 04, 2009
2008/10/06 2009/10/06
Compal Electronics, Inc.
Enables the Test Debug Bus using GPIO. (VSYNC)
1 : Disable (RS780)
0 : Enable (Rs780)
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb
Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT
DFT_GPIO1: LOAD_EEPROM_STRAPS
RS780 DFT_GPIO1
RS780 use HSYNC to enable SIDE PORT
RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)
0. Enable (RS780)
1 : Disable(RS780)
RS780 use HSYNC to enable SIDE PORT
26mA
15mA
+1.1VS=W/S=20/10mil For Memory PLL power
+1.8VS=W/S=20/10mil For Memory PLL power
220 ohm @ 100MHz,2A
03/16 SA000031O00 S IC D2 64M16/500 K4N1G164QE-HC20 FBGA84
Layout Note: 50 mil for VSSDL
Support 8M x 16bit x 8 bank side port
03/16 SA00002UH00 S IC D2 64M16/500 H5PS1G63EFR-20L FBGA84
C628
1U_0402_6.3V4Z
SP@
C628
1U_0402_6.3V4Z
SP@
1
2
R284 150_0402_1%@R284 150_0402_1%@
1 2
R1191K_0402_1%
SP@
R1191K_0402_1%
SP@12
L22
FBMA-L11-160808-221LMT 0603
L22
FBMA-L11-160808-221LMT 0603
12
C200
0.1U_0402_16V4Z
SP@
C200
0.1U_0402_16V4Z
SP@
1
2
R282 3K_0402_5%SP@R282 3K_0402_5%SP@
12
D29
CH751H-40_SC76@
D29
CH751H-40_SC76@
2 1
R120
1K_0402_1%
SP@
R120
1K_0402_1%
SP@
12
R1181K_0402_1%
SP@
R1181K_0402_1%
SP@12
R136 40.2_0402_1%SP@R136 40.2_0402_1%SP@
12
R135
100_0402_1%
SP@
R135
100_0402_1%
SP@
12
C197
0.1U_0402_16V4Z
SP@
C197
0.1U_0402_16V4Z
SP@
1
2
C201
0.1U_0402_16V4Z
SP@
C201
0.1U_0402_16V4Z
SP@
1
2
C183
2.2U_0603_6.3V4Z
SP@
C183
2.2U_0603_6.3V4Z
SP@
1
2
C207
0.1U_0402_16V4Z
SP@C207
0.1U_0402_16V4Z
SP@
1
2
L23
FBMA-L11-160808-221LMT 0603
SP@ L23
FBMA-L11-160808-221LMT 0603
SP@ 12
R117
1K_0402_1%
SP@
R117
1K_0402_1%
SP@
12
R281 3K_0402_5%VGA@R281 3K_0402_5%VGA@
12
C626
1U_0402_6.3V4Z
SP@
C626
1U_0402_6.3V4Z
SP@
1
2
C185
2.2U_0603_6.3V4Z
SP@
C185
2.2U_0603_6.3V4Z
SP@
1
2
L21
FBMA-L11-160808-221LMT 0603
L21
FBMA-L11-160808-221LMT 0603
12
C208
22U_0805_6.3V6M
SP@
C208
22U_0805_6.3V6M
SP@
1
2
R287 3K_0402_5%@R287 3K_0402_5%@
12
SBD_MEM/DVO_I/F
PAR 4 OF 6
U3D
RS780M_FCBGA528
SBD_MEM/DVO_I/F
PAR 4 OF 6
U3D
RS780M_FCBGA528
MEM_A0(NC)AB12
MEM_A1(NC)AE16
MEM_A2(NC)V11
MEM_A3(NC)AE15
MEM_A4(NC)AA12
MEM_A5(NC)AB16
MEM_A6(NC)AB14
MEM_A7(NC)AD14
MEM_A8(NC)AD13
MEM_A9(NC)AD15
MEM_A10(NC)AC16
MEM_A11(NC)AE13
MEM_A12(NC)AC14
MEM_A13(NC)Y14
MEM_BA0(NC)AD16
MEM_BA1(NC)AE17
MEM_BA2(NC)AD17
MEM_RASb(NC)W12
MEM_CASb(NC)Y12
MEM_WEb(NC)AD18
MEM_CSb(NC)AB13
MEM_CKE(NC)AB18
MEM_ODT(NC)V14
MEM_CKP(NC)V15
MEM_CKN(NC)W14
MEM_DM0(NC) W17
MEM_DM1/DVO_D8(NC) AE19
MEM_DQS0P/DVO_IDCKP(NC) Y17
MEM_DQS0N/DVO_IDCKN(NC) W18
MEM_DQS1P(NC) AD20
MEM_DQS1N(NC) AE21
MEM_DQ0/DVO_VSYNC(NC) AA18
MEM_DQ1/DVO_HSYNC(NC) AA20
MEM_DQ2/DVO_DE(NC) AA19
MEM_DQ3/DVO_D0(NC) Y19
MEM_DQ4(NC) V17
MEM_DQ5/DVO_D1(NC) AA17
MEM_DQ6/DVO_D2(NC) AA15
MEM_DQ7/DVO_D4(NC) Y15
MEM_DQ8/DVO_D3(NC) AC20
MEM_DQ9/DVO_D5(NC) AD19
MEM_DQ10/DVO_D6(NC) AE22
MEM_DQ11/DVO_D7(NC) AC18
MEM_DQ12(NC) AB20
MEM_DQ13/DVO_D9(NC) AD22
MEM_DQ14/DVO_D10(NC) AC22
MEM_DQ15/DVO_D11(NC) AD21
MEM_COMPP(NC)AE12
MEM_COMPN(NC)AD12 MEM_VREF(NC) AE18
IOPLLVDD18(NC) AE23
IOPLLVSS(NC) AD23
IOPLLVDD(NC) AE24
R286 3K_0402_5%R286 3K_0402_5%
12
C206
0.1U_0402_16V4Z
SP@
C206
0.1U_0402_16V4Z
SP@
1
2
C195
0.1U_0402_16V4Z
SP@C195
0.1U_0402_16V4Z
SP@
1
2
C184
1U_0402_6.3V4Z
SP@C184
1U_0402_6.3V4Z
SP@
1
2
L16 0_0805_5%SP@L16 0_0805_5%SP@
1 2
R140 40.2_0402_1%SP@R140 40.2_0402_1%SP@
12
R299 3K_0402_5%@R299 3K_0402_5%@
12
U61
HY5PS561621AFP-25_FBGA84
@
U61
HY5PS561621AFP-25_FBGA84
@
VREFJ2
LDMF3
UDMB3
DQ14 B1
DQ13 D9
DQ12 D1
DQ11 D3
DQ10 D7
DQ9 C2
DQ8 C8
DQ7 F9
DQ6 F1
DQ5 H9
DQ4 H1
DQ3 H3
DQ2 H7
DQ1 G2
DQ0 G8
BA1L3
BA0L2
A11P7
A10/APM2
A9P3
A8P8
A7P2
A6N7
A5N3
A4N8
A3N2
A0M8
A1M3
A2M7
RASK7
CKEK2
ODTK9
CSL8
CASL7
CKJ8
CKK8
WEK3 VDDQ G9
VDDQ A9
VDDQ C1
VDDQ C3
VDDQ C7
VDDQ C9
VDDQ E9
VDDQ G1
VSSQ A7
VSSQ B2
VSSQ B8
VSSQ D2
VSSQ D8
VSSQ E7
VSSQ F2
VSSQ F8
VSSQ H2
VSSQ H8
VSS A3
VSS E3
VSS J3
VSS N1
VSS P9
UDQSA8
UDQSB7
LDQSE8
LDQSF7
VDDQ G3
VDDQ G7
VDD A1
VDD E1
VDD J9
VDD M9
VDD R1
A12R2
DQ15 B9
VDDL J1
VSSDL J7
NCR8
NCA2
NCL1
NCR3
NCR7
NCE2
hexainf@hotmail.com
14. 5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]
CLK_PCIE_VGA
CLK_PCIE_VGA#
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_P9
PEG_NRX_C_GTX_P8
PEG_NRX_C_GTX_P9
PCIE_GTX_C_MRX_P10PEG_NRX_C_GTX_P10
PCIE_GTX_C_MRX_P11PEG_NRX_C_GTX_P11
PCIE_GTX_C_MRX_P12PEG_NRX_C_GTX_P12
PCIE_GTX_C_MRX_P13PEG_NRX_C_GTX_P13
PEG_NRX_C_GTX_P14 PCIE_GTX_C_MRX_P14
PEG_NRX_C_GTX_P15 PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_N10
PEG_NRX_C_GTX_N9
PEG_NRX_C_GTX_N8
PCIE_GTX_C_MRX_N11
PEG_NRX_C_GTX_N10
PCIE_GTX_C_MRX_N12PEG_NRX_C_GTX_N12
PEG_NRX_C_GTX_N11
PEG_NRX_C_GTX_N13 PCIE_GTX_C_MRX_N13
PEG_NRX_C_GTX_N15 PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_N14PEG_NRX_C_GTX_N14
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_N0PEG_NRX_C_GTX_N0
PCIE_GTX_C_MRX_N2
PEG_NRX_C_GTX_N1
PCIE_GTX_C_MRX_N3
PEG_NRX_C_GTX_N2
PEG_NRX_C_GTX_N5
PCIE_GTX_C_MRX_N4PEG_NRX_C_GTX_N4
PEG_NRX_C_GTX_N3
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_N5
PEG_NRX_C_GTX_N6
PEG_NRX_C_GTX_N7
PCIE_GTX_C_MRX_P0PEG_NRX_C_GTX_P0
PCIE_GTX_C_MRX_P1PEG_NRX_C_GTX_P1
PCIE_GTX_C_MRX_P2PEG_NRX_C_GTX_P2
PCIE_GTX_C_MRX_P3PEG_NRX_C_GTX_P3
PCIE_GTX_C_MRX_P4PEG_NRX_C_GTX_P4
PCIE_GTX_C_MRX_P5PEG_NRX_C_GTX_P5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_P7
PEG_NRX_C_GTX_P6
PEG_NRX_C_GTX_P7
PCIE_GTX_C_MRX_P[0..15]<10>
PCIE_GTX_C_MRX_N[0..15]<10>
PCIE_MTX_C_GRX_P[0..15]<10>
PCIE_MTX_C_GRX_N[0..15]<10>
CLK_PCIE_VGA<20>
CLK_PCIE_VGA#<20>
PLT_RST#<11,13,24,31,33>
+1.1VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
14 49Monday, May 04, 2009
2007/10/11 200810/11
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
14 49Monday, May 04, 2009
2007/10/11 200810/11
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
401728 A
SCHEMATICS,MB A5401
14 49Monday, May 04, 2009
2007/10/11 200810/11
Compal Electronics, Inc.
PCIE LANE REVERSAL PCIE LANE REVERSAL
For Future ASIC Pin
N10 need pull down
ESD
For M92 S2-LP
disable PCIE GFX 0~7
C1084 0.1U_0402_16V7K
@
C1084 0.1U_0402_16V7K
@
1 2
C1077 0.1U_0402_16V7K
@
C1077 0.1U_0402_16V7K
@
1 2
C1063 0.1U_0402_16V7K
VGA@
C1063 0.1U_0402_16V7K
VGA@
1 2
C1073 0.1U_0402_16V7K
VGA@
C1073 0.1U_0402_16V7K
VGA@
1 2
R865 2K_0402_1%
VGA@
R865 2K_0402_1%
VGA@
1 2
R955
10K_0402_5%@
R955
10K_0402_5%@
12
R864 1.27K_0402_1%
VGA@
R864 1.27K_0402_1%
VGA@
1 2
C1091 0.1U_0402_16V7K
@
C1091 0.1U_0402_16V7K
@
1 2
C1074 0.1U_0402_16V7K
VGA@
C1074 0.1U_0402_16V7K
VGA@
1 2
C1083 0.1U_0402_16V7K
@
C1083 0.1U_0402_16V7K
@
1 2
C1062 0.1U_0402_16V7K
VGA@
C1062 0.1U_0402_16V7K
VGA@
1 2
C1085 0.1U_0402_16V7K
@
C1085 0.1U_0402_16V7K
@
1 2
C1068 0.1U_0402_16V7K
VGA@
C1068 0.1U_0402_16V7K
VGA@
1 2
C1067 0.1U_0402_16V7K
VGA@
C1067 0.1U_0402_16V7K
VGA@
1 2
C1078 0.1U_0402_16V7K
@
C1078 0.1U_0402_16V7K
@
1 2
C1076 0.1U_0402_16V7K
@
C1076 0.1U_0402_16V7K
@
1 2
C1069 0.1U_0402_16V7K
VGA@
C1069 0.1U_0402_16V7K
VGA@
1 2
C1080 0.1U_0402_16V7K
@
C1080 0.1U_0402_16V7K
@
1 2
C1075 0.1U_0402_16V7K
VGA@
C1075 0.1U_0402_16V7K
VGA@
1 2
C1070 0.1U_0402_16V7K
VGA@
C1070 0.1U_0402_16V7K
VGA@
1 2
C1064 0.1U_0402_16V7K
VGA@
C1064 0.1U_0402_16V7K
VGA@
1 2
C1060 0.1U_0402_16V7K
VGA@
C1060 0.1U_0402_16V7K
VGA@
1 2
PCIEXPRESSINTERFACE
CLOCK
CALIBRATION
U64A
216-0728002 A11 M92-S2_FCBGA631
VGA@
PCIEXPRESSINTERFACE
CLOCK
CALIBRATION
U64A
216-0728002 A11 M92-S2_FCBGA631
VGA@
NC#1L9
NC#2N9
NC_PWRGOODN10 PCIE_CALRN AA22
PCIE_CALRP Y22
PCIE_REFCLKNAK32
PCIE_REFCLKPAK30
PCIE_RX0NAE31
PCIE_RX0PAF30
PCIE_RX10NR31
PCIE_RX10PT30
PCIE_RX11NP28
PCIE_RX11PR29
PCIE_RX12NN31
PCIE_RX12PP30
PCIE_RX13NM28
PCIE_RX13PN29
PCIE_RX14NL31
PCIE_RX14PM30
PCIE_RX15NK30
PCIE_RX15PL29
PCIE_RX1NAD28
PCIE_RX1PAE29
PCIE_RX2NAC31
PCIE_RX2PAD30
PCIE_RX3NAB28
PCIE_RX3PAC29
PCIE_RX4NAA31
PCIE_RX4PAB30
PCIE_RX5NY28
PCIE_RX5PAA29
PCIE_RX6NW31
PCIE_RX6PY30
PCIE_RX7NV28
PCIE_RX7PW29
PCIE_RX8NU31
PCIE_RX8PV30
PCIE_RX9NT28
PCIE_RX9PU29
PERSTBAL27
PCIE_TX0N AG31
PCIE_TX0P AH30
PCIE_TX10N U23
PCIE_TX10P U24
PCIE_TX11N T27
PCIE_TX11P T26
PCIE_TX12N T23
PCIE_TX12P T24
PCIE_TX13N P26
PCIE_TX13P P27
PCIE_TX14N P23
PCIE_TX14P P24
PCIE_TX15N N26
PCIE_TX15P M27
PCIE_TX1N AF28
PCIE_TX1P AG29
PCIE_TX2N AF26
PCIE_TX2P AF27
PCIE_TX3N AD26
PCIE_TX3P AD27
PCIE_TX4N AB25
PCIE_TX4P AC25
PCIE_TX5N Y24
PCIE_TX5P Y23
PCIE_TX6N AB26
PCIE_TX6P AB27
PCIE_TX7N Y26
PCIE_TX7P Y27
PCIE_TX8N W23
PCIE_TX8P W24
PCIE_TX9N U26
PCIE_TX9P V27
C1081 0.1U_0402_16V7K
@
C1081 0.1U_0402_16V7K
@
1 2
C1089 0.1U_0402_16V7K
@
C1089 0.1U_0402_16V7K
@
1 2
C780 10P_0402_50V8J@C780 10P_0402_50V8J@
12
C1071 0.1U_0402_16V7K
VGA@
C1071 0.1U_0402_16V7K
VGA@
1 2
C1086 0.1U_0402_16V7K
@
C1086 0.1U_0402_16V7K
@
1 2
C1079 0.1U_0402_16V7K
@
C1079 0.1U_0402_16V7K
@
1 2
C1065 0.1U_0402_16V7K
VGA@
C1065 0.1U_0402_16V7K
VGA@
1 2
C1072 0.1U_0402_16V7K
VGA@
C1072 0.1U_0402_16V7K
VGA@
1 2
C1090 0.1U_0402_16V7K
@
C1090 0.1U_0402_16V7K
@
1 2
C1082 0.1U_0402_16V7K
@
C1082 0.1U_0402_16V7K
@
1 2
C1066 0.1U_0402_16V7K
VGA@
C1066 0.1U_0402_16V7K
VGA@
1 2
C1061 0.1U_0402_16V7K
VGA@
C1061 0.1U_0402_16V7K
VGA@
1 2
C1088 0.1U_0402_16V7K
@
C1088 0.1U_0402_16V7K
@
1 2
C1087 0.1U_0402_16V7K
@
C1087 0.1U_0402_16V7K
@
1 2
