1 - Al Kossow's Bitsavers

SMYOOO2.,MOS MemoryData Book1984II IIII\'h'\/ Commercial and Military, :\ Specifications '1'/!.Jf. TEXASINSTRUMENTS

Alphanumeric Index, Table of Contents, Selection GuideInterchangeability Guide _Glossary/Timing Conventions/Data Sheet StructureDynamic RAM and Memory Support DevicesDynamic RAM ModulesEPROM DevicesROM DevicesStatic RAM and Memory Support DevicesApplications InformationLogic SymbolsMechanical Data

ALPHANUMERIC INDEX TO DATA SHEETSSMJ2516SMJ2532SMJ2564SMJ2708SMJ27L08SMJ4164Page6-16-116-216-316-314-39SMJ4416 .................... 4-85SMJ5517 .................... 8-25TM4164EC4 .................. 5-1TM4164EL9 .................. 5-5TM4164FL8 .................. 5-9TMS2114 .................... 8-1TMS2114L ................... 8-1TMS2150 .................... 8-7TMS2516 .................... 6-1TMS2532 .................... 6-11TMS2564 .................... 6-21TMS2708 .................... 6-31TMS27L08 ................... 6-31TMS2732A ................... 6-47TMS2764TMS4016TMS4044TMS40L44TMS4116TMS4161TMS4164TMS4256TMS4257 .................. .TMS4416 .................. .TMS4464 .................. .TMS4500A ................. .TMS4664 .................. .TMS4732 .................. .TMS4764 .................. .TMS4964 .................. .TMS27128 ................. .TMS47128 ................ ..TMS47256 ................. .Page6-538-13 Q)"C8-19 '58-19 e,:,4-1 t:4-150'';::::;4-39 CJQ)4-63 1)C/)4-634-85 0...4-107 t:Q)4-125 ...t:7-1 0(,J7-7....7-13 0Q)7-196-61:sCO7-27 I-7-37 >

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TABLE OF CONTENTSALPHANUMERIC INDEX, TABLE OF CONTENTS, SELECTION GUIDEAlphanumeric Index to Data Sheets .................................. .Table of Contents ............................................... .RAMs, ROMs, EPROMs Selection Guide ............................... .INTERCHANGEABILITY GUIDEPart I - Alternate Vendor Part Numbering (Examples) .................. .Part II - Second Sources ........................................ .Dynamic RAMs ............................................. .Static RAMs ............................................... .EPROMs .................................................. .GLOSSARY/TIMING CONVENTIONS/DATA SHEET STRUCTUREPart I - General Concepts and Types of Memories .................... .Part II - Operating Conditions and Characteristics (Including Letter Symbols)Part III - Timing Diagrams Conventions ............................. .Part IV Basic Data Sheet Structure ............................... .DYNAMIC RAM and MEMORY SUPPORT DEVICES~ TMS4116 16,384-bit (16Kx1) ............................. .TMS4161 65,536-bit Multiport Memory ....................... .SMJ4164 65,536-bit (64K x 1) ............................. .TMS4164 65,536-bit (64K x 1) ............................. .TMS4256 262,144-bit (256K x 1) ............................ .TMS4257 262,144-bit (256K x 1) ............................. .SMJ4416 65,536-bit (16Kx4) ............................. .TMS4416 65,536-bit (16K x4) ............................. .TMS4464 262,144-bit (64K x4) ............................. .TMS4500A Dynamic RAM Controller .............................. .1-11-31-52-12-82-82-92-103-13-33-83-84-14-154-394-394-634-634-854-854-1074-125CD"CoSC!'c0o~(,)CDQ)tJ)U;....cCD....c0U'to-0CD:iscot->

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MOSLSIRAMs, ROMs, EPROMsSELECTION GUIDEWORDS1K2K4K8K16KSRAMsTMS4044BITS PER WORD1 4TMS40L44DRAMsTMS4116(4K)(16K)SRAMsTMS2114TMS2114LDRAMsTMS4416SMJ4416(4K)(64K)SRAMsTMS4016SMJ5517ROMsTMS4732ROMsTMS4664TMS4764TMS4964ROMs8EPROMsTMS2708TMS27L08SMJ2708SMJ27L08(8K)(16K)EPROMsTMS2516SMJ2516TMS2716(32K)EPROMsTMS2532SMJ2532TMS2732A(64K)EPROMsTMS2564SMJ2564TMS2764(128K)EPROMsTMS47128 TMS27128Q)"'C'S(!Jco'';:;(.)Q)Q)enu)...CQ)...CoU....oQ):cCO...>

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If you want to give it a try for yourself …• Download the code– https://github.com/fp7-ofelia/VeRTIGO/downloads• Install– https://github.com/fp7-ofelia/VeRTIGO/wiki• Generate the initial configuration for VeRTIGO (FV-like):– fvconfig generate config.xml• Create a new slice and define its flowspace:– fvctl createSlice charlie tcp:127.0.0.1:6633 charlieemail@yourhost.com– fvctl addFlowSpace any 10 any "Slice:charlie=4“• Questions? Contact Matteo Gerola (matteo.gerola (at)create-net.org)27 September 2012 WP 816/16

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INTERCHANGEABILITY GUIDEPART 1 -ALTERNATE VENDOR PART NUMBERING (EXAMPLES)TEXAS INSTRUMENTS (TI)EXAMPLE:TMSTMS Commercial MaSSMJ Military MaS2114L -45Max Access- 4 45 ns -20200 ns- 5 55 ns -25250 ns- 7 70 ns -30300 ns-10 100 ns -35350 ns-12 120 ns .-45450 ns-15 150 nst Inclusion of an "L" in the product identification indicates the device operates at low power.N(J.g,)FP Plastic Chip CarrierJCerpak/CerdipJD Side BrazeMC Chip-on-BoardN Plastic DIPELMSL-40°C to ao°cooC to 70°C-55°C to 125°C- 55°C to 100°CCI)"C·S~>-~:cCOCI)ent:CO..r:::CJ....CI)......5ADVANCED MICRO DEVICES (AMD)Am 91L28-1590 DRAM91 SRAM92 ROM17/27 EPROMMax Access-70 70 ns-10 100 ns-15 150 ns-20 200 nsAMERICAN MICROSYSTEMS, INC. (AMI)S 2364 AMax AccessA 350 nsB 250 nsTEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-1

INTERCHANGEABILITY GUIDEELECTRONIC ARRAYS, INC. (EA)EA ~A:r....(1)():rII)::sCO(1)II)g;;:;:-

INTERCHANGEABILITY GUIDEFUJITSUMB 8264MB FujitsuMBM Industry Standard. PrefixHITACHI~ ~A..::.3..-10. (s.... tn ..)Max Access-10 100 ns-12 120 ns-15 150 nsQ)"'C·SC!J>~:cCOQ)C)..cCO.s::.(,)Q)....5HM RAMHN ROMMax Access-1 Fastest-2-3-4 SlowestINMOSIMS 2600-15Max Access-45 45 ns-55 55 ns-10 100 ns-12 120 ns-15 150 nsTEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-3

INTERCHANGEABILITY GUIDEINTEL...:::lCD...C')::rDl:::lCCCDDlg;:;'-

INTERCHANGEABILITY GUIDEMOTOROLAMCM-t( IC Memory Prefix)t Inclusion of an "L" indicates low power version.NATIONAL SEMICONDUCTOR-15Max Access-10 100 ns-12 120 ns-15 150 ns. -20 200 ns-25 250 ns-30 300 ns-45 450 nsQ)"C·S~>:!::cctIQ)C)c:ctI.c(,)...Q)~.54164-15•Max Access-12 120 ns-15 150 ns.-20 200 nsOKI SEMICONDUCTOR (OKI)MSM 3764-20Max Access-12 120 ns-15 150 ns-20 200 nsTEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752652-5

INTERCHANGEABILITY GUIDENIPPON ELECTRIC CORPORATION (NEC)JLPD4164A-2..... 5"C .,('):rm~COCmg;;:;"-

INTERCHANGEABILITY GUIDETOSHIBATMM 4164VLSI TECHNOLOGYVT4500A-3(5."'1.. .. ,)Max Access-1 Fastest-2-3-4-5 Slowest-15( Sf.JR ..• ' )Max Access-15 150 ns-20 200 ns-25 250 nsCD"C'SC!)>:l::scaCDC)Cca.c(,)...CD......5TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-7

INTERCHANGEABILITY GUIDEPART II -SECOND SOURCES*"Based on available published data. (Official second sourcing agreements not necessarily implied.)All devices listed operate over the OOC to 70°C temperature range..... 5'CD...('):::rQ).:::JCCCDQ)g==t'-

INTERCHANGEABILITY GUIDESTATIC RAMSORGANIZATION4Kx1(5 V)MAX ACCESSMax Access = 450 nsTITIVENDORSECOND SOURCESAMDIntersilPART NUMBERTMS4044/TMS40L44Am4044IM7141/IM7141LIntel2141/2141LNational SCMM21411Kx4(5 V)Max Access = 450 nsTIMitsubishiMostekNECSynertekAMDEAEMM/SEMIFairchildM5T4044MK4104I'PD4104SY2141/SY2141 LTMS2114/TMS2114LAm9114E/91L14EEA2114L21142114HitachiHM472114AIntel2114A/2114AL2Kx8(5 V)Max Access = 250 nsTIMitsubishiMotorolaNational SCNECOKISynertekFairchildFujitsuMitsubishiM5L2114LMCM2114/MCM21L14MM2114/MM21 L 14I'PD2114/I'PD2114LMSM2114/MSM2114LSY2114/SY2114ATMS4016F3528MB8128M58725MostekOKIToshibaMK4802MSM2128TMM2016TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752652-9

INTERCHANGEABILITY GUIDEEPROMSORGANIZATION1Kx8(3 Supply)2KxS(3 Supply)2Kx8(5 V)4KxS(5 V)4KxS(5 V)SKxS(5 V)SKxS(5 V)16Kx8(5 V)MAX ACCESSMax Access = 450 nsMax Access = 450 nsMax Access = 450 nsMax Access = 450 nsMax Access = 450 nsMax Access = 450 nsMax Access = 450 nsMax Access = 250 nsTITITITITITITITITIVENDORSECOND SOURCESAMDFairchildFujitsuIntelMotorolaNational SCOKIMotorolaAMDFujitsuHitachiIntelMitsubishiMostekMotorolaNationalNECOKIToshibaHitachiMotorolaNationalAMDFairchildFujitsuHitachiIntelMitsubishiNECOKIToshibaMotorola.AMDFairchildFujitsuHitachiIntelMitsubishiOKIFujitsuIntel/PART NUMBERTMS270S/TMS27LOS270SF270SMBS5182708/270SLMCM270SMM270SMSM270STMS2716TMS2716/TMS27 A 16TMS25162716MBM2716HN4627162716M5L2716MK2716MCM2716/MCM27L 16MM2716/LPD2716MSM2716TMM323TMS2532HN62532MCM2532/MCM25L32MM2532TMS2732AAm2732F2732MBM2732AHN4627322732AM5L2732/LPD2732MSM2732TMM2732TMS2564MCM68764TMS2764Am27642764MBM2764HN4S27642764M5L2764MSM2764ATMS2712SMBM27128271282-10TEXASINSlRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

Alphanumeric Index, Table of Contents, Selection GuideInterchangeability GuideGlossary/Timing Conventions/Data Sheet StructureDynamic .RAM and Memory Support DevicesDynamic RAM ModulesEPROM Devices ..ROM DevicesStatic RAM and Memory Support DevicesApplication$ Information ..Logic SymbolsMechanical Data

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GLOSSARY fTIMING CONVENTIONS/DATA SHEET STRUCTUREPART 1-GENERAL CONCEPTS AND TYPES OF MEMORIESAddress -Any given memory location in which data can be stored or from which it can be retrieved.Automatic Chip-Select/Power Down -(see Chip Enable Input)Bit -Byte -Contraction of Binary digiT, i.e., a 1 or a 0; in electrical terms the value of a bit may be represented by the presence orabsence of charge, voltage, or current.A word of 8 bits (see word)Chip Enable Input - A control input to an integrated circuit that when active permits operation of the integrated circuit for input,internal transfer, manipulation, refreshing, andlor output of data and when inactive causes the integrated .circuit tobe in a reduced power standby mode.Chip Select Input - Chip select inputs are gating inputs that control the input to and output from the memory. They may beof two kinds:1. Synchronous - Clockedllatched with the memory clock. Affects the inputs and outputs for the duration ofthat memory cycle.2. Asynchronous - Has direct asynchronous control of inputs and outputs. In the read mode, an asynchronouschip select functions like an output enable.Column Address Strobe (CAS) - A clock used in dynamic RAMs to control the input of column addresses. It can be activehigh (CAS) or active low (CAS).Data -Any information stored or retrieved from a memory device.Dynamic (Read/Write) Memory (DRAM) - A readlwrite memory in which the cells require the repetitive application of controlsignals in order to retain the stored data.NOTES: 1 . The words "read/write" may be omitted from the term when no misunderstanding will result.2. Such repetitive application of the control signals is normally called a refresh operation.3. A dynamic memory may use static addressing or sensing circuits.4. This definition applies whether the control Signals are generated inside or outside the integrated circuit.Electrically Alterable Read-Only Memory (EAROM) - A nonvolatile memory that can be field-programmed like a PROM orEPROM, but that can be electrically erased by a combination of electrical signals at its inputs.Erasable and Programmable Read-Only Memory (EPROM)/Reprogrammable Read-Only Memory - A field-programmableread-only memory that can have the data content of each memory cell altered more than once.Erase - Typically associated with EPROMs and EAROMs. The procedure whereby programmed data is removed and the .device returns to its unprogrammed state.Field-Programmable Read-Only Memory - A read-only memory that after being manufactured, can have the data content ofeach memory cell altered.Fixed Memory - A common term for ROMs, EPROMs, EAROMs, etc., containing data that is not normally changed. A moreprecise term for EPROMs and EAROMs is nonvolatile since their data may be easily changed.Q)...::::J...CJ::::J...en...Q)Q).cenCO...COcenco'';::;cQ)>CoUt:nc'Ei=-> ...CO(/)(/)oaFully Static RAM - In a fully static RAM, the periphery as well as the memory array is fully static. The periphery is thusalways active and ready to respond to input changes without the need for clocks. There is no precharge required forstatic periphery.K -When used in the context of specifying a given number of bits of information, 1 K = 210 = 1024 bits. Thus,64K = 64 X 1024 = 65,536 bits.Large-Scale Integration (LSI) - The description of any IC technology that enables condensing more than 100 gates onto asingle chip.TEXAS INSTRUMENTSINCORPORATED3-1POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

GLOSSARY/TIMING CONVENTIONS/DATA SHEET STRUCTUREMask-Programmed Read-Only Memory - A read-only memory in which the data content of each cell is determined duringmanufacture by the use of a mask. the data content thereafter being unalterable.Memory - A medium capable of storage of information from which the information can be retrieved.Memory Cell - The smallest subdivision of a memory into which a unit of data has been or can be entered. in which it is orcan be stored. and from which it can be retrieved.Metal-Oxide Semiconductor (MOS) -semiconductor device.The technology involving photolithographic layering of metal and oxide to produce aNMOS - A type of MOS technology in which the basic conduction mechanism is governed by electrons. (Short forN-channel MOS)G)5"enenQ)-

GLOSSARY/TIMING CONVENTIONS/DATA SHEET STRUCTUREVery-Large-Scale Integration (VLS!) - The description of any IC technology that is much more complex than large-scale integration(LSI), and involves a much higher equivalent gate count. At this time an exact definition including a minimumgate count has not been standardized by JEDEC or the IEEE.Volatile Memory -A memory in which the data content is lost when power supplied is disconnected.Word -Write -A series of one or more bits that occupy a given address location and that can be stored and retrieved in parallel.A memory operation whereby data is written into a desired address location.Write Enable - A control signal that when true causes the memory to assume the write mode, and when false causes it toassume the read mode.PART 11- OPERATING CONDITIONS AND CHARACTERISTICS (INCLUDING LETTER SYMBOLS)CapacitanceCurrentThe inherent capacitance on every pin, which can vary with various inputs and outputs.Example symbology:Ci Input capacitanceCo Output capacitanceCi(D) Input capacitance, data inputHigh-level input current, IIHThe current into an input when a high-level voltage is applied-to that input.High-level output current, 10HThe current into * an output with input conditions applied that according to the product specification will establish a·hig!;l level at the output.Low-level input current, IlLThe current into an input when a low-level voltage is applied to that input.Low-level output current, 10LThe current into * an output with input conditions applied that according to the product specification will establish alow level at the output.Off-state Ihigh-impedance-state) output current lof a three-state output), 10ZThe current into * an output having three-state capability with input conditions applied that according to the productspecification will establish the high-impedance state at the output.Short-circuit output current, lOSThe current into * an output when the output is short-circuited to ground lor other specified potential) with input conditionsapplied to establish the output logic level farthest from ground potential (or other specified potential).Supply current IBB' ICC, 100, IppThe current into, respectively, the VBB, VCC, VDD, Vpp supply terminals.Operating Free-Air TemperatureQ).....::s(.).. ::s...CJ)...Q)Q)..c:CJ)...COCOQ-enco"+:cQ)>Co(.)C)C"si=-~COeneno(5The temperature (T A) range over which the device will operate and meet the specified electrical characteristics.Operating Case TemperatureThe case temperature IT C) range over which the device will operate and meet the specified electrical characteristics." Current out of a terminal is given as a negative value.TEXAS INSTRUMENTSINCORPORATEDPOST OFFICE BOX 225012 • DALLAS, TEXAS 752653-3

GLOSSARY /TIMING CONVENTIONS/DATA SHEET STRUCTUREVoltageHigh-level input voltage, VIHAn input voltage within the more positive (less negative) of the two ranges of values used to represent the binaryvariables.NOTE:A minimum is specified that is the least positive value of high-level input voltage for which operation of thelogic element within specification limits is guaranteed.High-level output voltage, VOHThe voltage at an output terminal with input conditions applied that according to the product specification willestablish a high level at the output.C')5"C/)C/)Q)..'

GLOSSARY!TIMING CONVENTIONS/DATA SHEET STRUCTUREThe hyphen between the Band C subscripts is omitted when no confusion is likely to occur.For examples of symbols of this type, see TMS 4116 (e.g., tpLCU.Classified time Intervals (general comments, specific times follow)Because of the information contained in the definitions, frequently the identification of one or both of the two signalevents that begin and end the intervals can be significantly shortened compared to the unclassified forms. For example,it is not necessary to indicate in the symbol that an access time ends with valid data at the output. However, ifboth signals are named (e.g., in a hold time), the from-to sequence is maintained.Access timeThe time interval between the application of a specific input pulse and the availability of valid signals at an output.Example symbology:ClassifiedUnclassifiedDescriptiontalA)·tatS), ta(CS)Cycle timetAVOVtSLOVAccess time from addressAccess time from chip select (low)The time interval between the start and end of a cycle.NOTE:Example symbology:NOTE:ClassifiedThe cycle time is the actual time interval between two signal events and is determined by the system inwhich the digital circuit operates. A minimum value is specified that is the shortest interval that must beallowed for the digital circuit to perform a specified function (e.g., read, write, etc.) correctly.tc(RI, tc(rd)tc(WIUnclassifiedtAVAV(R)tAVAV(W)DescriptionRead cycle timeWrite cycle timeR is usually used as the abbreviation for "read"; however, in the case of dynamic memories, "rd" is usedto permit R to stand for RAS.Disable time (of a three-state output)The time interval between the specified reference points on the input and output voltage waveforms, with the threestateoutput changing from either of the defined active levels (high or lowl to a high-impedance (offl state.Example symbology:Classifiedtdis(S)tdis(W)UnclassifiedtSHOZtWLOZThese symbols supersede the older forms tpvz or tpXZ.Enable time (of a three-state outputlDescriptionOutput disable time after chip select (high)Output disable time after write enable (low)The time interval between the specified reference points on the input and output voltage waveforms, with the threestateoutput changing from a high-impedance (off) state to either of the defined active levels (high or low).NOTE: For memories these intervals are often classified as access times.Example symbology:Classifiedten(SL)UnclassifiedtSLOVDescriptionOutput enable time after chip select low...(1)(1).cen~...~C-t/)Co'';::;c(1)>CoUC)c'si=->...~t/)t/)o(5These symbols supercede the older form tpZV.TEXAS INSTRUMENTSINCORPORATED3-5POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

GLOSSARY/TIMING CONVENTIONS/DATA SHEET STRUCTUREHold timeThe time interval during which a signal is retained at a specified input terminal after an active transition occurs atanother specified input terminal.NOTES: 1. The hold time is the actual time interval between two signal events and is determined by the systemin which the digital circuit operates. A minimum value is specified that is the shortest interval forwhich correct operation of the digital circuit is guaranteed.2. The hold time may have a negative value in which case the minimum limit defines the longest interval(between the release of the signal and the active transition) for which correct operation of the digitalcircuit is guaranteed.Example symbology:C)5"(I)(I)Q)..

GLOSSARY/TIMING CONVENTIONS/DATA SHEET STRUCTURESetup timeThe time interval between the application of a signal at a specified input terminal and a subsequent active transition atanother specified input terminal. .NOTES: 1. The setup time is the actual time interval between two signal events and is determined by the systemin which the digital circuit operates. A minimum value is specified that is the shortest interval forwhich correct operation of the digital circuit is guaranteed.2. The setup time may have a negative value in which case the minimum limit defines the longest interval(between the active transition and the application of the other signal) for which correct operationof the digital circuit is guaranteed.Example symbology:Classifiedtsu(D)tsu(CA)tsu(RA)UnclassifiedtDVWHtCAV-CLtRAV-RLDescriptionData setup time (before write high)Column address setup time (before CAS low)Row address setup time (before RAS low)Transition times (also called rise and fall times)The time interval between two reference points (10% and 90% unless otherwise specified) on the same waveformthat is changing from the defined low level to the defined high level (rise time) or from the defined high level to thedefined low level (fall time).Example symbology:Classified Unclassified Descriptiontttt(CH)tr(C)tf(C)Valid time(a)(b)GeneraltCHCHtCHCHtCLCLTransition time (general)Low-to-high transition time of CASCAS rise timeCAS fall timeThe time interval during which a signal is (or should be) valid.Output data-valid timeThe time interval in which output data contines to be valid following a change of input conditions that couldcause the output data to change at the end of the interval.Example symbology:Classified Unclassified Descriptiontv(A) tAXQX Ou~put data valid time after change of address.This supersedes the older form tpVX....Q)::l...(,)::l...en...Q)Q)..c:enCO...COC-enco'';:::;cQ)>CoUC)c'E~-> ...COeneno(9TEXAS INSTRUMENTSINCORPORATED3-7POST OFFICE BOX 225012 • DALLAS. TEXAS 75265

GLOSSARY/TIMING CONVENTIONS/DATA SHEET STRUCTUREPART 111- TIMING DIAGRAMS CONVENTIONSTIMING DIAGRAMSYMBOLINPUTFORCING FUNCTIONSMEANINGOUTPUTRESPONSE FUNCTIONS .Must be steady high or lowHigh-to-Iow changespermittedWill be steady high or lowWill be changing from highto low some time duringdesignated intervalC')5"(I)(I)Q)...-

GLOSSARY/TIMING CONVENTIONS/DATA SHEET STRUCTUREoperation once the inputs are applied. These parameters are guaranteed for the test conditions given. The interrelationshipof the timing requirements to the switching characteristics is illustrated in timing diagrams for each type ofmemory cycle (e.g." read, write, program).At the end of a data sheet additional applications information may be provided such as how to use the device, graphsof electrical characteristics, or other data on electrical characteristics.Q)..:::l....CJ:::l....en....Q)Q).cenC'O....C'OC-(I)co'+:;cQ)>CoUC)c'E..i=->C'O(I)(I)oc:5TEXAS INSTRUMENTSINCORPORATED3-9POST OFFICE BOX 225012 • PALLAS, TEXAS 75265

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Alphanumeric Index, Table of Contents, Selection GuideInterchangeability GuideGlossary/Timing Conventions/Data Sheet StructureDynamic RAM and Memory Support DevicesDynamic RAM ModulesEPROM DevicesROM DevicesStatic RAM and Memory Support DevicesApplications InformationLogic SvmbolsMechanical Data

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MOSLSITMS411616,384-811 DYNAMIC RANDOM-ACCESS MEMORYOCTOBER 1977 - REVISED MAY 19820 16,384 X 1 Organization••10% Tolerance on All SuppliesAll Inputs Including Clocks TTL-Compatible0 Unlatched Three-State Fully TTL-CompatibleOutput•3 Performance Ranges:ACCESS ACCESS READTIME TIME ORROW COLUMN WRITEADDRESS ADDRESS CYCLE(MAX) (MAX) (MIN)TMS4116-15 150 ns 100 ns 375 nsTMS4116-20 200 ns 135 ns 375 nsTMS4116-25 250 ns 165 ns 410 ns0 Page-Mode Operation for Faster AccessTime•Common I/O Capability with "Early Write"Feature0 Low-Power Dissipation- Operating 462 mW (Max)- Standby 20 mW (Max)0 1-T Cell Design, N-Channel Silicon-GateTechnology•description16-Pin 300-Mil (7.62 mm) PackageConfigurationREAD,MODIFY-WRITEtCYCLE(MIN)375 ns375 ns515 nsTMS4116 .•• NL PACKAGE(TOP VIEW)AO-A6CASDQRASVBBVCCVDDVSSINVBBDiNRASAOA2AlVSSCASQA6A3A4A5VDD ......... __ --'"-VCCPIN NOMENCLATUREAddressesColumn Address Strobe, Data InputData OutputRow Address Strobe-5-V Power Supply+ 5-V Power Supply+ 12-V Power SupplyGroundWrite EnableThe TMS4116 series is composed of monolithic high-speed dynamic 16,384-bit MOS random-access memories organizedas 16,384 one-bit words, and employs single-transistor storage cells and N-channel silicon-gate technology.All inputs and outputs are compatible with Series 74 TTL circuits including clocks: Row Address Strobe RAS (or R)and Column Address Strobe CAS (or C). All address lines (AO through A6) and data in (D) are latched on chip to simplifysystem design. Data out (Q) is unlatched to allow greater system flexibility.Typical power dissipation is less than 350 milliwatts active and 6 milliwatts during standby (VCC is not required duringstandby operation). To retain data, only 10 milliwatts average power is required which includes the power consumedto refresh the contents of the memory.The TMS4116 series is offered in a 16-pin dual-in-line plastic (NL suffix) package and is guaranteed for operationfrom ooc to 70oe. Package is designed for insertion in mounting-hole rows on 300-mil (7.62 mm) centers.CI)Q)CJ"S;Q)C...oQ.Q.:::lUl... >-oEQ)~"t:Jc::CO~

TMS411616,384·81T DYNAMIC RANDOM·ACCESS MEMORYoperationaddress (AO through A6)Fourteen address bits are required to decode 1 of 16,384 storage cell locations. Seven row-address bits are set upon pins AO through A6 and latched onto the chip by the row-address strobe (RAS). Then the seven column-addressbits are set up on pins AO through A6 and latched onto the chip by the column-address trobe (CAS). All addressesmust be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip enable in that it activatesthe sense amplifiers as well as the row decoder. CAS is used as a chip select activating the column decoder and theinput and output buffers.write enable(W)The read or write mode is selected through the write enable (W) input. A logic high on the W input selects the readmode and a logic low selects the write mode. The write enable terminal can be driven from standard TTL circuitswithout a pull-up resistor. The data input is disabled when the read mode is selected. When W goes low prior to CAS,data-out will remain in the high-impedance state for the entire cycle permitting common 1/0 operation.c-

TMS411616,384·811 DYNAMIC RANDOM·ACCESS MEMORY,.,.Ilogic symbol tAOA1A2A3A4A5A6RAM 16K X 1(5)20D7/21DO(7)(6)(12) 0(11 )A 16383(10)(13)20D13/2106C20[ROW]RASCASIND(3)(2)A.22D23C22AV(14) Qt This symbol is in accordance with IEEE Std 91/ANSI Y32.14 and recent decisions by IEEE and lEG. See explanation on page 10-1.functional.block diagramA6A5A4A3A2A1AD--'---~ROW H~ ROWADDRESSI- ~ DECODEBUFFERS171f---7--COLUMNADDRESSBUFFERS~~""-RAS3CASR/WDSENSEAMPCONTROLROW~ DECODEAD·A6TIMING & CONTROL~----------------------------~11/21 MEMORY ARRAYDUMMY CELLS11/21 1 OF 64 COLUMN DECODE128 SENSE REFRESHAMPS11/21 1 OF 64 COLUMN DECODEDUMMY CELLS11/21 MEMORY ARRAY'---- 110upINREG._--f-- ::::~~, '""''' 10F2--f-4-~--f- 1/01/0 SELECTIODATAOUTREG.enQ)(,)':;Q)C....oc.C.:::lCJ)...>oEQ)~'CCca~c:t:a:(,)'Ecac>CTEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-3

TMS411616,384-8IT DYNAMIC RANDOM-ACCESS MEMORYabsolute maximum ratings over operating free-air temperature range (unless other~ise noted) tVoltage on any pin (see Note 1) ............................................. -0.5 V to 20 VVoltage on Vee, Voo supplies with respect to Vss ................................ -1 V to 15 VShort circuit output current ........................................................ 50 mAPower dissipation ................................................................. 1 WOperating free-air temperature range ............................................ ooe to 70 0 eStorage temperature range ................................................ - 65 °e to 150 0 et Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functionaloperation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specificationis not implied. Exposure to absolute-maximum-rated conditions for extended periods may affact device reliability.NOTE 1: Under absolute maximum ratings, voltage values are with respect to the most-negative supply voltage, Vee (substrate), unless otherwise noted.Throughout the remainder of this data sheet, voltage values are with respect to VSS'recommended operating conditionsc

1MS411616,384-811 DYNAMIC RANDOM-ACCESS MEMORYcapacitance over recommended supply voltage range and operating free-air temperature range, f1 MHzPARAMETER Typt MAX UNITCj(A) Input capacitance, address inputs 4 5 pFCj(O) Input capacitance, data input 4 5 pFCHRC) Input capacitance, strobe inputs 8 10 pFCHW) Input capacitance, write enable input 8 10 pFCo Output capacitance 5 7 pFswitching characteristics over recommended supply voltage range and operating free-air temperature rangePARAMETERTEST CONDITIONSCL = 100 pF,ALT.TMS4116-15SYMBOL MIN MAXta(C) Access time from CAS Load = 2 Series, tCAC 10074 TTL gatesta(R)tdis(GH)Access time from RASOutput disable timeafter GAS hightRLCL = MAX,CL = 100 pF,Load = 2 Series,74 TTL gatesCL = 100 pF,tRAG 150Load = 2 Series tOFF a 4074 TTL gatest All typical values are at T A = 25·C and nominal supply voltages.TMS4116-20 TMS4116-25·UNITMIN MAX MIN MAX135 165 ns200 250 nsa 50 a 60 nsCI)Q)(.)':;Q)C....oc.C.::JtJ)...>-oEQ)~"'0CCO~~a:(.)'ECOc>C.. ,'TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-5

TMS411616,384·BIT DYNAMIC RANDOM·ACCESS MEMORYtiming requirements over recommended supply voltage range and operating free-air temperature rangeo-3:C»::l0-3:CD3o ...-

TMS411616.384·81T DYNAMIC RANDOM·ACCESS MEMORYread cycle timingADDRESSESDOr tc(rd):::-it 'wIRLIII${\-__ _~I4--tCLRH~ I.-tW(RHI~I j4-t T RLCL tW(CL)---i r-tCHRL----iIf iRLC"lLVIL ---1 I4t tsu(RA) ! I j..---tW(CHI---.jI f4--th(RLCA)~ Ith(RAI --t J4-r- I I II I --t j4f-tsU(CA) Iv~: ~COLUMN ~D~N)SGOOCTEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-7

1MS411616,384·811 DYNAMIC RANDOM·ACCESS MEMORYearly write cycle timingcfI)ADDRESSES·01DOVOHVOL----------HI-Z-----------4-8TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

TMS411616,384·811 DYNAMIC RANDOM·ACCESS MEMORYwrite cycle timingADDRESSESDIDOenQ)(J'S;Q)C....oQ.Q.~rJ)...>oEQ)~"CCa:1~«0:(J'Ea:1c>Ct The enable time (ten) for a write cycle is equal in duration to the access time from CAS (ta(C)) in a read cycle; but the active levels at the output are invalid.TEXASINSTRUMENTSPOST OFFICE aox 225012 • DALLAS. TEXAS 752654-9

TMS411616,384·8IT DYNAMIC RANDOM·ACCESS MEMORYread·write/read-modify-write cycle timingc

zIiADDRESSES~!.....RASCASwDO"*. i,* V'H -=k~ 'wlRL>VILil~ - 5J =( L _i"- ~rtRLCHI r tc(P).--I I ~ tw(RH)~ ;.~ 14-tCLRH ---.I I~:I I.- 'RLCL 1-1 t-----I 'w'CHI I r- 'CHRL --I oilV'H II I r-'WICL>~ r-tr-'WICL>-: f-f ~r-'W'ClI~J=V" II· ~ ¥j jl- .fj It flth(RA) ~ I-- I ~ th(CLCA) 1 I ~ th(CLCA) I I M th(CLCA) II r ~ I I I ItSU(RA)..j~ I -+j!J-tSU(CAl I ~~tSU(CAl I --I~tSU(CA) I~,: ~o3fc3~DtNjtAd./~&ff~00

of"~I\JzI~~RASCASADDRESSESw01V,H -.,lsaO!l\aa uoddnS AJowall\l pue 11\1,,1:1 O!weuAa'wIRLI !t=k=----=-l1\VIL 1"14 tRLCH -I 1J t \.tW(RHl.j1 1 r teWl~ \4--tCLRH.-..{ II j4-tRLCL-fi \4--.I-t W (CHl I litCHRL....III I i-,wlcLI-,1 I r-'WIClI-, r-'WIClI-,~,: II ~ T1- r~ .}f'hIRAI-tI ~ I ~'hICLCAI I I h'hICLCAI I I ~th(CLCAlllI ~th(RLCAl-1 I I I I I Itsu(RAl ~'t I ~'t tsu(CAl I ~'+ tsu(CAl ,. tsu(CAl--i ~ I I I~: ~~~;s~#'t~;~~1?§~W

TMS411616,384-81T DYNAMIC RANDOM-ACCESS MEMORYRAS-only refresh timingADDRESSESDOVOHVOL------------HI-Z-------------........oc.C.::::Jen>-...oECl)~"Cr::a:I~~a:(,)'Ea:Ir::>-CTEXASINSTRUMENTSPOST OFFICE BOX 225012 • OALLAS, TEXAS 752654-13

TMS411616,384·81T DYNAMIC RANDOM·ACCESS MEMORYCYCLE RATE (& TIME) VS TEMPERATURECYCLE RATE (& TIME) VS MAX SUPPLYCURRENT. 1001Q.EGII-70~ 60GIatI~50~~otc(rd) - Cycle Time - ns3751000 500400, 300TA (MAX)2 310 3 /tc(rd) - Cycle Rate - MHz2504c:tE~f:;()>C.Q.::s(/jIXc:t~0.950mA40mA30mA20mA10mA3751000 500400 300tc(rd) - Cycle Time - ns~~";;''Y~«.,v .~+~~ ~~~?- -

MOSLSITMS416165,536-81T MULTIPORT MEMORYJULY 1983• Dual Accessability - One Port SequentialAccess, One Port Random Access• Four Cascaded 64-Bit Serial Shift Registersfor Sequential Access Applications• Shift Register Loaded Once Every 64, 128,192, or 256 Shift Cycles as Desired byUser• Fast Serial Port ... 25 MHz Shift Rate• TR/QE as Output Enable Allows Direct Connectionof D, Q and Address Lines toSimplify System Design• Random Access Port Looks Exactly Like aTMS4164• Separate Serial In and Serial Out to AllowSimultaneous Shift In and Out• 65,536 x 1 Organization• Maximum Access Time from RAS LessThan ·150 ns• Minimum Cycle Time (Read or Write) LessThan 260 ns• Long Refresh Period ... 4 Milliseconds• Low Refresh Overhead Time . . . As Low As1.6% of Total Refresh Period• All Inputs, Outputs, Clocks Fully TTLCompatible• 3-State Unlatched Outputs for Both Randomand Serial Access• Common I/O Capability with "Early Write"Feature• Page-Mode Operation for Faster Access• Low Power Dissipation (TMS4161-15)- Operating 0 •• 175 mW (Typical)- Standby 0 0 0 40 mW (Typical)• New SMOS (Scaled-MOS) N-ChannelTechnology• SOE Simplifies Multiplexing of Video DataStreamsdescriptionAO-A7CASDTMS4161 ... NL PACKAGESINSCLK(TOP VIEW)VSSSOUTTRICESOEDCASW 0RASAOA6AlA5A2A4A3VDDA7PIN NOMENCLATUREAddress InputsColumn Address StrobeRandom Access Data-In0 Random Access Data-OutRAS Row Address StrobeSCLKSINSOESOUTTA/GEINVDDVSSSerial Data ClockSerial Data-InSerial Output EnableSerial Data-OutRegister Transfer/O Output EnableWrite Enable+5-V SupplyGround• Available with MIL-STD-883B Processingand L(O °C to 70°C), E( - 40°C to 85 DC), orS( - 55°C to 100°C) Temperature Ranges inthe FutureCI)Q)(,)oSQ)C......0C.C.::len>-...0EQ)~"Cc:::CO~«ex:(,)'ECOc:::>-CThe TMS4161 is a high-speed, dual-access 65,536-bit dynamic random-access memory. The random-access portmakes the memory look like it is organized as 65,536 words of one bit each like the TMS41 ~4. The sequential accessport is interfaced to an internal 256-bit dynamic shift register organized as four 64-bit shift registers which makesthe memory look like it is organized as up to 256 words of up to 256 bits each which are accessed serially. One,PRODUCT PREVIEWThis document contalnalnfonnation on a product unde,development. Texallnstrumentl reserve. the right tochange or discontinue this product without notice.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265Copyright © 1983 by Texas Instruments Incorporated4-15

TMS416165.536·81T MULTIPORT MEMORYtwo, three, or four 64-bit shift registers can be sequentially read out depending on a two-bit code applied to the twomost significant column address inputs. The TMS4161 employs state-of-the-art SMOS (Scaled-MOS) N-channel doublelevel polysilicon gate technology for very high performance combined with low cost and improved reliability.The TMS4161 features full asynchronous dual access capability except when transferring data between the shift registerand the memory array.Refresh period is extended to 4 milliseconds, and during this period each of the 256 rows must be strobed with RASin order to retain data. CAS can remain high during the refresh seql!ence to conserve power. Note that the transferof a row of data from the memory array to the shift register also refreshes that row.All inputs and outputs, including clocks, are compatible with Series 74 TTL. All address lines and data-in are latchedon chip to simplify system design. Data-out is unlatched to allow greater system flexibility.The TMS4161 is offered in a 20-pin dual-in-line-plastic package and is guaranteed for operation from OOC to 70°C.Packages are designed for insertion in mounting-hole rows on 300-mil (7,62 mm) centers.random access address space to sequential address space mappingThe TMS4161 is designed with each row divided into four, 64-column sections. The first column section to be shiftedout is selected by the two most significant column address bits. If the two bits represent binary 00, then one to fourC registers can be shifted out in order. If the two bits represent binary 01, then only 1 to 3 (the most significant) registers~ can be shifted out in order. If the two bits represent 10, then one to two of the most significant registers 'can bem shifted out in order. Finally, if the two bits represent 11 only the most significant register can be shifted out. All registers3 are shifted out with the least significant bit (bit 0) first and the most significant bit (bit 63) last. Note that if the twon' column address bits equal 00 during the last register transfer cycle (TRInE equal to 0) a total of 256 bits can be sequentiallyread out.::al>~Q):sQ.~CI)..3o-

TMS416165,536-811 MULTIPORT MEMORYfunctional block diagram256 COLUMNS(4 GROUPS OF 64 COLUMNS),-D-- - ROW0II COL01 -fDQI~~i IQSCLKSINA6A7SOE256OWS1_ ROW255- - -COL0REG00tIIIMEMORY ARRAYf256 COLUMNS- SHIFT REGISTERS--REGREG01 I 10ICOLCOL64 ~ 128 !random access operationTR/QEThe TA/DE pin has two functions. First, it selects either register transfer or random-access operation as RAS falls,and second, if this is a random-access operation, it functions as an output enable after CAS falls.IIICOL192REG11+65.535SINr--COL25564 BITSK>--128 BITS 1 OF 4REGISTERSOUT192 BITSDECODER256 BITS+ tfI)(1)CJ"S;(1)C......00.0.::::Jen>...0E(1):;'"CCCO:;

TMS416165,536·BIT MULTIPORT MEMORY.of an overlap between data on the address lines and data appearing on the Q output making it possible to connectthe address lines to the Q and 0 lines (Use of this organization prohibits the use of the early write cycle.).address (AO through A 71Sixteen address bits are required to decode 1 of 65,536 storage cell locations. Eight row-address bits are set up onpins AO through A7 and latched onto the chip by the row-address strobe (RAS). Then the eight column-address bitsare set up on pins AO through A7 and latched onto the chip by the column-address strobe (CAS). All addresses mustbe stable on or before the falling edges of RAS and CAS. RAS is similar to a chip enable in that it activates the senseamplifiers as well as the row decoder. CAS is used as a chip select activating the column decoder and the input andoutput buffers.write enable (WIThe read or write mode is selected through the write enable (W) input. A logic high on the W input selects the readmode and a logic low selects the write mode. The write enable terminal can be driven from standard TTL circuitswithout a pull-up resistor. The data input is disabled when the read mode is selected. When W goes low prior to CAS,data-out will remain in the high-impedance state for the entire cycle permitting common 110 operation.c-

TMS416165,536-BIT MULTIPORT MEMORYsequential access operationTR/QEMemory operations involving parallel use of the shift register are first indicated by bringing TR/QE low before RASfalls low. This enables the switches connecting the 256 elements of the shift register to the 256 bit lines of the memoryarray. The W line determines whether the data will be transferred from or to the shift registers.write enable (W)In the sequential access mode, W determines whether a transfer will occur from the shift registers to the memoryarray, or from the memory array to the shift registers. To transfer from the shift registers to the memory array, Iiiis held low as RAS falls, and, to transfer from the memory array to the shift registers, W is held high as RAS falls.Thus, reads and writes are always with respect to the memory array. The write setup and hold times are referencedto the falling edge of RAS for this mode of operation.row address (AO through A 7)Eight address bits are required to select one of the 256 possible rows involved in the transfer of data to or from theshift registers. The AO-A7, W, and the TR/QE line are latched on the falling edge of RAS.register column address (A7, A6)To select one of the four shift registers (transfer from memory to register only), the appropriate 2-bit column address(A 7, A6) must be valid when CAS falls. However, the CAS and register address signals need not be supplied everycycle, only when it is desired to change or select a new register.SCLKData is shifted in and out on the rising edge of SCLK. This makes it possible to view the shift registers as thoughit were made of 256 rising edge D flip-flops connected D to Q. The TMS4161 is designed to work with a wide rangeduty cycle clock to simplify system design. Note that data will appear at the SOUT pin not only on the rising edgeof SCLK but also after an access time of ~a(RSO) from RAS high during a parallel load of the shift registers.SIN and SOUTData is shifted in through the SIN pin and is shifted out through the SOUT pin. The TMS4161 is designed such thatit requires 0 ns hold time on SIN as SCLK rises. SOUT is guaranteed not to change for at least 8 ns after SLCK rises.These features make it possible to easily connect TMS4161 s together, to allow SOUT to be connected to SIN, andto give external circuitry a full SLCK cycle time to allow manipulation of the serial data. To guarantee proper serialclock sequence after power up, a transfer cycle must be initiated before serial data is applied at SIN.SOEThe serial output enable pin controls the impedance of the serial output allowing multiplexing of more than one bankof TMS4161 memories into the same external video circuitry. When SOE is at a low logic level, SOUT will be enabledand the proper data read out. When SOE is at a high logic level, SOUT will be disabled and be in the high-impedance state.absolute maximum ratings over operating free-air temperature range (unless otherwise noted) tVoltage on any pin except VDD and data out (see Note 1)Voltage on VDD supply and data out with respect to VSS-1.5 V to 10 V-1 V to 6 VShort circuit output current ........................................................ 50 mAPower dissipation ................................................................. 1 WOperating free-air temperature range ............................................ OOC to 70°CStorage temperature range ................................................ - 65°C to 150°CenQ)(J'S;Q)C.......oc.C.:len... >oEQ)~"Cc::CO~«a:(J'sCOc::>Ct Stress beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functionaloperation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specificationis not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTE 1: All voltage values in this data sheet are with respect to VSS'TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TeXAS 752654-19

TMS416165,536·81T MUL TIPORT MEMORYrecommended operating conditionsPARAMETER MIN NOM MAX UNITSupply voltage, VOO 4.5 5 5.5 VSupply voltage, VSS 0 VHigh-level input voltage, VIH 2.4 VOO+0.3 VLow-level input voltage, VIL (see Note 2) -1 0.8 VOperating free-air temperature, T A 0 70 °CNOTE 2:The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic voltage levels only.electrical characteristics over full range of recommended operating conditions (unless otherwise noted)c-s:mjc.s:(t)..3o-

TMS416165,536-0IT MULTIPORT MEMORYcapacitance over recommended supply voltage and operating free-air temperature range, f1 MHzPARAMETER Typt MAX UNITCi(A) Input capacitance, address inputs 4 5 pFCi(D) Input capacitance, data input 4 5 pFCURCI Input capacitance, strobe inputs 8 10 pFCi(W) Input capacitance, write enable input 8 10 pFCi(CK) Input capacitance, serial clock 8 10 pFCi(SI) Input capacitance, serial in 4 5 pFCi(SOE) Input capacitance, serial output enable 4 5 pFCi(TR) Input capacitance, register transfer input 4 5 pFCo(O) Output capacitance, random-access data 5 7 pFCo(SOUT) Output capacitance, serial out 5 7 pFt All typical values are at T A = 25°C and nominal supply voltages.switching characteristics over recommended supply voltage range and operating free-air temperature range(see figure 1)PARAMETERTEST CONDITIONSALT. TMS4161-15 TMS4161-20SYMBOL MIN MAX MIN MAXta(C) Access time from CAS CL = 100 pF tCAC 100 135Access time of a fromta(GE)CL = 100 pF 40 40ta(R)ta(RSO)ta(SOE;TR/DE lowAccess time from RASSOUT access time fromRAS highAccess time from SOElow to SOUTtRLCL = MAX,CL = 100 pFtRAC 150 200CL = 50 pF 60 60CL = 50 pF 20 25 nsta(SOI Access time from SCLK CL = 50 pF 30 30a output disable timetdis(CH)+tOFF20 25from CAS hightdis(OE)+tdis(SOE)+Q output disable timefrom 'fA/DE highSerial output disable timefrom SOE high20 2520 25t The maximum values for tdis(CH). tdis(QE). and tdis(SOE) define the time at which the output achieves the open circuit condition and are not referencedto VOH or VOL.UNITenQ)CJ'S:Q)c......oc.c.::::stJ)...>-oEQ)~'Cc:ca~

TMS416165,536·81T MULTIPORT MEMORYtiming requirements over recommended supply voltage range and operating free-air temperature range.OJ:J0..s:(I)3o"'l-

TMS416165,536·BIT MUL TIPORT MEMORYtiming requirements over recommended supply voltage range and operating free·air temperature range (continued)PARAMETERALT. TMS4161-15 TMS4161·20SYMBOL MIN MAX MIN MAXth(SO) Serial data out hold time after SCLK high 8 8 nsth(TR) TR/QE hold time after RAS low 20 20 nstRLCH Delay time, RAS low to CAS high tCSH 150 200 nstCHRL Delay time, CAS high to RAS low tCRP a a nstCLQEH Delay time, CAS low to QE high 100 135 nstCLRH Delay time, CAS low to RAS high tRSH 100 135 nstCLWLDelay time, CAS low to W low(read-modify-write cycle only)tCWD60 65nsDelay time, CAS low to QE lowtCQE (maximum value specified only 60 95 nsto guarantee ta(QE) access time)tRHSC Delay time, RAS high to SCLK high' 50 50,000 50 50,000 nstRLCLDelay time, RAS low to CAS low (maximumvalue specified only to guarantee ta(R))tRCD20 50 25 65 nstRLWLtCKRLDelay time, RAS low to W low(read-modify-write cycle only)Delay time, SCLK high beforeRAS low with TR/QE low'tRWD 110 130UNITns10 50,000 10 50,000 nstrf Refresh time interval tREF 4 4 msNOTE: Timing measurements are made at the 10% and 90% points of input and clock transitions. In addition, VIL max and VIH min must be met at the 10%and 90% points., SCLK be high or low during tWIRL)'PARAMETER MEASUREMENT INFORMATIONv = 1.31 V= 217 flOUTPUTUNDER TEST-JRLTCLt/)Q)(.)'SQ)c......oc.C.::len>...oEQ)~"Cc::CO~«ex:(.)'ECOc::>CFIGURE 1 -LOAD CIRCUITTEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-23

TMS416165,536-BIT MULTIPORT MEMORYread cycle timingVIHVILVIHVILc-

TMS416165,536 o BIT MUL TIPORT MEMORYearly write cycle timingAO-A7IiiDQVOHI_ •• twlWI -,~thlwLDI~I t---thlcLDI--.f... 1.1-----thRLD -I---D-O-N-'T-C-A-RE----~ VAUD DATA X'-______--.....~tsuIDIDON'T CARE\_-D_O_N_'T_C_A_R_E _____---------------HI-Z---------------f/)Q)(,)oS;Q)C...a..o0.0.:::JCJ)>-a..oEQ)~""Cc::CO~CTEXASINSTRUMENTSPOST OFFICE BOX 225012 '. DALLAS, TEXAS 752654-25

TMS416165,536-8IT MULTIPORT MEMORYwrite cycle timingc-

TMS416165,536·811 MULTIPORT MEMORYread-write/read-modify-write cycle timing,I.114·-----------tcrdWI----------~·1I 14 I-------- t WIRLI---------"1;-AO-A7l'RiilEDo.. ~t .:....I"'------tCLRH----~tl._twIRHI~1 L.-- tRLCL -----..I r I---..{IthlRAl11LI:. ! tRLCH------~t:.. 1 ~tCHRL---+I1 1----twlcLI---~_iII ~ III ~r-:-tsulRAI11'-----------......._I' 11 1 I----:--thlRLCAl .., tt --I t---I· .. I I .. ~---:-----tcLoEH-~I~II~I I I --.a '7tsUICAI I ~ Il~~ruI...._--twlcHI--~.. 1I I- -I 1 1I \\\f\\\\~ 'wIDE) l1;Z;.,......,...-r--rj---r-I , I II tsulrdl-:--1 ~tsuIWCHI~ II I, I~ tsuIWRHI~ I.. thlRLWI I -f 1I I I' I1'. II thlCLWI ·1 11 rtcLWL--.f I . I I I:: OC~~~c&oot! )[;-.wIM1X-X~X....,.)~~,r--J'·{~~4T"'""J1~Cr-"Jf'I. tRLWL "I I I I I• thIRLDI' . .1 I I: t---thlcLDI I II .1 1 1I I --..f~tsuIDI .1 I I:.: OOOOO&N10d00CI I thlWLDI I" ", I --I j-- tdislOEI1 I ~ j4-talOEi I· i tdislCHIVOHr-- tcoE ~II ; ~ VA"D p>-----I,-,--talCI• talRI -IIfAQ)Co)·SQ)c...>oEQ):liE""C&:CO:liEoCta:Co)'ECO&:>CTEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752654-27

~~~:;;z0_+>-N(Xl;;c ~~~d.~~t!'J~z~@x~U1'" enU1sao!l\aa ~.IoddnsA.lowall\l pue II\I"H O!weuAO_II twIRL) 1 ~RAS :,:[\ IS Jf ~I I· tRLCH ., tw(RH) r --t~-.I t.- ,. te(P) :1 r-- tCLRHtt I I tw(CH) I. ~ tCHRL---ICAS :,:I i.-tRLCL--=-t tt-.l ~ I ~tW(CL)---.f 1! i it,wICLJ1ht,wICLJr ~ i~----th(RA).,...., I ~ th(CLCA) I , I ' I I I II ~ th(RLCA)~ I I ,.. -I th(CLCA) , j.....*th(CLCA) I Itsu(RA) ~Ij- I ~ rstsU(CA)· I -.f r;-tSU(CA) I tSU(CA,)--t r;- I I IAD.A7 ~,: ROW DON'T CARE ~"f""x....:n-~"'

zI[~~~co,.. twiRL) _,RAS:::~ SI l LI J" tRLCH -, j.-tW(RH).,1 L I" tc(P) :1 j.--tCLRH ----Itt -1 ~ tw(CH) I. I ~ tCHRL---II tRLCL--t I tt--': ~-I· ~tW(CLlfCAS :,: : i W-" ClI l4" rtw,clI1r~ tlr-----th(RAI ~ ;"-+-th(CLCAI 1 I , I I 1 I 11 ~th(RLCAI--.J.. .1 th(CLCAI i----I-th(CLCAI,tsU(RAI~--Ir;-I -+I'"iCAI ! ~f\ €N;TZ~i ~X~HHHXX>th(TRI-J.--..! 1 I I . I· I 1 I--., \.- tsulTRI I I I I 1 I II~ I 7hv I.fRtOE :,: 'I I ~XXX)(~NKXX;0XXXXXXXXXY ~I I 1 1 I I I...--th(RLWI, _I I I t.:- tsu(WRHI---1J r-::- tsu(WCHI--.I ~ tsu(WCHI----t I.-tsu(WCHI-.jI th(CLWI I I" -I I th(CLWI I" -I I th(CLWI I I. -I·W:,: eN;~~R~: ~e4J~ Jt9{~~~E~ -l®

f'woz~~~~~RAS VIH~. rl 'wIRLIS9~!1\9a ~oddns AJOW911\1 pue 11\1,,1:::1 ~!WeUAa1 F . \VIL-,i'l::r-ss ¥i i'-tt I' tc(P) 'I J4-tCLRH -I I--tw(RH)---tr--tRLCL I~- tW(CL)~ I I--tcHRL----t! I' I t~LCH ---I I II_VIH :t! 1~~t--tW(CL)_____1ff~' ~~CAS VIL :: iTIi i'T fi-tW(CH)~\..I th(CLCA)~ tt-.4 I-- II tt-.t ~I I4--- t h(RLCA)4-!---i I Ith(RA) I I' ,I ; I I I I f4---.f- th(CLCA) I II""~RAT ~~ .. ",~.~ ~ IIIAOA7 ~,:~ • ROW ~ COLUMN i.V\AMf\N;~ COLUMN ~ '" A A A .. -th(TR) I I_ " I I I I I I I I---1 J.:-tsu(TR) I I I I I I I IIwOE ::7 : \ \N\'1- !: II : i" 'CLDEH iw VIH I XX'!::mlI &.....-...t-tCOE I I I I I II Itsu(rd) -'--1 I I I I' I I I I III tCLWL I- ~. - Ie- tsu(WCH)~ . II tsu(WCH) I' ,I I tsu(rd) -f I.-- I.--tSU(WRH)~ II I II r--tw(W)..f I tCLWL~ j--tw(W)--t II II~~~W; -\~ I ~I ~-r-JXX_ : 1\ ~IY I 1\ -¥5Z-"C en -III)CC .?1S:CD U1 enCor.)~3 en-0' enc.CD !!!-(;c.-III)s:c:3 r-0 -I§; :;;'

TMS416165,536·BIT MULTIPORT MEMORYRAS only refresh timingRASVIHVILVIHCASVILAO-A7VIHVILTR/OEVii0aVIHVILVIHVILVIHVILVOHVOL--------------HI-Z--------------....oc.C.:::ICJ)...>-oECD~"Ct:co~lid:a:(.)'Ecot:>CTEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-31

TMS416165,536·81T MULTIPORT MEMORYshift register to memory timingC'

~ ___TMS416165.536-BIT MUL TIPORT MEMORYmemory to shift register timing:,:------::lII.it-'RLCL----1 }1I r tRLCH .1AO·A7 :,:

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TMS416165,536-8IT MULTIPORT MEMORY1001001 VS. CYCLE TIME1001003 VS. CYCLE TIME«EI-ffia:a:::lU~c.c.::len098070605040302010100~ 'C, .f?'~O," ~" )-,0~,""'-'"" r--....... '~. I',~200 300 400 500 700 1000tc(rdl - CYCLE TIME - ns10080I I60 1-50% DUTY CYCLEINCLUDES 1002« 40 I-NOMINAL VOOEI-Z 20'" a:a:::lU10~c.c. 8::len 6«EII-Za:'"a:::lU~~::lenM0980706050403020101001005 VS. CYCLE TIME"r---.,i'-~-~ 'C.1.f?R" I.~ ")-,0~O ~.....,~.....,i'-..i'-......~ "200 300 400 500tc(rd) - CYCLE TIME - nsi--III 40 I---- --I--1-- ~I--- -- _.-9I---100221 10 2040 60 80 100 200tc(SCLK) - CYCLE TIME - ns400 600 1000800~.700 1000enQ)CJoS;Q)C4J...oc.c.~CJ)...>oEQ)~"CCCO~«a:CJ°eCOc>CTexas Instruments reserves the right to make changes at any time in order to improve design and to supply the best product possible.14TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-37

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MOSLSITMS4164, SMJ416465,536-8IT DYNAMIC RANDOM-ACCESS MEMORYJULY 1980 - REVISED OCTOBER 1983• 65,536 X 1 Organization• Single +5-V Supply (10% Tolerance)• JEDEC Standardized Pin-Out in Dual-In-LinePackages• Upward Pin Compatible with TMS4116(16K Dynamic .RAM)• First Military Version of 64K DRAM• Available Temperature Ranges:M . . . - 55°C to 125°CS ... - 55°C to 100°CE ... -40°C to 85°CL ... OOC to 70°C• Long Refresh Period . . . 4 milliseconds• Low Refresh Overhead Time . . . As Low As1.8% of Total Refresh Period• All Inputs, Outputs, Clocks Fully TTLCompatible• 3-State Unlatched Output• Common I/O Capability with "Early Write"Feature• Page-Mode Operation for Faster Access• Low Power DissipationOperating ... 125 mW (TVP)Standby ... 17.5 mW (TVP)• Performance Ranges (S, E, L TemperatureRanges):ACCESS ACCESSTIME TIMEROW COLUMNADDRESS ADDRESS(MAX) (MAX)'4164-12 120 ns 70 ns'4164-15 150 ns 85 ns'4164-20 200 ns 135 ns• New SMOS (Scaled-MOS) N-ChannelTechnologydescriptionREADORWRITECYCLE(MIN)230 ns260 ns326 nsThe '4164 is a high-speed, 65,536-bit, dynamicrandom-access memory, organized as 65,536 wordsof one bit each. It employs state-of-the-art SMOS(scaled MOS) N-channel double-level polysilicon gatetechnology for very high performance combined withlow cost and improved reliability.TMS4164 ••• FPL PACKAGE(TOP VIEW)c Zu m mlm u(TOP VIEW)NC [1 V16 VSSD 2 15 CASW 3 14 QRAS 4 13 A6AO 12 A3A2 11 A4A1 10 A5VDD 9 A7SMJ4164 •.• FG PACKAGE(TOP VIEW)2 1 1817 2 1 1817IN 3 0 16 Q IN 3 A 16 QRAS 4NC 5AO 6A2 7READ-MODIFY-WRITECYCLE(MIN)260 ns285 ns345 ns8 91011C I"- ll'l< C C:4ADVANCE INFORMATIONMILITARY PRODUCTS (SMJ) ONLYThis document contains information on a new product.Specifications are subject to change without notice.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265Copyright © 1983 by Texas Instruments Incorporated4-39

TMS4164, SMJ416465,536·BIT DYNAMIC RANDOM·ACCESS MEMORYThe '4164 features RAS access times of 120 ns, 150 ns, and 200 ns maximum. Power dissipation is 125 mW typicaloperating and 17.5 mW typical standby.Refresh period is extended to 4 milliseconds, and during this period each of the 256 rows must be strobed with RASin order to retain data. CAS can remain high during the refresh sequence to conserve power.A" inputs and outputs, including clocks, are compatible with Series 54/74 TTL. A" address lines and data-in are latchedon chip to simplify system design. Data-out is unlatched to allow greater system flexibility. Pin 1 has no internalconnection to allow compatibility with other 64K RAMs that use this pin for an additional function.The TMS4164 is offered in a 16-pin dual-in-line plastic package and is guaranteed for operation from 0 °C to 70°C.This package is designed for insertion in mounting-hole rows on 300 mil (7,62 mm) centers. An 18-pin plastic chipcarrier (FP suffix) package is also available.c-s:Q)::::JCos:(l)3.., o-

TMS4164, SMJ416465,536-811. DYNAMIC RANDOM-ACCESS MEMORYrefreshA refresh operation must be performed at least every four milliseconds to retain data. Since the output buffer is inthe high-impedance state unless CAS is applied, the RAS-only refresh sequence avoids any output during refresh.Strobing each of the 256 row addresses lAO through A 7) with RAS causes all bits in each row to be refreshed. CAScan remain high (inactive) for this refresh sequence to conserve power.page-modePage-mode operation allows effectively faster memory access by keeping the same row address and strobing successivecolumn addresses onto the chip. Thus, the time required to setup and strobe sequential row addresses forthe same page is eliminated. To extend beyond the 256 column locations on a single RAM, the row address and RASare applied to mUltiple 64K RAMs. CAS is then decoded to select the proper RAM.power-upAfter power-up, the power supply must remain at its steady-state value for 1 ms. In addition, RAS must remain highfor 100 p.s immediately prior to initialization. Initialization consists of performing eight RAS cycles before proper deviceoperation is achieved.logic symbol tAOA1A2A3A4A5A6A7RASCASViD15)~.;....---t 20D8/2100(7)(6)(12)(11)(10)(13)(9)(4)(15)(3)(2)....;..~--_t A,220RAM 64K X 1oA--6553523C22(14)AVt----- QC/)Q)(J->Q)c.....a..oC.C.::::J(J)> a..oEQ)~"Cc:CO~«a:(J-ECOc:>Ct This symbol is in accordance with IEEE Std 91/ANSI Y32.14 and recent decisions by IEEE and lEe. See explanation on page 10-1.ITEXASNSTRUMENlSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752654-41

TMS4164, SMJ416465,536-8IT DYNAMIC RANDOM-ACCESS MEMORYfunctional block diagramRAS=3CASTIMING & CONTROLW~------------------~0c-s:II)::lCos:ctI..3o'

TMS416465,536-811 DYNAMIC RANDOM-ACCESS MEMORYrecommended operating conditionsPARAMETERTMS4164MIN NOM MAXSupply voltage, VOO 4.5 5 5.5 VSupply voltage, VSS 0 VHigh-level input voltage, VIHI VOO = 4.5 V 2.4 4.8I VOO = 5.5 V2.4 6VLow-level input voltage, VIL (see Notes 2 and 3) -0.6 0.8 VOperating free-air temperature, T A 0 70 DCUNITNOTES:2. The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic voltagelevels only.3. Due to input protection circuitry. the applied voltage may begin to clamp at -0.6 V. Test conditions should comprehend this occurrence.electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)PARAMETERVOH High-level output voltage IOH = -5 mAVOL Low-level output voltage 10L = 4.2 mAIIInput current (leakage)TESTCONDITIONSVI=O V to 5.8 V, VOO=5 V,All other pins = 0 VVa = 0.4 to 5.5 V,10 Output current (leakage) VOO = 5 V,CAS high1001 *Average operating currentduring read or write cycle1002§ Standby current1003* Average refresh current RAS low,tc = minimum cycleAfter 1 memory cycle,RAS and CAS hightc = minimum cycle,CAS hightc(P) = minimum cycle.1004 Average page-mode current RAS low,CAS cyclingt All typical values are at T A = 25°C and nominal supply voltages.; Additional information on last page.§ VIL > -0.6 V.TMS4164-12 TMS4164-15MIN TYpt MAX MIN TVpt MAXUNIT2.4 2.4 V0.4 0.4 V±10 ±10 /LA±10 ±10 /LA40 48 35 45 mA3.5 5 3.5 5 mA28 40 25 37 mA28 40 25 37 mA...o~~::::JCJ)..>-oEQ)~"'Cr:::::CO~~a:(J-eCOr:::::>CTEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-43

TMS416465,536·BIT DYNAMIC RANDOM·ACCESS MEMORYelectrical chara,cteristics over full ranges of recommended operating conditions (unless otherwise noted)PARAMETERVOH High-level output voltage IOH = -5 mAVOL Low-level output voltage IOL = 4.2 mAIIInput current (leakage)TESTCONDITIONSVI = 0 V to 5.8 V. VOO = 5 VAll other pins = 0 VVo = 0.4 to 5.5 V.10 Output current (leakage) VOO = 5 V.CAS high1001 ~Average operating currentduring read or write cycle1002§ Standby current1003~ Average refresh current RAS low.tc = minimum cycleAfter 1 memory cycle.RAS and CAS hightc = minimum cycle.CAS high1004 Average page-mode current RAS low.tc(P) = minimum cycle.CAS cycling\TMS4164-20MIN Typt MAX2.40.4±10±1027 373.5 520 3220 32UNITVVp.Ap.AmAmAmAmAt All typical values are at T A = 25°C and nominal supply voltages.t Additional information on last page.§ VIL > ,-0.6 V.D)::::Ja.s:en3o ..,-

TMS416465,536·811 DYNAMIC RANDOM·ACCESS MEMORYswitching characteristics over recommended supply voltage range and operating free-air temperature rangetalC)ta(R)tdis(CH)PARAMETERAccess time from CASAccess time from RASOutput disable timeafter CAS highTEST CONDITIONSCL = 100 pFLoad = 2 Series 74 TTL gatestRLCL = MAX.Load = 2 Series 74 TTL gatesCL = 100 pF.Load = 2 Series 74 TTL gatesALT.TMS4164-20SYMBOLMIN MAXUNITtCAC 135 nstRAC 200 nstOFF 0 50 nsen(1)(J"S(1)c.....oc.C.::l(I'J...>oE(1)~"'CCCO~«a:(J"ECOc>CTEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-45

1MS416465.536·811 DYNAMIC RANDOM·ACCESS MEMORYtiming requirements over recommended supply voltage range and operating free-air temperature ranqeQ):::sCo~CD3o ...-

TMS416465,536-811 DYNAMIC RANDOM-ACCESS MEMORYtiming requirements over recommended supply voltage range and operating free-air temperature rangeALT.TMS4164-20PARAMETERUNITSYMBOL MIN MAXtc(P) Page mode cycle time tpc 206 nstc(rd) Read cycle time 1 tRC 326 nstc(W) Write cycle time twc 326 nstc(rdW) Read-write/read-modify-write cycle time tRWC 345 nstw{CH) Pulse width, CAS high (precharge time)t tcp 80 nstw(CLl Pulse width, CAS low 9 tCAS 135 10,000 nstw(RH) Pulse width, RAS high (precharge time) tRP 120 nstwIRL) Pulse width, RAS low' tRAS 200 10,000 nstw(W) Write pulse width twp 55 nstt Transition times (rise and fall) for RAS and CAS tT 3 50 nstsu(CA) Column addresBs;etup time tASC -5tsu(RA) Row address setup time tASR 0 nstsu(D) Data setup time tDS a nstsu(rd) Read command setup time tRCS 0 nstsu(WCH) Write command setup time before CAS high tCWL 60 nstsu(WRH) Write command setup time before RAS high tRWL 60 nsth(CLCA) Column address hold time after CAS low tCAH 55 nsth(RA) Row address hold time tRAH 25 nsth(RLCA) Column address hold time after RAS low tAR 120 nsth(CLD) Data hold time after CAS low tDH 55 nsth(RLD) Data hold time after RAS low tDHR 145 nsth(WLD) Data hold time after W low tDH 55 nsth(CHrdl Read command hold time after CAS high tRCH 0 nsth(RHrd) Read command hold time after RAS high tRRH 5 nsth(CLW) Write command hold time after CAS low tWCH 55 nsth(RLWI Write command hold time after RAS low tWCR 145 nstRLCH Delay time, RAS low to CAS high tCSH 200 nstCHRL Delay time, CAS high ,to RAS low tCRP 0 nstCLRH Delay time, CAS low to RAS high tRSH' 135 nstCLWLDelay time, CAS low to W low(read-modify-write cycle only)tCWD 65 nsDelay time, RAS low to CAS iowtRLCL (maximum value specified only tRCD 25 65 nsto guarantee access time)tRLWLtWLCLDelay time, RAS low to W low(read-modify-write cycle only)Delay time, W low to CASlow (early write cycle)tRWD 130twcs -5trf Refresh time interval tREF 4 msnsns......oc.C.:l(J)...>-oEQ)~"Ct:CO~~a:CJ-ECOt:>CNOTE: Timing measurements are made at the 10% and 90% points of input and clock transitions. In addition, Vil max and VIH min must be met at the10% and 90% points.t All cycle times assume tt = 5 ns.* Page mode only.§ In a read-modify-write cycle, tClWl and tsu(WCHI must be observed. Depending on the user's transition times. this may require additional CAS low time(tw(Clll. This applies to page mode read-modify-write also., In a read-modify-write cycle. tRlWl and tsu(WRHI must be observed. Depending on the user's transition times, this may require additional RAS low time(tw(Rlll.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-47

SMJ416465.536·811 DYNAMIC RANDOM·ACCESS MEMORYrecommended operating conditionsSMJ4164PARAMETER M VERSION S VERSION EVERSION UNITMIN NOM MAX MIN NOM MAX MIN NOM MAXSupply voltage, VOO 4.5 5 5.5 4.5 5 5.5 4.5 5 5.5 VSupply voltage, VSS 0 0 0High-level inputvoltage, VIHLow-level input2.4 VCC+0 .3 2.4 VCC+0.3 2.4 VCC+0.3 Vvoltage, VIL -0.6 0.8 -0.6 0.8 -0.6 0.8 V(see Notes 2 and 3)Operating casetemperature, T C-55 125 -55 100 -40 85 DCNOTES:2. The algebraic convention. where the more negative (less positive I limit is designated as minimum. is used in this data sheet for logic voltagelevels only.3. Due tq input protection circuitry. the applied voltage may begin to clamp at -0.6 V. Test conditions should comprehend this occurrence.C'

SMJ416465,536-011 DYNAMIC RANDOM-ACCESS MEMORYelectrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)PARAMETERVOH High-level output voltage 10H = -5 mAVOL Low-level output voltage 10L = 4.2 mAIIInput current (leakage)TESTCONDITIONSVI=O V to 5.8 V, VOO=4.5 Vto 5.5 V, output openVo = 0 V to 5.5 V,10 Output current (leakage) VOO = 5 V,CAS high1001fAverage operating currentduring read or write cycle1002§ Standby current1003 f Average refresh current RAS low,tc = minimum cycleAfter 1 memory cycle,RAS and CAS hightc = minimum cycle,CAS hightc(P) = minimum cycle,1004 Average page-mode current RAS low,CAS cyclingt All typical values are at TC = 25 DC and nominal supply voltages.t Additional information on last page.§ VIL > -0.6 V.SMJ4164-12SMJ4164-15S,E VERSIONS S,E VERSIONS UNITMIN Typt MAX MIN Typt MAX2.4 2.4 V0.4 0.4 V±10 ±10 p.A±10 ±10 p.A40 48 35 45 mA3.5 5 3.5 5 mA28 40 25 37 mA28 40 25 37 mA+"...o0.0.::len... >oEQ)~"'Cc::CO~CTEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752654-49

SMJ416465,536-811 DYNAMIC RANDOM-ACCESS MEMORYC'

SMJ416465,536-81T DYNAMIC RANDOM-ACCESS MEMORYswitching characteristics over recommended supply voltage range and operating free-air temperature rangeta(C)ta(R)tdis(CH)PARAMETERAccess time from CASAccess time from RASOutput disable timeTEST CONDITIONSCL = 80 pF,see Figure 1tRLCL = MAX,see Figure 1CL = 80 pF,after CAS high see Figure 1SMJ4164-12 SMJ4164-15ALT.S,E VERSION S,E VERSIONSSYMBOLMIN MAX MIN MAXUNITtCAC 70 85 nstRAC 120 150 nstOFF 0 40 0 40 nsswitching characteristics over recommended supply voltage range and operating free-air temperature rangeta(C)ta(R)tdis(CH)SMJ4164-20ALT.PARAMETER TEST CONDITIONS S,E VERSION UNITSYMBOLMIN MAXAccess time from CASAccess time from RASOutput disable timeCL = 80 pF,see Figure 1tRLCL = MAX,see Figure 1CL = 80 pF,after CAS high see Figure 1tCAC 135 nstRAC 200 nstOFF 0 50 nsenQ)(.)-s;Q)c~-o0.0.::l(J),0>-EQ)~,~c:CO~«a:(.)-eCOc:>-CTEXASINSfRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752654-51

SMJ416465,536-811 DYNAMIC RANDOM-ACCESS MEMORYtiming requirements over recommended supply voltage range and operating free-air temperature rangec

SMJ416465,536-011 DYNAMIC RANDOM-ACCESS MEMORYtiming requirements over recommended supply voltage range and operating free-air temperature rangeSMJ4164-12 SMJ4164-15ALT.PARAMETER S,E VERSIONS S.E VERSIONS UNITSYMBOLMIN MAX MIN MAXtc(P) Page mode cycle time tpc 130 160 nstc(rd) Read cycle time t tRC 230 260 nstc(Wi Write cycle time twc 230 260 nstc(rdW) Read-write/read-modify-write cycle time tRWC 260 285 nstwlCH) Pulse width, CAS high (precharge time) * tcp 50 50 nstw(CLl Pulse width, CAS low § tCAS 70 10,000 85 10,000 nstw(RH) Pulse width, RAS high (precharge time) tRP 80 100 nstwIRL) Pulse width, RAS low' tRAS 120 10,000 150 10,000 nstw(Wi Write pulse width twp 40 45 nstt Transition times (rise and fall) for 'RAS and CAS tT 3 50 3 50 nstsu(CA) Column address setup time tASC -5 -5 nstsulRAi Row address setup time tASR 0 0 nstsu(D) Data setup time tDS 0 0 nstsu(rd) Read command setup time tRCS 0 0 nstsu(WCH) Write command setup time before CAS high tCWL 50 50 nstsu(WRH) Write command setup time before RAS high tRWL 50 50 nsth(CLCA) Column address hold time after CAS low tCAH 40 45 nsth(RAJ Row address hold time tRAH 15 20 nsth(RLCA) Column address hold time after RAS low tAR 85 95 nsth(CLD) Data hold time after CAS low tDH 40 45 .. nsth(RLDl Data hold time after RAS low tDHR 85 95 nsth(WLD) Data hold time after W low tDH 40 45 nsth(CHrd) Read command hold time after CAS high tRCH 0 0th(RHrdl Read command hold time after RAS high tRRH 5 5 nsth(CLW) Write command hold time after CAS low tWCH 40 45 nstti(RLW) Write command hold time after ~ low tWCR 85 95 nstRLCH Delay time, RAS low to CAS high tCSH 120 150 nstCHRL Delay time, CAS high to RAS low tCRP 0 0 nstCLRH Delay time, CAS low to RAS high tRSH 60 100 nstCLWLDelay time, CAS low to W low(read-modify-write cycle only)tCWD 40 60 nsDelay time, RAS low to CAS lowtRLCL (maximum value specified only tRCD 15 50 20 65 nsto guarantee access time)tRLWLtWLCLDelay time, RAS low to W low(read-modify-write cycle only)Delay time, W low to CASlow (early write cycle)tRWD 85 100 nstwcs -5 -5trf Refresh time interval tREF 4 4 ms-"nsns.~a..o0.0.::len>- a..oEOJ~"0c::CO~«a:(.)'ECOc::>CNOTE: Timing measurements are made at the 10% and 90% points of input and clock transitions. In addition. VIL max and VIH min must be met at the10% and 90% points.t All cycle times assume tt = 5 ns.t Page mode only.§ In a read-modify-write cycle, tCLWL and tsulWCH) must be observed. Depending on the user's transition times, this may require additional CAS low time(tw(CL))' This applies to page mode read-modify-write also.__, In a read-modify-write cycle, tRLWL and tsu(WRH) must be observed. Depending on the user's transition times, this may require additional RAS low time(tw(RL))'TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-53

SMJ416465,536-8IT DYNAMIC RANDOM-ACCESS MEMORYtiming requirements over recommended supply voltage range and operating free-air temperature rangec-~~:lCo~CD3...o-

TMS4164, SMJ416465,536·81T DYNAMIC RANDOM·ACCESS MEMORYPARAMETER MEASUREMENT INFORMATION1.31 VOUTPUTUNDERTESTFIGURE 1 -I-IRLelLOAD CIRCUITread cycle timingRASCASAO-A7wenQ)(J.S;Q)C......oc.C.:::::ICI)...>-oEQ)~~c:m~«a:::(J'Emc:>-CQTEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-55

TMS4164. SMJ416465.536"8IT DYNAMIC RANDOM"ACCESS MEMORYearly write cycle timingRASCASc-

TMS4164, SMJ416465,536·8IT DYNAMIC RANDOM·ACCESS MEMORYwrite cycle timingRASCASAO-A7ViDQVIHVILVIHVILVIHV,LVIHVILV,HV,LVOHVOL_tSU(RA)~I-tc(W) -,1,, I- tw(RL)~ I IU -t ~~r-ttI- tCLRH "I r-tw(RH)~, j.-tRLCL ~ J.- tCHRL ---I, I.. I tRLCH _I "1 t-tW(CL)~L'--1l4jt SU tw(CH)~(CA) I'"I ~th(RLCA)~ ---I Jl-ttt~(RA)-r--' 1 ~th(CLCA) IIIROW ~COLUMN~1 I ~ tsu(WCH) --.f ! I~ 1 I---tSU(WRH)~th(RLW) -1 II ~th(CLW)----' I~VvIJr~~~0ECD~"CCctS~

TMS4164, SMJ416465,536·BIT DYNAMIC RANDOM·ACCESS MEMORYread-write/read-modify-write cycle timingC-----1 ! II 14--- ta(C)~/- ta(R) ./I II4-58 TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

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~0,oz~i~RASCASAO-A7WoNOTE:sa:>!l\ac ~Joddns AJOWall\l pue II\IVU :>!WeUAC/I- tw(RLI -IVIH~ ijc 4-VIL I H fL l\-Ir tRLCH·1 . f4-tw(RHI~1_ ,----i .-tt Itc(PI -,\ .~I~tCLRH~1IL --l tw(CHI . 1...-tRLCL I~I --I t--tt I ~tCHRL .......I \- tw(CLI-----l ~l.-tW(CL)--.ltl: : I i.--tW(CLI----..fnlVIH II -t~ , I }~ , IVIL I I ,+ I =f fI \' I 1th(RA)J.....i, 'I...-Lth(CLCA) I , ~th(CLCA) II \ ~I th(CLCA)1 \I I 1 j- -I I I' 'I j I, J4-rh(RLSA)~ " I I I I I I I ItSU(RA)-.t'f I ~tSUtCA) : ~~tSU.(CA): .-.llttSU(CA) II:" ~~ COL ~""""'~D"O""N"'T""C"'A"'RE"""'-""IL ~ 'II ~th(CLW) h - J-t"""", th(CLW) 'I. su(WRH)t---th(RLW)----, I 1 ' ~,1 I 1 ~ , - r---tsu(WCH)......,, j4---tsu(WCH)---" ~tsu(WCH)~ \1VIH~I: I~~! ~~_i!'--,-------4"""':t~VIL~~~~ ~, I I- ·1 tw(W) ,I--I tw(W) I IJ -, tw(W)1 I II . ., L"tsu(D) ~ J..!-t ~ tsu(D)...... r-:-:-,1I , , , ' .JI " " th(WLD) I- 1 th(WLD)I I 1 ~ 1~'" OON'T CARE VALID DATA DON'T CARE VALID DATA *~~{;~6HmIL I I 1I I- .1 th(CLD) I- th(CLD) I. .1 th(CLD)~th(RLD) ---...IA read cycle or a read-modify-write cycle can be intermixed with write cycles as long as read and read-modify-write timing specifications are notviolated,=-f'CI»ec .?'IE!!:CD U'I mw~30 =-c. . =CD 5!!!~-f"~. omCD -~C)CDE!!:-... -=n~3'5'ec > =Z0QE!!::i:-nm3:m3:Q= -

Z~d~~~~0,'...."CIIICCCD:3of. twIRL) ,CoCDHAS ~,: , II ~e---.--=lt- [-.r ,.-tt I. tc(P) -I,. tCLRH ., t-tw(RH)., :3I I I 0, J.--tRLCL~ tw(CL) ~~I II. tw(CL) .1 &-tCHRL.....f g;VIH ,. ===--J tRLCH -I ~ '1 4- ~CAS I I I I Jt.1:\' ~.VIL , , _ ..... tt' tt ..... J.- I CDr----:-th(RLCA)~ I, II I r.--tW(CH)~ ~., ~th(RA) I ~th(CLCA) " I : :.--.J-th(CLCA) 'II ;.-.. 'ItSU(RA~.1 t-;-tsu(CA) I ---- j.f-tsu(CA) I , _.AO-A7 VIH ~ ROW COLUMN m:J: cOLuMN~gl*l:mI~ ~.VIL~, ~I ~ ~ 'I' CC, tsU(rd)~ I i--tsu(WCH)-.I tsu(rd)--'----; I tsU(WCH)~I ,I , I I I tsu(WRH) I rI I j-"-tCLWL ~ I I I I.-tCLWL ----,1 ,VIH %hilililii'tJlf, ttJ.-tW(W)-''' I t+~tW(W)--I~'U""''''''AAA~W DON'T CARE N'T AR I DON'T CAREDQNOTE:VIL I L"f,. ,,' tRL~L _Ii I . I : I I nnnnn).. thIRLD). I -I I I I II. I. th(CLD) -, I • th(CLD) .,. • ~tSU(D) ~ I -..Il+-tsu(D) ~~:~_~VALIDDAT~:";:;WNmm*ALlDDAT~;mI I th(WLD) I· -I ~tdis(CH) I th(WLD)I· -1 HtdiS(CH)~~: I HI-Z I ¢ VALID DA;A ~r-fHI-Z ¢ VALID DATA }-l.--ta(C)------:II. taIR) ------..1----..~ ta(C)---.IA read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not violated.Dynamic RAM and Memory Support DevicesenenU,Co\)enCa=iCI-

TMS4164, SMJ416465,536-81T DYNAMIC RANDOM-ACCESS MEMORYRAS-only refresh timingRASCASC'....IQ.Q.::III)MC910080706050403020101001003 vs. CYCLE TIMEN '(),jI~~~,jI~..... l-y..o',.........................,"" ....200 300 400 500 700 1000~tc(rd) - CYCLE TIME - ns~Texas Instruments reserves the right to make changes at any time in order to i~prove design and to supply the best product possible.4-62 TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

MOSLSITMS4256. TMS4257262.144·8IT DYNAMIC RANDOM·ACCESS MEMORIESMAY 1983 - REVISED JANUARY 1984• 262,144 X 1 Organization• Single +5-V Supply (10% Tolerance)• JEDEC Standardized Pin Out• Upward Pin Compatible with TMS4164(64K Dynamic RAM)• Performance Ranges:ACCESS ACCESSTIME TIMEDEVICE ROW COLUMNADDRESS ADDRESS(MAX) (MAX)TMS4256-10TMS4257-10TMS4256-12TMS4257-12TMS4256-15TMS4257-15TMS4256-20TMS4257"20100 ns 50 ns120 ns 60 ns150 ns 75 ns200 ns 100 ns• Long Refresh Period ... 4 ms (MAX)READORWRITECYCLE(MIN)200 ns230 ns260 ns330 nsTMS4256. TMS4257 ... JL OR NL PACKAGEAD-ASASDWRASAD• Low Refresh Overhead Time ... As Low As 1.3% of Total Refresh Period• On-Chip Substrate Bias Generator• All Inputs, Outputs, arid Clocks Fully TTL Compatible• 3-State Unlatched Output• Common I/O Capability with "Early Write" Feature• Page ('4256) or Nibble-Mode ('4257) Options for Faster Access Operation• Power Dissipation As Low As:Operating ... 225 mW (TVP)Standby ... 12.5 mW (TVP)• RAS-Only Refresh Mode• Hidden Refresh Mode• CAS-Before-RAS Refresh Mode (Optional)CASDQRASINVDDVSSA2AlVDD(TOP VIEW)VSSCASQA6A3A4A5A7, PIN NOMENCLATUREAddress InputsColumn Address StrobeData-InData-OutRow Address StrobeWrite Enable+5-V SupplyGround• Available with MIL-STD-883B Processing and L(OOC to 70°C), E(-400C to 85°CI, or S(-55°C to100°C) Temperature Ranges in the Future........oc.c.::::sen>- ...oEQ)~"Ct:CO~«ex:(.)'ECOt:>-CdescriptionThe' 4256 and' 4257 are high-speed, 262, 144-bit dynamic random-access memories, organized as 262,144 wordsofone bit each. They employ state-of-the-art SMOS (scaled MOS) N-channel double-level polysilicon gate technologyfor very high performance combined with low cost and improved reliability.These devices feature maximum RAS access times of 100 ns, 120 ns, 150 ns, or 200 ns. Typical power dissipationis as low as 225 mW operating and 12.5 mW standby.New SMOS technology permits operation from a single + 5-V supply, reducing system power supply and decouplingPRODUCT PREVIEWThis document contains information on a product underdevelopment. Texas Instruments reserves the right tochange or discontinue this product without notice.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265Copyright © 1984 by Texas Instruments Incorporated4-63

TMS4256, TMS4257262,144·81T DYNAMIC RANDOM·ACCESS MEMORIESrequirements, and easing board layout. IDD peaks are 150 mA typical, and a -1-V input voltage undershoot can betolerated, minimizing system noise considerations.operationAll inputs and outputs, including clocks, are compatible with Series 74 TTL. All address and data-in lines are latchedon chip to simplify system design. Data-out is unlatched to allow greater system flexibility.The' 4256 and' 4257 are offered in a 16-pin dual-in-line ceramic or plastic package and are guaranteed for operationfrom 0 DC to 70 DC. These packages are designed for insertion in mounting-hole rows on 300 mil (7,62 mm) centers.address (AO through AS)c-s:Q)jCos:CD3o~-

TMS4256, TMS4257262,144·8IT DYNAMIC RANDOM·ACCESS MEMORIESpage-mode (TMS4256)Page-mode operation allows effectively faster memory access by keeping the same row address and strobing randomcolumn addresses onto the chip. Thus, the time required to setup and strobe sequential row addresses for the samepage is eliminated. The maximum number of columns that can be addressed is determined by tw(RL), the maximumRAS low pulse width. For example, with a minimum cycle time (tc(P) = 100 ns) appr'oximately 100 of the 512 columnsspecified by column AO to column AS can be accessed. Row AS provided in the first page cycle, specifies whichgroup of 512 columns, out of the 1024 internal columns is to be paged.nibble-mode (TMS4257)Nibble-mode operation allows high-speed serial read, write, or read-modify-write access of 1 to 4 bits of data. Thefirst bit is accessed in the normal ~ner wit~ad data coming out at talC) time. The next sequential nibble bitscan be read or written by cycling CAS while RAS remains low. The first bit is determined by the row and columnaddresses, which need to be supplied only for the first access. Row AS and column AS provide the two binary bitsfor initial selection, with row AS being the least significant address. Thereafter, the falling edge of CAS will accessthe next bit of the circular 4-bit nibble in the following sequence:C--(O,O) .. (0,1)--------.,.... ( 1,0) -------1...( l,l):=-JIn nibble-mode, all normal memory operations (read, write, or ready-modify-write) may be performed in any desiredcombination.power-upTo achieve proper device operation. an initial pause of 200 p'S is required after power up followed by a minimum ofeight initialization cycles.logic symbol t(5)RAM 256K X 1AO ....;..;..:...----12009/2100(7)A1(6)A2(12)A3(11)A4A_O_(10)A5262143(13)A6(9)A7(1)ASRAS(4)enCl).(.)'SCl)c......oc.C.::::JtJ)...>oECl)~"Ct:CO~~a:(.)'ECOt:>CCAS(15)23C22W0(3)(2)A,220A\l(14)Qt This symbol is in accordance with IEEE Std 91/ANSI Y32.14 and recent decisions by IEEE and lEe. See explanation on page 10·1.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-65

TMS4256, TMS4257262,144·81T DYNAMIC RANDOM·ACCESS MEMORIESfunctional block diagramc

TMS4256, TMS4257262,144-8IT DYNAMIC RANDOM-ACCESS MEMORIESelectrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)TMS4256-10TMS4256-12TESTPARAMETER TMS4257-10 TMS4257-12 UNITCONDITIONSMIN Typt MAX MIN Typt MAXVOH High-level output voltage 10H = -5 mA 2.4 2.4 VVOL Low-level output voltage 10L = 4.2 mA 0.4 0.4 VII Input current (leakage)VI=O V to 5.8 V, VOO=5 V,All other pins = 0 V to 5.8 V±10 ±10 I'AVo = 0 V to 5.5 V,10 Output current (leakage) VOO = 5 V, ±10 ±10 I'ACAS high10D1Average operating currentduring read or write cycletc = minimum cycle 75 TBO 65 TBO mA1002 Standby currentAfter 1 memory cycle,RAS and CAS hightc = minimum cycle,2.55 2.5 5 mA1003 Average refresh current RAS low, 60 TBO 50 TBO mACAS hightc(P) = minimum cycle, \1004 Average page-mode current RAS low, 50 TBO 40 TBO mACAS cyclingtc(N) = minimum cycle,1005 Average nibble-mode current RAS low. 45 TBO 35 TBO mACAS cyclingt All typical values are at T A = 25°C and nominal supply voltages.TMS4256-15 TMS4256-20TESTPARAMETER TMS4257-15 TMS4257-20 UNITCONDITIONSMIN Typt MAX MIN Typt MAXVOH High-level output voltage IOH = -5 mA 2.4 2.4 VVOL Low-level output voltage 10L = 4.2 mA 0.4 0.4 VII Input current (leakage)VI=O V to 5.8 V. VDD=5 V,All other pins = 0 V to 5.8 V±10 ± 10 I'AVo = 0 V to 5.5 V,10 Output current (leakage) VOO = 5 V, ±10 ±10 I'ACAS high1001Average operating currentduring read or write cycle1002 Standby currenttc = minimum cycle 55 TBO 45 TBO mAAfter 1 memory cycle,RAS and CAS hightc = minimum cycle,2.5 5 2.5 5 mA1003 Average refresh current RAS low, 45 TBO 35 TBO mACAS hightc(P) = minimum cycle,1004 Average page-mode current RAS low, 35 TBO 25 TBO mACAS cyclingtc(N) = minimum cycle,1005 Average nibble-mode current RAS low. 30 TBO 20 TBO mACAS cyclingU)Q)o-S;Q)c......oc.c.::::sen>-...oEQ)~"Cr::::m~«a:o-Emr::::>-Ct All typical values are at T A = 25°C and nominal supply voltages.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-67

TMS4256, TMS4257262,144·8IT DYNAMIC RANDOM~ACCESS MEMORIEScapacitance over recommended supply voltage range and operating free-air temperature range, f1 MHzPARAMETER Typt MAX UNITCi(A) Input capacitance, address inputs 4 7 pFCi(O) Input capacitance, data input 4 7 pFCilRC) Input capacitance strobe inputs 8 10 pFCi(W) Input capacitance, write enable input 8 10 pFCo Output capacitance 5 10 pFt All typical values are at T A· = 25 DC and nominal supply voltages,switching characteristics over recommended supply voltage range and operating free·alr temperature rangeC'3:C»:;:,c..3:c3o..'

TMS4256, TMS4257262,144·8IT DYNAMIC RANDOM·ACCESS MEMORIEStiming requirements over recommended supply voltage range and operating free-air temperature rangeTMS4256-10 TMS4256-12ALT.PARAMETER TMS4257-10 TMS4257-12 UNITSYMBOLMIN MAX MIN MAXtc!PI Page-mode cycle time (read or write cycle) tpc 100 120 nstc(PM) Page-mode cycle time (read-modify-write cycle) tpCM 135 165 nstc(rd) Read cycle time t tRC 200 230 nstC!WI Write cycle time twc 200 230 nstc(rdW) Read-write/read-modify-write cycle time tRWC 235 270 nstw(CH)P Pulse duration, CAS high (page mode) tcp 40 50 nstwlCHI Pulse duration, CAS high (non-page mode) tCPN 40 50 nstw(Cl) Pulse duration, CAS low:t tCAS 50 10,000 60 10,000 nstw(RHI Pulse duration, RAS high (precharge time) tRP 90 100 nstwIRl) Pulse duration, RAS low § tRAS 100 10,000 120 10,000 nstw(WI Write pulse duration twp 35 40 nstt Transition times (rise and fall) for RAS and ~ tT 3 50 3 50 nstsuJCAi Column address setup time tASC 0 0 nstsu(RA) Row address setup time tASR 0 0 nstsu(D) Data setup time tDS 0 0 nstsu(rd) Read command setup time tRCS 0 0 nstsu(WCL)Early write command setup timebefore CAS lowtwcs0 0 nstsulWCHI Write command setup time before CAS high tCWL 30 40 nstsu(WRH) Write command setup time before RAS high tRWL 30 40 nsth(CLCA) Column address hold time after CAS low tCAH 20 20 nsth(RAI Row address hold time tRAH 15 15 nsth(RLCAI Column address hold time after RAS low tAR 70 80 nsthlCLD) Data hold time after CAS low tDH 30 35 nsth(RLD) Data hold time after RAS low tDHR 80 95 nsth(WLD) Data hold time after W low tDH 30 35 nsthiCHrdl Read command hold time after CAS high tRCH 0 0 nsthlRHrdl Read command hold time after RAS high tRRH 10 10 nsth{CLW) Write command hold time after CAS low tWCH 30 35 nsthlRLWI Write command hold time after RAS low tWCR 80 95 nstRLCHR Delay time, RAS low to CAS high 1 tCHR 20 25 nstRLCH Delay time, RAS low to CAS high tCSH 100 120 nstCHRL Delay time, CAS high to RAS low tCRP 0 0 nstCLRH Delay time, CAS low to RAS high tRSH 50 60 nstCLRL Delay time, CAS low to RAS low' tCSR 20 25 nsDelay time, CAS low to W lowtCLWL(read-modify-write cycle only)tCWD 50 60 nsDelay time, RAS low to CAS lowtRLCL (maximum value specified only tRCD 25 50 25 60 nsto guarantee access time)tRLWLDelay time, RAS low to W low(read-modify-write cycle only)tRWD 100 120 nstrf Refresh time interval tREF 4 4 ms.. ..NOTE: Timing measurements are made at the 10% and 90% POints of Input and clock tranSitIOns. In additIOn, VIL max and VIH min must be met at the10% and 90% points.t All cycle times assume tt = 5 ns.:I: In a read-modify-write cycle, tCLWL and tsu(WCHI must be observed. Depending on the user's transition times, this may require additional CAS low time(tw(CLII. This applies to page-mode read-modify-write also.§ In a read-modify-write cycle, tRLWL and tsu(WRHI must be observed. Depending on the user's transition times, this may require additional RAS low time(tw(RLII., CAS before RAS refresh only.......oc.C.::len> ...oE(1)~"Ceca~«a:(.)'Eca·e>C14TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-69

TMS4256, TMS4257262,144·811 DYNAMIC RANDOM·ACCESS MEMORIEScCD

TMS4257262.144·8IT DYNAMIC RANDOM·ACCESS MEMORIESNIBBLE MODE CYCLEswitching characteristics over recommended supply voltage range and operating free-air temperature range(unless otherwise noted)ALT. TMS4257-10 TMS4257-12PARAMETERSYMBOL MIN MAX MIN MAXta(CN) Nibble mode access time fro~ CAS tNCAC 25 30UNITnsPARAMETERNibble mode access time from CAS'ALT.SYMBOLtNCACtiming requirements over recommended supply voltage range and operating free-air temperature range(unless otherwise noted)PARAMETERALT. TMS4257-10 TMS4257-12SYMBOL MIN MAX MIN MAXtc(N) Nibble mode cycle time tNC 50 60tc(rdWN) Nibble mode read-modify-write cycle time tNRMW 70 85tCLRHN Nibble mode delay time, CAS low to RAS high tNRSH 25 30tCLWLN Nibble mode delay time, CAS to W delay tNCWD 20 25tw(CLN) Nibble mode pulse duration, CAS low tNCAS 25 30tw(CHN) Nibble mode pulse duration, CAS high tNCP 15 20Nibble mode write command setuptsu(WCHN)time before CAS hightNCWL '20 25timing requirements over recommended supply voltage range and operating free-air temperature range(unless otherwise noted)PARAMETERALT. TMS4257-15 TMS4257-20SYMBOL MIN MAX MIN MAXtc(N) Nibble mode cycle time tNC 75 90tc(rdWN) Nibble mode read-modify-write cycle time tNRMW 105 130tCLRHN Nibble mode delay time, CAS low to RAS high tNRSH 40 50tCLWLN Nibble mode delay time, CAS to W delay tNCWD 30 40tw(CLN) Nibble mode pulse duration, CAS low tNCAS 40 50tw(CHN) Nibble mode pulse duration, CAS high tNCP 25 30Nibble mode write command setuptsu(WCHN)time before CAS hightNCWL 35 45UNITnsUNITnsenCI)CJ'S;CI)C...oc.C.:J(/)..>oECI)~"'CCCO~«a:CJ'ECOc>CTEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-71

TMS4256, TMS4257262,144"81T DYNAMIC RANDOM"ACCESS MEMORIESread cycle timingc-

TMS4256, TMS4257262,144·BIT DYNAMIC RANDOM·ACCESS MEMORIESearly write cycle timingRASCASAD-ASwoQVOH-----------HI-Z------------t/)Q)(.).s;:Q)C......o0.0.::len... >oEQ)~"'0c:CO~

TMS4256, TMS4257262,144·81T DYNAMIC RANDOM·ACCESS MEMORIESwrite cycle timingRASmCASC-

TMS4256, TMS4257262,144·8IT DYNAMIC RANDOM·ACCESS MEMORIESread·write/read-modify-write cycle timingRASCASAO-ASwDQ(/)Q)(,)'S;Q)C...~oc.C.::Jen>~oEQ)~"CL:C'O~c3:a:(,)'EC'OL:>C4TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752654-75

TMS4257262,144·8IT DYNAMIC RANDOM·ACCESS MEMORIESnibble mode read cycle timingRASCAStW(RH)---\ r-~:: ~----------------------il\..I,: I.. tRLCH---~·1I r--tRLCL ~ -Ii r- tw(CHN)I I tw(CL) I. .1. I---tC(N)~II'c-

TMS4257262,144·81T DYNAMIC RANDOM·ACCESS MEMORIESnibble mode write cycle timingRASCASAO-ABWDQt W (RH)-1 ~~:: 1\1""----------------------"-IIIVIHI I_ tRLCH III: j---tRLCL -----i tCLRHN --II Itw(CL) -Io~f---~IVIL -.j iJ- tsu(RA) I II I th(CLCA) I I.. -I II ICI tw(CLN) II "1---.-th(RLCA)H II Ith(RA)-iIi4'--~-1I IL-.! ith(CLCA) I I I~:J¢I'-'"'R-O-W-~COLUMN~I I II II I II II ~tsU(WCL) I I II I II th(CLW)--to-'iVIH . w~~i\~~~E~ II ! M~~~';?VIL 'llli"J"JfMX~ =fZW ~IIII- th(RLD)--~·1 II ~th(WLD)tsu(D)-otJ+--- II I IVIHVILVOHVOLHI-ZIC/)Q)U":;Q)C..."-o0.0.::len>"-oEQ)~"'0CCO~«a:::u"ECOc>CTEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752654-77

. 14--1 th(RLCA)~1TMS4257262, 144·8IT. DYNAMIC RANDOM·ACCESS MEMORIESnibble mode read·modify·write-cycle timingc-4-78 TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

Z~d~~~~.!..JcoNOTE:'CIIICO(1),- twIRL) -, ~RAS ~',: ---N H J{ t :: I- tRLCH 'I I r-tW(RH)j ~!.----.t-tw(CH)P,1.-+I I--tt I- te(P) I I -I \.--tCLRH~ I I ~1 !.-tRLCL!.i J : l~tCHRL.....j i'l I ! ~._VIH 'N,II l+-tw(CL) -rtW(CL)---..intt~ I I I.--tw(CL)~ r-lCAS - I I' 1VIL I 1 I I I I : I II I I,-_i 1 1 I H II I M'th(RA)t' r-- I r--r-th(CLCA) 1 I ~th(CLCA) 1 . 1 I th(CLCA) I II rTth(RLCA).....J I I I I I 1 I I I ItSU(RA)--\J.!- I .....Jr7tsU(ICA) 1 --.,j.!-tSU(CA) I --Il..!-l tsu(CA) II I~IIIII~I-IIL I II I~IS II IIADAS :H ROW • COL J~~;;{~~~!{~ COL TTT~:iN'I'T'I"'~'j:~~;~;"""'E~W V'HEW'I I I I --1 \.!-tsU(rd) I I I 1 ;..t-th(RHrd)I 1 I ---.J I' I 1 I I I: -J~tsU(rd) lr-th(CHrd) th(CHrd)--I \.- ---J :.r-tsU(rd) J.--..I-th(CHrd)jW-; iW~: ' __VIL I I I II~$Y- II- ta(R) -I I II i---ta(C) ----I I j.---ta(C) ----.I I I--- ta(C) ----.II. I.I ~tdis(CH) I ~tdiS(CH) I i.-+tdis(CH)

~CooZ~d~~.~RASCASAO-ASWoNOTE:sao!l\aa :a..IoddnS A.lowall\l pue II\IVt:l O!weuAaI- tw(RL) -,VIH~. ~ 4-Ir tRLCH -I ~ tw(RH) ~VIL. I· S, I l\-. L I- tc(P) -I I 1~ r-tt I I L J.-- tCLRH--'"L ... II tw(CH)P I II r--tRLCL -rI --I j+"tt I j4--tCHRL ~: : I i.-t W (CL)---..Ir-1{1 1 I' tW(CL)~ . ~Ltw(CL)--..ItlVIH II =t~ I I }~ I 11&=-----VIL I I I~ I =f 1.th(RA~....I.-.I1 I ~th(CLCA) I ,I /.--.f-th(CLCA) : I 41 th(CLCA)1 1 .I • J I j I t4-rh(RL~A)--.j I I I I I I I I . tSU(RA).....j1.!- I f,tsU(CA) I ~ ~ tsu(CA) II ---.J ~ tsu(CA) II I~I 1'T"r'T"I'T"~~:,:~~COL~: ~th(CLW) , 'h!J-tI_!I ~ ~ I I th(CLW) I I su(WRH)----"~th(RLW)----' 1 • I ~ IJ I • ~ . I -r--tsu(WCH)-.,I ~tsu(WCH)---" ,..-:--tsu(w6n--., III I I I I· ~'---""'.~I th(CLW)V'H~!i ,~!! I~ II l~VIL~~~~~I I I- -, tw(W) • I I- -I tw(W) I IJ -I tw(W).1 II _I L IIt SU(D)"1 j..!-f ~ tsu(D)..... "'-:--1I I ,I I I .JI ,. ,- th(WLD) I- 1 th(WLD)I I , »¢I:'~ OON'T CARE· VALID DATA OON'T CARE VALID DATA _~¥i;:¥X;~~IL 1 1 I . II .- _I th(CLD) I- th(CLD) I. -. th(CLD)~th(RLD) ----..JA read cycle or a read-modify-write cycle can be intermixed with write cycles as long as read and read-modify-write timing specifications are notviolated.N-f't:IIIICC ens:~!"en3 -~0 ~NCo ~U1~'en~"CCI~=i-f~ cS:n

i:Z~d~~z~+:>0Co ......"CCICCCD:3og.,- tw(RLl ',l:RAS ~I~~ SS Ti t- ~__ -..,f r--tt I. tc(Pl ..\ J. tCLRH "I ~tw(RHl~ :3I I I 0J..-tRLCL~ tw(CLl ~I 'II. tw(CLl .. I &-tCHRL--I 2;VIH II- ==- I - ~ II l-lc 4\~ :ECAS II Jtl ::!.VIL II I - I.-tt I tt-.l \.- I (j)~th(RLCAl!...L-....,l II II I r.--tW(CHl~ ~II ~th(RAl I ~th(CLCAl I I I : :.---.I--th(CLCAl III ~--. ~tSU(R~!4;'"tSU(CAl I -..-I j.!-tsu(CAl I I ....AOAS ~,:~ ~OW f~l(f';;;C;LUMN~~C;LUMN~gm:m~~ j:I tsu(rdl~ I ~tsu(WCHl.....j I tsu(rdl~ I \.-tsU(WCHl~I I I I I I I !--tsu(WRHl 11'I I t-"-tCLWL ----+I I . I I !.t-tCLWL --11 IVIH %iiiiiiiiii'tJlf I ti:l.-tW(Wl-'V I ~~tW(Wl......f~AAHHAA;';'~W . DON'T CARE N'T CAR I DON'T CAREHXXXXDQNOTE:VIL " "/.." I .. ' tRL~L "II I I : I I Hn\4 th(RLDl. I .. I I I I II ~t,"IDI ~ ," t~l.-t'"IDI ~~:~~AUDDAT~~,~AUDDAT~'ttft~I I th(WLD) I· "I ~tdiS(CH) I th(WLD) I· -1 HtdiS(CHl~~: I HI-Z I ¢ VAUDI.--ta(Cl---.jI. ta(R)-------J--.tDATA }sr-+z¢ VALID DATA }--j.---ta(Cl---iA read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not violated,Dynamic RAM and Memory Support Devices~Nen.!"-~~CD=tc

TMS4256. TMS4257262.144·8IT DYNAMIC RANDOM·ACCESS MEMORIESRAS-only refresh cycle timingCAS :1: JI ~th(RA) ~ ~\xw 'L1-1..' . ~Wr i tsu(RA)I~~ ROW~EW~~c';~AO-A7 VIH ROWVIL ~ _ _ _YYYlCXXXXX~~'U.XX;H:r.lCX_VOHQ ---------------- HI-Z --------------------VOLhidden refresh cycle timingQ):::Jc..~(I)..3o'

TMS4256, TMS4257262,144·8IT DYNAMIC RANDOM·ACCESS MEMORIESautomatic (CAS before RAS) refresh cycle timingRASCASI .....-..-------tclrdl---------·~Ir--tWIRHI~ t.-,.t-----twIRLI---...... 1 IV,H -' . -l,1VILtCLRL-~l=""----------~fIJ.---tRLCHR~:I:----""\~ ¥J1=-QVOHVOLHI-Zt/)Q)(.).:;Q)C.......0c.c.~en>...0EQ)~"'Cc:CO~

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MOSLSITMS4416. SMJ441616.384·WORD 8Y 4·81T DYNAMIC RAMAUGUST 1980 - REVISED JANUARY 1984• 16,384 X 4 Organization• Single +5·V Supply (10% Tolerance)• Performance Ranges:ACCESS ACCESS READTIME TIME ORROW COLUMN WRITEADDRESS ADDRESS CYCLE(MAX) (MAX) (MIN)'4416-12 120 ns 70 ns 230 ns'4416-15 150 ns 80 ns 260 ns'4416-20 200 ns 120 ns 330 ns• Available Temperature Ranges*:S . .. - 55°C to 1 00 °CE ... -40°C to 85°CL ... OOC to 70°C• Long Refresh Period . . . 4 milliseconds• Low Refresh Overhead Time ... As LowAs 1.7% of Total Refresh Period• All Inputs, Outputs, Clocks Fully TTLCompatible• 3-State Unlatched Outputs• Early Write or G to Control Output BufferImpedance• Page-Mode Operation for Faster Access• Low Power Dissipation. Operating ... 200 mW (TVP)Standby ... 17.5 mW (TVP)• New SMOS (Scaled-MOS) N-ChannelTechnologydescriptionREAD-MODIFY-WRITECYCLE(MIN)320 ns330 ns440 nsTMS4416 ..• NL PACKAGESMJ4416 •.. JD PACKAGE(TOP VIEW)DQlGDQ2WRASA6A5A4VSSDQ4CASDQ3AOAlA2A3VDD -" __ ..J- A7TMS4416 .•. FPL PACKAGE SMJ4416 .• .' FG PACKAGE(TOP VIEW)(TOP VIEW)(/l 02 1 18172 1 1817DQ2 016 CAS DQ2 3 A 16 CAs15 DQ3 Iii 4 15 DQ314 AO RAS 5 14 AOA613 Al A6 6 13 AlA512 A2 A5 12 A28 910118 9 1011

TMS4416, SMJ441616,384·WORD BY 4·BIT DYNAMIC RAMThe TMS4416 is offered in 18-pin plastic dual-in line and 18-pin plastic chip carrier packages. It is guaranteed foroperation from OOC to 70°C. The SMJ4416 is offered in 18-pin ceramic side-braze dual-in-line and 18-pin ceramicchip carrier packages. It is available in - 55°C to 100°C and -: 40°C to 85 °C temperature ranges. Dual-in-line packagesare designed for insertion in mounting-hole rows on 300-mil (7,62 mm) centers.operationaddress (AO through A7).C'~Q)~Co~CD3o .,'

TMS4416, SMJ441616,384·WORD BY 4·BIT DYNAMIC RAMpage modePage mode operation allows effectively faster memory access by keeping the same row address and strobing successivecolumn addresses onto the chip. Thus, the time required to setup and strobe sequential row addresses forthe same page is eliminated. To extend beyond the 64 column locations on a single RAM, the row address and RASare applied to mUltiple 16K x 4 RAMs. CAS is then decoded to select the proper RAM.power-upAfter power-up, the power supply must remain at its steady-state value for 1 ms. In addition, the RAS input mustremain high for 100 p.s immediately prior to initialization. Initialization consists of performing eight RAS cycles beforeproper device operation is achieved. .logic symbolt(14)RAM 16Kx42006~~ (13)2007/2100A2 (12)A3 (11) 0(8) A--A4 16383AS (7)A6 (6)20012/2105A7 (10)RAS (5)CAS (16)W(4)G' (1)OQl (2)OQ2 (3)OQ3 (15)OQ4 (17)23C22A.Z26tThis symbol is in accordance with IEEE Std 91/ANSI Y32.14 and recent decisions by IEEE and lEe. See explanation on page 10-1.t/)Q)to)':;Q)0........00.0.:::len... >-0EQ)~"'Cc:C'O~-0l4TEXASINSfRUMENlSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-87

TMS4416, SMJ441616,384·WDRD BY 4·BI1 DYNAMIC RAMfunctional block diagramRAS ==::jc~ ~~ _____T_IM_IN_G_& __ C_ON_T_R_O_L __ ~ADc'

TMS441616,384-WORD BY 4-BI1 DYNAMIC RAMrecommended operating conditionsPARAMETERSupply voltage, VOOSupply voltage, VSSHigh-level input voltage, VIHLow-level input voltage, VIL (see Note 2)Operating free-air temperature, T AIVOO = 4.5 VI VOO = 5.5 VTMS4416MIN NOM MAXUNIT4.5 5 5.5 V0 V2.4 4.82.4 5.8VVIK 0.8 V0 70 °CNOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic voltage levels only.electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)PARAMETERVIK Input clamp voltageVOH High-level output voltageVOL Low-level output voltageIIInput current (leakage)10 Output current (leakage)Average operating current1001during read or write cycle1002t Standby current.1003 Average refresh currentAverage page-mode1004currentt Ali typical values are at T A = 25 DC and nominal supply voltages.tVIL 2: -0.6 V on ali inputs.TEST CONDITIONS11= -15 mA,see Figure 110H = -2 mA10L = 4.2 mAVI = 0 V to 5.8 V,VOO = 5 V,All other pins = 0 VVo = 0.4 V to 5.5 V,VOO = 5 V, CAS highAt tc = minimum cycleAfter 1 memory cycle,RAS and CAS hightc = minimum cycle,RAS cycling,CAS hightc(P) = minimum cycle,RAS low,CAS cyclingTMS4416-12MIN Typt MAXUNIT-1.2 V2.4 V0.4 V±10 p.A±10 p.A54 mA3.5 5 mA46 mA46 mAenQ)(J'S;Q)C....~oc.C.:::lCJ)>-~oEQ)~"'CI:CO~

TMS441616,384·WORD BY 4·81T DYNAMIC RAMelectrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)VIKPARAMETERInput clamp voltageII ~TEST CONDITIONS-15 mA,see Figure 1VOH High-level output voltage IOH =; -2 mAVOL Low-level output voltage IOL ~ 4.2 mAVI ~ 0 V to 5.8 V,II Input current (leakage) VOO ~ 5 V,All other pins ~ 0 V10 Output current (leakage)1001Average operating currentduring read or write cycle1002:t Standby currentVo ~ 0.4 V to 5.5 V,VOO ~ 5 V, CAS highAt tc ~ minimum cycleAfter 1 memory cycle,RAS and CAS hightc ~ minimum cycle,1003 Average refresh current RAS cycling,CAS hightc(P) ~ minimum cycle,Average page-mode1004 RAS low,currentCAS cyclingTMS4416-15TMS4416-20MIN Typt MAX MIN Typt MAXUNIT-1.2 -1.2 V2.4 2.4 V0.4 0.4 V±10 ±10 IlA±10 ±10 IlA40 48 35 42 mA3.5 5 3.5 5 mA2& 40 21 34 mA25 40 21 34 mAt All typical values are at T A = 25°C and nominal supply voltages.tVIL

TMS441616,384-WORD BY 4-BIT DYNAMIC RAMswitching characteristics over recommended supply voltage range and operating free-air temperature rangeta(C)taIR)ta(G)tdis(CH)tdis(G)PARAMETERAccess time from CASAccess time from RASAccess time after GlowOutput disable time after CAS highOutput disable timeafter G highTEST CONDITIONSCL = 100 pF.Load = 2 Series 74 TTL gatestRLCL = MAX.CL = 100 pFLoad = 2 Series 74 TTL gatesCL = 100 pF.Load = 2 Series 74 TTL gatesCL =100 pF.Load = 2 Series 74 TTL gatesCL = 100 pF.Load = 2 Series 74 TTL gatesALT. TMS4416·12SYMBOL MIN MAXtCAC 70tRAC 12030tOFF 0 300 30UNITnsnsnsnsnsta(C)ta(R)tdis(G)PARAMETERAccess time from CASAccess time from RASta(G) Access time after Glow--tdis(CH) Output disable time after CAS highOutput disable timeafter G highTEST CONDITIONSCL = 100 pF.Load = 2 Series 74 TTL gatestRLCL = MAX.CL = 100pFLoad = 2 Series 74 TTL gatesCL = 100 pF.Load = 2 Series 74 TTL gatesCL = 100 pF.Load = 2 Series 74 TTL gatesCL = 100 pF.Load = 2 Series 74 TTL gatesALT.SYMBOLtCACtRACtOFFTMS4416-15 TMS4416-20MIN MAX MIN MAX80 120150 20040 500 30 0 400 30 0 40UNITnsnsnsnsnstJ)Q)(.)':;Q)C..."-oc.C.:::len>"-oEQ).~"0t:m~«a:(.)'Emt:>CTEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752654-91

TMS441616,384·WORD BY 4·BIT DYNAMIC RAMtiming requirements over recommended supply voltage range and operating free-air temperature rangeo'

TMS441616,384-WORD BY 4-BIT DYNAMIC RAMtiming requirements over recommended supply voltage range and operating free-air temperature rangePARAMETERtc(P)Page mode cycle timetc(rd) Read cycle time *tc(W) Write cycle timetc(rdW) Read-write/read·modify·write cycle timetw(CH) Pulse width, CAS high (precharge time) * *tw(CL) Pulse width, CAS low ttw(RH) Pulse width RAS high (precharge time)twiRl) Pulse width, RAS low*tw(W) Write pulse widthttTransition times (rise and fall) for RAS and CAStsu(CA) Column address setup timetsu(RA) Row address setup timetsu(D) Data setup timetsu(rd) Read command setup timetsu(WCH) Write command setup time before CAS hightsu(WRH) Write command setup time before RAS highth(CLCA) Column address hold time after CAS lowth(RA) Row address hold timeth(RLCA) Column address hold time after RAS lowth(CLD) Data hold time after CAS lowth(RLD) Data hold time after RAS lowth(WLD) Data hold time after W lowth(RHrd) Read command hold time after RAS highth(CHrd) Read command hold time after CAS highth(CLW) Write command hold time after CAS lowth(RLW) Write command hold time after RAS lowtRLCH Delay time,RAS low to CAS hightCHRL Delay time, CAS high to RAS lowtCLRH Delay time, CAS low to RAS highDelay time, CAS low to W lowtCLWL(read, modify-write· cycle only) •••Delay time, RAS low to CAS lowtRLCL(maximum value specified only to guarantee access time)Delay time, RAS low to W lowtRLWL(read modify-write-cYcie only) • * *tWLCL Delay time, W low to CAS low (early write cycle)tGHD Delay time, G high before data applied at DQtrfRefresh time intervalALT.SYMBOLtpctRCtwctRWCtcptCAStRPtRAStwptTtASCtASRtDStRCStCWLtRWLtCAHtRAHtARtDHtDHRtDHtRRHtRCHtWCHtWCRtCSHtCRP.tRSHtCWDtRCDtRWDtwcstREFTMS4416-15 TMS4416-20MIN MAX MIN MAXUNIT140 210 ns260 330 ns260 330 ns360 440 ns50 80 ns80 10,000 120 10,000 ns100 120 ns150 10,000 200 10,000 ns40 50 ns3 50 3 50 ns0 0 ns0 0 ns0 0 ns0 0 ns60 80 ns60 80 ns40 50 ns20 25 ns110 130 ns60 80 ns130 160 ns40 50 ns10 10 ns0 0 ns60 80 ns130 160 ns150 200 ns0 0 ns80 120 ns120 150 ns20 70 25 80 ns190 230 ns-5 -5 ns30 40 ns4 4 mst/)Q)CJ-SQ)c+oJ...o0.0.:1en>-...oEQ)~"Cc:::CO~

SMJ441616,384·WDRD BY 4·B11 DYNAMIC RAMrecommended operating conditionsSMJ4416PARAMETER S VERSION EVERSION UNITMIN NOM MAX MIN NOM MAXSupply voltage, VOO 4.5 5 5.5 4.5 5 5.5 VSupply voltage, VSS 0 0 VHigh-level input voltage, VIHI VOO = 4.5 V 2.4 4.8 2.4 4.8I VOO = 5.5 V 2.4 5.8 2.4 5.8Low-level input voltage, VIL (see Note 2) VIK 0.8 VIK 0.8 VOperating case temperature, TC -55 100 -40 85 °cVNOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum. is used in this data sheet for logic voltage levels only.electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)o'

SMJ441616,384·WORD BY 4·BIT DYNAMIC RAMelectrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)VIKPARAMETERInput clamp voltageTEST CONDITIONS11= -15 mA,see Figure 1VOH High-level output voltage 10H = -2mAVOL Low-level output voltage 10L = 4.2 mAVI = 0 V to 5.8 V,II Input current (leakage) VOO = 5 V,A" other pins = 0 V10 Output current (leakage)1001Average operating currentduring read or write cycle1002* Standby currentVa = 0.4 V to 5.5 V,VDO = 5 V, CAS highAt tc = minimum cycleAfter 1 memory cycle,RAS and CAS hightc = minimum cycle,1003 Average refresh current RAS cycling,CAS hightc(P) = minimum cycle,Average page-mode1004 RAS low,currentCAS cyclingt A" typical values are at TC = 25 DC and nominal supply voltages.*VIL ~ -0.6 V on a" inputs.SMJ4416-15 SMJ4416-20MIN Typt MAX MIN Typt MAXUNIT-1.2 -1.2 V2.4 2.4 V0.4 0.4 V±10 ±10 p.A±10 ±10 p.A40 48 35 42 mA3.5 5 3.5 5 mA25 40 21 34 mA25 40 21 34 mAcapacitance over recommended supply voltage range and operating case temperature range, f = 1 MHzPARAMETERSMJ4416TypT MAXCi(A) Input capacitance, address inputs 5 7 pFCi(RC) Input capacitance, strobe inputs 8 10 pFCi(W) Input capacitance, write enable input 8 10 pFCito Input/output capacitance, data ports 8 10 pFt A" typical values are at T C = 25 DC and nominal supply voltages.UNITenQ)(,).:;;Q)C...oc.C.:::Jen>-...oEQ)~"'CI:CO~CTEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-95

SMJ441616,384·WORD BY 4·B11 DYNAMIC RAMswitching characteristics over recommended supply voltage range and operating case temperature rangeta(C)PARAMETERAccess time from CASTEST CONDITIONSCL = 100 pF,Load = 2 Series 74 TTL gatesALT. SMJ4416-12UNITSYMBOL MIN MAXtCAC 70 nsta(R)ta(G)tdis(CH)tdis(G)Access time from RASAccess time after GlowOutput disable time after CAS highOutput disable timeafter GhightRLCL = MAX,CL = 100 pFLoad = 2 Series 74 TTL gatesCL = 100 pF,Load = 2 Series 74 TTL gatesCL = 100 pF,Load'" 2 Series 74 TTL gatesCL = 100 pF,Load = 2 Series 74 TTL gatestRAC 120 ns30 nstOFF 0 30 ns0 30 nsCI)::::l0-s:CD3o...-

SMJ441616,384-WORD BY 4-B11 DYNAMIC RAMtiming requirements over recommended supply voltage range and operating case temperature rangetC(PItc(rd)tC(WItc(rdWItw(CH)twlCLItwIRH)twIRL)twlWItttsulCAItsuIRA)tsu(D}tsulrdltsu(WCH)tsu(WRH)th(CLCA)ttl/RAJth(RLCA)th(CLD)th(RLD)th(WLD)thlRHrdlth(CHrd)thlCLWIthIRLW)tRLCHtCHRLtCLRHtCLWLtRLCLtRLWLtWLCLtGHDtrfPARAMETERPage mode cycle timeRead cycle time·Write cycle timeRead-write/read-modify-write cycle timePulse width, CAS high (precharge time)··Pulse width, CAS low TPulse width RAS high (precharge time)Pulse width, RAS low+Write pulse widthTransition times (rise and fall) for RAS and CASColumn address setup timeRow address setup timeData setup timeRead command setup timeWrite command setup time before CAS highWrite command setup time before RAS highColumn address hold time after CAS" lowRow address hold timeColumn address hold time after RAS lowData hold time after CAS lowData hold time after RAS lowData hold time after W lowRead command hold time after RAS highRead command hold time after CAS highWrite command hold time after CAS lowWrite command hold time after RAS lowDelay time, RAS low to CAS highDelay time, CAS high to RAS lowDelay time, CAS low to RAS highDelay time, CAS low to W low(read, modify-write-cycle only)···Delay time, RAS low to CAS low(maximum value specified only to guarantee access time)Delay time, RAS low to W low(read, modify-write-cycle only)···Delay time, W low to CAS low (early write cycle)Delay time, G high before data applied at DORefresh time interval• Note: All cycle times assume tt = 5 ns,•• Page mode only .•• 'Necessary to insure IT has disabled the output buffers prior to applying data to the device.ALT.SMJ4416·12UNITSYMBOL MIN MAXtpc 120 nstRC 230 nstwc 230 ns,·tRWC 320 nstcp 40 nstCAS 70 10,000 nstRP 80 nstRAS 120 10,000 nstwp 30 nstT 3 50 nstASC 0 nstASR 0 nstDS 0 nstRCS 0 nstCWL 50. nstRWL 50 nstCAH 35 nstRAH 15 nstAR 85 nstDH 40 nstDHR 100 nstDH 30 nstRRH 10 ns .tRCH 0 nstWCH 40 nstWCR 100 nstCSH 150 nstCRP 0 nstRSH 80 nstCWD 120 nstRCQ 20 50 nstRWD 170 nstwcs -5 ns30 nstREF 4 mstin a read-modify-write cycle, tCLWL and tsu(WCH) must be observed. Depending on the user's transition times, this may require additional CAS low time tW(CL)'*In a read-modify-write cycle, tRLWL and.tsu(WRH) must be observed. Depending on the user's transition times, this may require additional RAS low time twIRL)'enQ)U.s:Q)o~oc.C.:::len>...oEQ):!"0t:C'O:!cd:a:u-eC'Ot:>oTEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-97

SMJ441616,384·WORD BY 4·B11 DYNAMIC RAMtiming requirements over recommended supply voltage range and operating case temperature rangeQ)::sc..s:CD3o ...

1MS4416, SMJ441616,384·WORD BY 4·B11 DYNAMIC RAMPARAMETER MEASUREMENT INFORMATIONVeeREMAINING {I IN~~;~OUTPUT(S)OPENNOTE:Each input is tested separately,FIGURE 1 -INPUT CLAMP VOLTAGE TEST CIRCUITread cycle timingAO-A7DQGVOLVIHVILHi-Z ------4tVAll D OUTPUT }).-------ta(R)I- .1 ,Ita(G)-r--t ~ tdis(G)II'\ tenQ)CJ'S;Q)C~o0.0.::::Jen>...oEQ)~"'Cc:CO~«Il:CJ'ECOc:>CTEXASINSTRUMENTS,POST OFFICE BOX 225012 • DALLAS, TEXAS 752654-99

TMS4416, SMJ441616,384-WORD BY 4-BIT DYNAMIC RAMearly write cycle timingc

TMS4416, SMJ441616,384·WORD BY 4·BIT DYNAMIC RAMwrite cycle timingAO-A7DOtJ)Q)o'S;Q)c...oc.C.::::Jen>...oEQ)~"Cc:CO~

TMS4416, SMJ441616,384-WORD BY 4-BI1 DYNAMIC RAMread-write/read-modify-write cycle timingAO-A7DQVILIVOL .........¥...~..K...&..JI~-¥. ......._......'" ~ ___;.,,;.;.,,;;__ta(GI~I~::--------~{,..',-__ tI~ tGHDI4-102TEXASINsrRuMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

z~~~z@towRAs-{rCASAO·A7wDQG:::'.!AUtt-VIH i~ ~i 1\.VIL : (, tRLCH II I I $ I :'-tW(RH).J--i '-tt I. tc(P) , .. I I--tCLRH---I I II I II I I I' II ..... tRLCL...:...I I ~tw(CH) J4-tCHRL----II I I ---1

C3~~.....o.po.3n_;z~~;;;c ~ ;O~d~~J>!TI:=z-~ ~xl;'"mRASCASAO-A7wVIHVILVILS93!J\aa :uoddnS AJOW811\1 pue lI\I"l:I 3!weuAa'tJ --4Q)tCCD.?'3:Wen3 =~0 ~~c..CD~:e;;c ..=encae..;:t.'CD 03:n-

1:'QltC(()3oc..(()C3~~n_:::Z~~~;;; c:~~~~tT'JrZ~~XG;enUlf'o0'1AAsCASVIHAO-A7VILViVIH~ tw(RLJ t~VIL I I I~ ,.-tt to- tc(PJ .1 I'- tcLRH -I :'tW(RHJ.II 1:== tRLCL ~ tw(CLJ .., I ~ tw(CLJ -, IJ.- tcHRL-./v," : I 11- ~'R'C"' Jt II Y.f ~VIL I ~ I /.-tt ~ ~ ti.-tt II th(RLCAJ T--i I r-- tw(CHJ~1 I I He-- tW(CHJ----..jth(RAJ ~ th(CLCAJ I ' I..---.t- th(CLCAJ I IVIHVILI tsu(RAJ -../ *tsU(CAJ I --.I H-tsU(CAJ I !---::L........".-i= :oL.KAAAAAAXXXX XAXAAJ\X,.,F 4XAAAAAJ\AXA./\J\A,Ir=l~--I/-tsu(DIIVIH/VOH . ~DO )()OO()(pgJ.Tf5.~! ; VALID , A+ =4iA X A J\J\XXJ\XJ\..1:k:---....VIL/VOL __ ~~ ~, __ OUTPUT!I I , Ita(GJ~ r-+-tGHD ta(GJ~ r--t-tGHDI I I IG :::------t t 't tk::-------NOTE: A read cycle or a write cycle can be intermixed with read-modify-write cycles as long as read and write timing specifications are not violated.Dynamic RAM and Memory Support DevicesCi3Qlc..3oc..~~s'r+3'5'tCenWco~:e=C)C=

TMS4416, SMJ441616,384·WORD BY 4·BIT DYNAMIC RAMRAS-only refresh timingRASI. tc(rd) -I. I IVIH --------------:111' I'W'RLI~J= ~VIL N- -:fi i"----IIl~tw(RH)~---..t t4- ttI III~l4-tt. 'II I .. I ~AO·A7Q)~Cos:(t)3o ...

MOSLSITMS446465,536-WORD BY 4-BIT DYNAMIC RAMNOVEMBER 19B3 - REVISED JANUARY 1984• 65,536 X 4 Organization• Single +5-V Supply (10% Tolerance)• JEDEC Standardized Pin-Out• Pin-Out Identical to TMS4416(16K X 4 Dynamic RAM)• Performance Ranges:DEVICEACCESSTIMEROWADDRESS(MAX)ACCESSTIMECOLUMNADDRESS(MAX)READORWRITECYCLE(MIN)READ-MODIFY-WRITECYCLE(MIN)TMS4464 ... JL OR NL PACKAGE(TOP VIEW)GDOlVSSDQ4CASDQ3ADAlA2A3A7TMS4464-10TMS4464-12TMS4464-15TMS4464-20100 ns120 ns150 ns200 ns60 ns70 ns85 ns12d ns200 ns230 ns260 ns330 ns270 ns310 ns345 ns435 ns• Long Refresh Period ... 4 ms (MAX)• Low Refresh Overhead Time ... As Low As 1.3% of TotalRefresh Period• On-Chip Substrate Bias Generator• All Inputs, Outputs, and Clocks Fully TTL Compatible• 3-State Unlatched Output• Early Write or G to Control Output Buffer Impedance• Page-Mode Operation for Faster Access• Power Dissipation As Low As:Operating ... 250 mW (TVP)Standby ... 12.5 mW (TVP)• RAS-Only Refresh Mode• Hidden Refresh Mode• CAS-Before-RAS Refresh Mode (Optional)descriptionPIN NOMENCLATUREAO·A7Address InputsCASColumn Address StrobeD01·D04 Data·ln/Data·OutGOutput EnableRASRow Address StrobeVDD+5-V SupplyVSSGroundINWrite EnableThe TMS4464 is a high-speed, 262, 144-bit dynamic random-access memory, organized as 65,536 words of fourbits each. It employs state-of-the-art SMOS (scaled MOS) N-channel double-level polysilicon gate technology for veryhigh performance combined with low cost and improved reliability.rnQ)Co)·SQ)c....o0.0.::::1(J)...>-oEQ)~"Ct:ca::?E

TMS446465,536·WORD BY 4-BIT DYNAMIC RAMoperationaddress (AO through A7)Sixteen address bits are required to decode 1 of 65,536 storage locations. Eight row-address bits are set up on pinsAO through A7 and latched onto the,chip by the row-address strobe (RAS). Then the eight column-address bits areset up on Pins AO through A7 and latched onto the chip by the column-address strobe (CAS). All addresses mustbe stable on or before the falling edges of RAS and CAS. RAS is similar to a chip enable in that it activates the senseamplifiers as well as the row decoder. CAS is used as a chip select activating the column decoder and the input andoutput buffers.write enable (W)The read or write mode is selected through the write enable (W) input. A logic high on the W input selects the readmode and a logic low selects the write mode. The write enable terminal can be driven from standard TTL circuitswithout a pull-up resistor. The data input is disabled when the read mode is selected. When W goes iow prior to CAS,data-out will remain in the high-impedance state for the entire cycle permitting common 1/0 operation.data-in (DO 1-004)Data is written during a write or read-modify write cycle. Depending on the mode of operation, the falling edge ofCAS or W strobes data into the on-chip data latches. These latches can be driven from standard TTL circuits withouta pull-up resistor. In an early-write cycle, W is brought low prior to CAS and the data is strobed in by CAS with setupand hold times referenced to this signal. In a delayed write or read-modify write cycle, CAS will already be low, thusthe data will be strobed in by Vi with setup and hold times referenced to this signal. In delayed or read-modify-write,G must be high to bring the output buffers to high impedance prior to impressing data on the I/O lines.data-out (001-004)Q)::JQ.s:(1)3o...'

TMS446465,536-WORD 8Y 4-81T DYNAMIC RAMpage-modePage-mode operation allows effectively faster memory access by keeping the same row address and strobing randomcolumn addresses onto the chip. Thus, the time required to setup and strobe sequential row addresses for the samepage is eliminated. The maximum number of columns that can be addressed is determined by tw(RL), the maximumRAS low pulse width. For example, with a minimum cycle time (tc(P) = 110 ns) approximately 90 of the 256 columnscan be accessed.power-upTo achieve proper device operation, an initial pause of 200 p.s is required after power-up followed by a minimum ofeight initialization cycles.logic symboltRAM 64K X 4(14)AO2008/2100(13)A1A2 (12)A3 (11) 0(8) A--A4 65535A5 (7)(6)A6(10)A7RAS (5)CAS (16)W (4)G (1)OQ1 (2)OQ2 (3)OQ3 (15)OQ4 (17)23C22A.Z26t/)Q)(,)oSQ)C....~0c..c..:::sen>-~0EQ)~"CCro~-Ct This symbol is in accordance with IEEE Std 91/ANSI Y32.14 and recent decisions by IEEE and IEC. See explanation on page 10-1.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-109

TMS446465,536-WORD BY 4-BIT DYNAMIC RAMfunctional block diagramo-s:Q)::::Jc..s:CD3o ...-

TMS446465,536·WORD BY 4·BIT DYNAMIC RAMelectrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)PARAMETERTEST CONDITIONSTMS4464-10TMS4464-12MIN TVpt MAX MIN TVpt MAXVOH High-level output voltage 10H = -5 mA 2.4 2.4 VVOL Low-level output voltage 10L = 4.2 mA 0.4 0.4 VIIInput current (leakage)VI=O V to 5.8 V, VOO=5 V,All other pins = 0 V to 5.8 VVa = 0 V to 5.5 V,UNIT±10 ±10 p,A10 Output current (leakage) VOO = 5 V, ' ±10 ±10 p,A1001Average operating currentduring read or write cycle1002 Standby currentCAS hightc = minimum cycle 80 TBO 70 TBO mAAfter 1 memory cycle,RAS and CAS hightc = minimum cycle,2.5 5 2.5 5 mA1003 Average refresh current RAS cycling, 65 TBO 55 TBO mACAS highItc(P) = minimum cycle,1004 Average page-mode current RAS low, 55 TBO 45 TBO mACAS cyclingelectrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)PARAMETERTEST CONDITIONSTMS4464-15TMS4464-20MIN TVPt MAX MIN TVpt MAXVOH High-level output voltage 10H = -5 mA 2.4 2.4 VVOL Low-level output voltage 10L = 4.2 mA 0.4 0.4 VIIInput current (leakage)VI=O V to 5.8 V, VOO=5 VAll other pins = 0 V to .5.8 VVa = 0 V to 5.5 V,UNIT±10 ±10 p,A10 Output current (leakage) VOO = 5 V, ±10 ±10 p,A1001Average operating currentduring read or write cycle1002 Standby currentCAS hightc = minimum cycle 60 TBO 50 TBO mAAfter 1 memory cycle,RAS and CAS hightc = minimum cycle,2.5 5 2.5 5 mA1003 Average refresh current RAS cycling, 50 TBO 40 TBO mACAS hightc(P) = minimum cycle,1004 Average page-mode current RAS low, 40 TBO 30 TBO mACAS cycling........oc.C.::len... >-oE(1)2"'Cc::CO2

TMS446465,536·WORD BY 4·BIT DYNAMIC RAMcapacitance over recommended supply voltage range and operating free·air temperature range. f1 MHzPARAMETERTMS4164Typt MAXUNITCi(A) Input capacitance, address inputs 4 7 pFCi(RC) Input capacitance strobe inputs 8 10 pFCi(W) Input capacitance, write enable input 8 10 pFCilo Output capacitance 8 10 pFt All typical values are at T A = 25 DC and nominal supply voltages,~witching characteristics over recommended supply voltage range and operating free-air temperature rangec-

1MS446465,536·WORD BY 4·B11 DYNAMIC RAMtiming requirements over recommended supply voltage range and operating free-air temperature rangeALT. TMS4464-10 TMS4464-12. PARAMETER UNITSYMBOL MIN MAX MIN MAXtc(P) Page mode cycle time tpc 110 130 nstc(PM) Page-mode cycle time (read-modify-write cycle) tpCM 180 210 nstc(rd) Read cycle time t tRC 200 230 nstc(W) Write cycle time twc 200 230 nstc(rdW) Read-write/read-modify-write cycle time tRWC 270 310 nstw(CH)P Pulse duration, CAS high (page mode) tcp 40 50 nstw(CH) Pulse duration, CAS high (non-page mode) tCPN 40 50 nstw(CL) Pulse duration, CAS low:!: tCAS 60 10,000 70 10,000 nstw!RH) Pulse duration, RAS high (precharge time) tRP 90 100 nstWIRL) Pulse duration, RAS low§ tRAS 100 10,000 120 10,000 nstw(W) Write pulse duration twp 35 40 nstt Transition times (rise and fall) for RAS and CAS tT 3 50 3 50 nstsu(CA) Column address setup time tASC 0 0 nstsu(RA) Row address setup time tASR 0 0 nstsu(D) Data setup time tDS 0 0 nstsu(rd) Read command setup time tRCS 0 0 nsEarly write command setuptsu(WCUtime before CAS lowtwcs 0 0nstsu(WCH) Write command setup time before CAS high tCWL 30 40 nstsu(WRH) Write command setup time before RAS high tRWL 30 40 nsth(CLCA) Column address hold time after CAS low tCAH 20 20 nsth(RA) Row address hold time tRAH 15 15 nsth(RLCA) Column address hold time after RAS low tAR 60 70 nsth(CLD) Data hold time after CAS low tDH 30 35 nsth(RLD) Data hold time after RAS low tDHR 70 85 nsth(WLDI Data hold time after W low tDH 30 35 nsth(CHrd) Read command hold time after CAS high tRCH 0 0 nsth(RHrd) Read command hold time after RAS high tRRH 10 10 nsth(CLW) Write command hold time after CAS low tWCH 30 35 nsth(RLW) Write command hold time after RAS low tWCR 70 85 nstRLCHR Delay time, RAS low to CAS high' tCHR 20 25 nstRLCH Delay time, RAS low to CAS high tCSH 100 120 nstCHRL Delay time, CAS high to RAS low tCRP 0 0 nstCLRH Delay time, CAS low to RAS high tRSH 60 70 nstCLWLDelay time, CAS low to W low(read-modify-write cycle only)#tCWD 95 105 ns'tCLRL Delay time, CAS low to RAS low' tCSR 20 25 nsDelay time, RAS low to CAS lowtRLCL (maximum value specified only tRCD 25 40 25 50 nsto guarantee access time)tRLWLDelay time, RAS low to W low(read-modify-write cycle only)#tRWD 135 155 nstGHDDelay time, G high beforedata applied at DQtGDD 30 30trf Refresh time interval tREF 4 4 mst All cycle times assume tt ~ 5 ns.~ In a read-modify-write cycle, tCLWL and tsu(WCH) must be observed. Depending on the user's transition times, this may require additional CAS low time(tw(CL))'§ In a read-modify-write cycle, tRLWL and tsu(WRH) must be observed. Depending on the user's transition times, this may require additional RAs low time~RL))', CAS-before-l'fAS refresh option only./I G must disable the output buffers prior to applying data to the device.nsCI)Q)(.)':;:Q)C..."-oc.C.:::len>"-oEQ):2:"Cs:::ca:2:

TMS446465,536-WORD BY 4-BIT DYNAMIC RAMc-

TMS446465,536·WORD BY 4·BIT DYNAMIC RAMread cycle timingAO- A7DQ"'1~1---------tC(rd)--------.l·lI I~ twIRL) .1 1 I:::1 t ~~--~ I-- tt !.---tCLRH----.f j.-tw (RHI--1I J.-tRLCL~tw(CL)~ r-TtCHRL----,I I~ tRLCH ::::I \.-1 tt::: -i LL- ,,,'RAl ~II I I 1I 14-:- th(RLCA)---.f I Ith(RA)~ J.-- _I IJ I I II I I ---, ~ tsu(CA) I I~::~COLUMNm€o$fcZRUXXX", _____ _I I!_ _I l...r ... th(RHrd)1 I ..--.,- th(CLCA) I I II tsU(rd)+--i I -r ~ th(CHrd) _IV·7Vi= I~v::>O&s\c*~~ : :"iXX&sz~~ii@I t--ta(c)~ II I "'1~1----4·M-I- tdis(CH)I~::----I --Hi-Z-----~¢ VALID OUTPUT }).-------I~ ta(R) .1 . Ita(G)~~tdis(G)II~p::.-I -----Jtl.!.----tJ..i.-'--tw -(-CH-)-.-"':1L-t:o0.0.:JCJ)>-~oEQ)2"Cr::::CO2«a:(.)'ECOr::::>CTEXASINsrRuMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-115

TMS446465,536·WORD BY 4,BIT DYNAMIC RAMearly write cycle timingQ)::JQ.s:CD3o ..,-

TMS446465,536-WORD BY 4-BIT DYNAMIC RAMwrite cycle timingAO-A7DQVIHVIL-------ttGHD~-~oCoCo:JCI)>~oEQ)~"'0c:CO~~a:(.)"eCOc:>CTEXASINSfRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752654-117

TMS446465,536·WORD BY 4·BIT DYNAMIC RAMread-write/read-modify-write cycle timingc

RASCAS----{! '.,ReIVIH i~VIL I tRLCH II, isVIHVIL'CIIICCCD:3o0-CD..CDIII0-n

"Vo~.... f"I\)on_~;;;z~~d. ~~tTl~z~~x&;o:;c:::~'" m'"RASCASAO·A7sao!l\aa ~Joddns AJowaU\l pue U\I"~::J!weuAaI. twiRL) '\I r tRLCH ., I f4'"twIRHI-,~:: 1 H ¥---, --&...1\--f [It I- tC(PI I ·1 ;--tCLRH~ II _tRLCL -rl I ~--+tWICHIP "I-tCHRL.-.fI! I J--twlcL)~nl 11"-,.,,,,---1 ~t--twICL)--I,,~VIL , I:r I I Ith(RAIM : r-;- th(CLCAI ! I hth(CLCA) I . I Hth(CLCAIIII ~th(RLCAI""" I ,I I I 'I' II""':JJJi.:;::, ! ±:"",: ~VIH I I \l tl -I ~ r' ~ ~...u.----:'H ~'g(~~:1~;£t5;~~~~DE!""I®!""IT~~':.r-~~r"~~"Il""'Il"'rIL I H I I I I "th(CLWI 1 ~ '_II I ~ th(CLWI r tsulWRHI~....--th(RLWI-----f I I I I " II I _I ~ tsulWCHI--jI J+-- tsulWCHI~ r.-- tsulWCHI--t I'I ~'I I ~I I ~""--I. ~$..I~h(~CLWI ~VIH y~~:~~n.A I ~'nA~2~:'A 'I ~I J\e~ I I ~~ ~~AA~N'l).W v W~~;"\yE 1~~~~~~~~~~R~I~~~~c~~~DQIL , I I . I I I ,I I ~twlWI I ~ twlWI.-f I I+tWIWl..lil I I' ~I'tsulOlj ~I tSUIOI--J---i I tsulOl I I II I I_I 'I th(WLDI I 4------!-th(WLDI ,j4- t h(WLDI.jVIH I.J. 4 J. J.. ' vJr I ~VIL ;yx:Y:Y~;r IN~UI f~~::':;~ 'I;;;~~ f:~om;~~~ ~:P~~ 2(V\iDs~TJfRiOO'CII)=-4eQ !.TI3:CD U'I enCo\)~30 c.=~. =CD :e~:IE 0a· = CIICDC'l-< =C'l - =3:G: I \...-.--4- th(CLDI :. .1 th(CLDI l. .1 th(CLDI~th(RLDI-...!~tGHDVIH .; \ ~vlLJNOTE:A read cycle or a read·modify write cycle can be intermixed with write cycles as long as read and read-modify-write timing specifications are not violated.

~~~n_;;;z~~. ~~tTlg ;O~d ;;;t::=z~@x~IV '"OJ'"t-"N-"RAs VIH ~ tw(RLI ~ . ,VIL I I 1~ r-- tt ,.. tt(PI ~I I'- tCLRH ~I :... tw(RHI..II l:---:tRLCL~tW(CLI -1 I ~ tw(CLI -I IJ.-tcHRL....jd - V'H I '"N- '''",CH', I I J?I-CAS 'I I Jt ~ I ~VIL I' \..-tt' ---..' u..-tt I, !..--th(RLCAI ~ I ~ tw(CHI-. 1 I I r.-- tw(CHI---iHth(RAI ~th(CLCAI ( (~th(CLCAI , I--.II _rtSu(RAI -..I ~tSU(CAI ( -.I k-tsU(CAI I IV'H~~ ~ ~ ~'~ ,tsU(rdl~ I tsu(WCHI ~ _, tsu(rdl~ I tsu(WCHI =- ~I 1 (. 1 . I' tsu(WRHIAO· A7 VIL ROW COLUMN~~1 ~~ COLUMN ~~NJgA3000000cWVIHVIL,. th(RLWI -i II "" th(CLWI I ~I I I--th(CLWI _I----IInmx1' : tt:"'W'1

TMS446465,536·WORD BY 4·BIT DYNAMIC RAMRAS·only refresh cycle timingautomatic (CAS before RAS) refresh cycle timingQ)::JC.s:CD3o"'I'

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MEMORY SUPPORTLSITMS4500ADYNAMIC RAM CDrHROLLERJANUARY 1982 - REVISED APRIL 1983• Controls Operation of 8K/16K/32K/64KDynamic RAMs• Creates Static RAM Appearance• One Package Contains Address Multiplexer,Refresh Control, and Timing Control• Directly Addresses and Drives Up to 256KBytes of Memory Without External Drivers• Operates from Microprocessor Clock- No Crystals, Delay Lines, or RC Networks- Eliminates Arbitration Delays• Refresh May Be Internally or ExternallyInitiated• VersatileStrap-Selected Refresh RateSynchronous, Predictable RefreshSelection of Distributed, Transparent, andCycle-Steal Refresh ModesInterfaces Easily to Popular Microprocessors• Strap-Selected Wait State Generation forMicroprocessor/Memory Speed Matching• Ability to Synchronize or Interleave Controllerwith the Microprocessor System(hicluding Multiple Controllers)• Three-State Outputs Allow MultiportMemory Configuration• Performance Ranges of 150 ns/200 nsf250 nsdescriptionTMS4500A ... Nl PACKAGEClKRDYRENlcsALERASORASl(TOP VIEW)vccREFREQThe TMS4500A is a monolithic DRAM system controller designed to provide address multiplexing. timing. controland refresh/access arbitration functions to simplify the interface of dynamic RAMs to microprocessor systems.The controller contains a 16-bit multiplexer that generates the address lines for the memory device from the 16 systemaddress bits and provides the strobe signals required by the memory to decode the address. An 8-bit refresh countergenerates the 256-row addresses required for refresh.A refresh timer is provided that generates the necessary timing to refresh the dynamic memories and assure dataretention.The TMS4500A also contains refresh/access arbitration circuitry to resolve conflicts between memory access requestsand memory refresh cycles. The TMS4500A is offered in a 40-pin. 600-mil dual-in-line plastic package and is guaranteedfor operation from 0 DC to 70 DC.ACRACWCASRAOCAOMAOMAlCAlRAlRA2CA2MA2GNDTWSTFSOFSlRA7CA7MA7MA6CA6RA6RA5CA5MA5RA4.....o0.0.~(J)... >oEQ)2"CCCO:E

TMS4500ADYNAMIC RAM CONTROLLERBLOCK DIAGRAMRAO·RA7 1..----'1MUlTIPLEXER.c-

TMS4500ADYNAMIC RAM CONTROLLERpin descriptions (continued)CSInputChip Select - A low on this input enables an access cycle. The trailing edge ofALE latches the chip select input.REN1INPUTRAS Enable 1 - This input is used to select one of two banks of RAM via theRASO and RAS1 outputs when chip select is present. When it is low, RASO isselected; when it is high, RAS1 is selected.InputAccess Control, Read; Access Control, Write - A low on either of these inputscauses the column address to appear on MAO - MA7 and the column addressstrobe. The rising edge of ACR or ACW terminates the cycle by ending RAS andCAS strobes. When ACR and ACW are both low, MAO - MA7, RASa, RAS1, andCAS go into a high-impedance (floating) state.ClKInputSystem Clock - This input provides the master timing to generate refresh cycletimings and refresh rate. Refres.h rate is determined by the TWST, FS1, FSOinputs.RASO, RAS1CASROYTWSTFSO, FS1I nput/OutputOutputOutputOutputInputInputsRefresh Request - (This input should be driven by an open-collector output.)On input, a low·going edge initiates a refresh cycle and will cause the internalrefresh timer to be reset on the next falling edge of the ClK. As an output, alow-going edge signals an internal refresh request and that the refresh timer willbe reset on the next low-going edge of ClK. REF REO will remain low until therefresh cycle is in progress and the current refresh address is present on MAO-MA7 .(Note: REFREO contains an internal pull-up resistor with a nominal resistanceof 10 kilohms.)Row Address Strobe - These three-state outputs are used to latch the row addressinto the bank of DRAMs selected by REN1. On refresh both signals are driven.Column Address Strobe - This three-state output is used to latch the columnaddress into the DRAM array.Ready - This totem-pole output synchronizes memories that are too slow toguarantee microprocessor access time requirements. This output is also used toinhibit access cycles during refresh when in cycle-steal mode.TiminglWait Strap - A high on this input indicates a wait state should be addedto each memory cycle. In addition it is used in conjunction with FSO and FS1 todetermine refresh rate and timing.Frequency Select 0; Frequency Select 1 - These are strap inputs to select Modeand Frequency of operation as shown in Table 1.(I)Q)U'S;Q)C......oc.C.::JCJ)...>oEQ)2"CCCO2«a:u'ECOc>C14TEXAS INSTRUMENTS 4-127INCORPORATED

TMS4500ADYNAMIC RAM CONTROLLERTABLE 1 - STRAP CONFIGURATIONWAITSTRAP INPUT MODESSTATESCLOCK.FOR MINIMUM CYCLESMEMORY REFRESH ClK FREO. REFRESH FOR EACHTWST FS1 FSO ACCESS RATE (MHz) . FREO. (kHz) REFRESHl l It 0 EXTERNAL - REFREO 4l l H 0 elK -;. 31 1.984 64·95 t 3l H l 0 elK -;. 46 2.944 64· 85* 3l H H 0 elK -;. 61 3.904 64·82§ 4H l l 1 elK -;. 46 2.944 64·85 t 3H l H 1 elK ~. 61 3.904 64·80* 4H H l 1 elK.:- 76 4.864 64· 77* 4H H H 1 elK -;. 91 5.824 64· 88~ 4o'

TMS4500ADYNAMIC RAM CONTROLLERarbiterThe arbiter provides two operational cycles: access and refresh. The arbiter resolves conflicts between cycle requestsand cycles in execution, and schedules the inhibited cycle when used in cycle·steal mode.timing and control blockThe timing and control block executes the operational cycle at the request of the arbiter. It provides the DRAM arraywith RAS and CAS signals. It provides the CPU with a ROY signal. It controls the multiplexer during all cycles. Itresets the refresh rate generator and decrements the refresh counter during refresh cycles.absolute maximum ratings over operating ambient temperature range (unless otherwise noted) tSupply voltage range, VCC (see Note 1) ......................................... -1.5 V to 7 VInput voltage range (any input) (see Note 1) .....................................• -1.5 V to 7 VContinuous power dissipation ............................................... __ . _ _ _ 1_2 WOperating ambient temperature range .......... ___ . __ ........ _.. __ . _ . __ .. ____ . _. O°C to 70°CStorage temperature range .. ________ .... __ . __ ... __ .. ___ . _..... _ . _ • __ . __ . _ _ -65°C to 150°Crecommended operating conditionsPARAMETER MIN NOM MAX UNITSupply voltage, Vee 4.5 5 5.5 VHigh-level input voltage, VIH 2.4 6 Vlow-level input voltage, Vil -1 + 0.8 VOperating ambient t temperature, T A 0 70 °et Stres&es beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only and functionaloperation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specificationis not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.t The algebraic convention, vyhere the more negative limit is designated as minimum, is used in this data sheet for logic voltage levels only.NOTE 1: Voltage values are with respect to the ground terminal.electrical characteristics over recommended operating ambient temperature range (unless otherwise noted)PARAMETER TEST CONDITIONS MIN Typt MAX UNITV OHMAO-MA7, ROY 2.4High-levelIOH = -.1 mA Vee = 4.5 VRASO,RAS1,eAS2.7output voltageREFREQ IOH = 100 ",A Vee = 4.5 V 2.4V~OL low-level output voltage IOl = 4 mA Vee = 4.5 V 0.4 VIIHHigh-level REFREQ 100VI = 5.5 Vinput current All others10",AIIIlow-level REFREQ -1.25 mAVI = OVinput current All others-10 p.AIOZ Off-state output current V O =Ot04.5V Vee = 5.5 V ±50 ",Alee Operating supply current TA = oDe 100 140 mAe i Input capacitance VI = OV, f = 1 MHz 5 pFeo Output capacitance Vo = 0 V, f = 1 MHz 6 pF+oJ..oc.C.::::Jen~oEQ):E"CCCO:Ecd:a:to)"eCOc>ot All typical values are at VCC = 5 V, T A = 25 DC except where otherwise noted.184TEXAS (NSTRUMENTS4-129INCORPORATED

TMS4500ADYNAMIC RAM CONTROLLERtiming requirements over recommended supply voltage range and operating ambient temperature rangeC'

TMS4500ADYNAMIC RAM CONTROLLERswitching chara~teristics over recommended supply voltage range and operating ambient temperature range(see Figure 1)tAEl-RElPARAMETERTime delay, ALE low toRAS starting lowTESTTMS4500A-15 TMS4500A-20 TMS4500A-25CONDITIONS MIN MAX MIN MAX MIN MAX30 40 50tt(REl) RAS fall time 15 20 25Cl = 160pFTime delay, row address validtRAV-MAV40 50 60to memory address validtAEH-MAVtAEl-RYltAEl-CElTime delay, ALE high tovalid memory addressTime delay, ALE to ROY start.inglow (TWST = 1 or refresh in progress)Time delay, ALE low to CASstarting low55 70 90Cl = 40 pF 20 25 3560 150 75 200 100 250Time delay, ALE high to RAStAEH-REH25 3040starting highCl = 160pFttIMAV) Address transition time 15 20 25tACl-MAX Row address hold from ACX low 15 20 25Time delay, memory addresstMAV-CElvalid to CAS starting low0 0 0ttlCELl CAS fall time Cl = 320 pF 15 20 25Time delay, ACX low to CAS'tACl-CElstarting low50 90 65 130 85 165tACH-REHTime delay, ACX to RASstarting highCl = 160 pF30 40 50ttIREH) RAS rise time 15 20 25Time delay, ACX high to CAStACH-CEHstarting high5 30 10 40 15 50ttICEH) CAS rise time Cl =320 pF 30 35 45Column address hold fromtACH-MAXACX highCl = 160 pF 15 20 25tCH-RYHtRFl-RFltCH-RFltCl-MAVtCH-RRltMAV-RRltCl-RFHtCH-RFHtCH-RRHtCH-MAXTime delay, ClK high to ROY startinghigh lafter AcX low) Isee Note 9)Time delay, REFREO external tillsupported by REFREO internalTime delay, ClK high till REFREOinternal starting lowTime delay, ClK low till refreshaddress validTime delay, ClK high tillrefresh RAS starting lowTime delay, refresh addressvalid till refresh RAS lowTime delay, ClK low to REF REOstarting high 13 cycle refresh)Time delay, ClK high to REFREOstarting high 14 cycle refresh)Time delay, ClK high to refreshRAS starting highTime delay, refresh address holdafter ClK high.Cl = 40 pF 35 45 60Cl = 40 pF25 30 3030 35 4575 100 12510 50 15 60 20 805 5 5Cl = 160pF 45 55 7545 55 755 35 10 45 10 6015 20 25UNITnsrJ)Q)(.)'>Q)C.....oa.a.::::Jen>...oEQ)~"Cc:CO~«a:(.)'ECOc:>CNOTE 9: ROY returns high on the rising edge of ClK. If TWST = 0, then on an access grant cycle ROY goes high on the same edge that causes access RASlow. If TWST = 1, then ROY goes to the high level on the first rising ClK edge after ACx goes low on access cycles and on the next rising edgeafter the edge that causes access RAS low on access grant cycles (assuming ACX low).34TEXAS INSTRUMENTS 4-131INCORPORATED

TMS4500ADYNAMIC RAM CONTROLLERswitching characteristics over recommended supply voltage range and operating ambient temperature range(see Figure 1) (continued) .C'

TMS4500ADYNAMIC RAM CONTROLLERaccess cycle timingAOW,RENlCOL,CSMAO-MA7RDYrefresh request timingREF REO(EXTERNAL)REFREQ(INTERNAL)\ / \~o0.0.:::lCJ)>-~oEQ)~"'Ct:co~«a:(.)'Ecot:>-C...If \'CH'''+--,\l4TEXAS (NSTRUMENTSINCORPORATED4-133

TMS4500ADYNAMIC RAM CONTROLLERready timing (ACX during ClK high) (see notes 10 thru 13)ClKALEROY~ ~---_----I'\ !~ r--tACl-Cl--l'AEL_~ -t 'ACL-RYH"\ 1-----C'

TMS4500ADYNAMIC RAM CONTROLLERoutput tristate timingOUTPUTSrefresh cycle timing(three cycle)refresh cycle timing(four cycle)\;-'CAV-CEL(I)(1)(,)'S;(1)c......0C.C.:len... >0E(1).~'t:JCCO~«a:(,)'ECOc>C~lMAVARl~t On the access grant cycle following refresh, the occurrence of CAS low depends on the relative occurrence of ALE low to ACX low. If ACX occurs priorto or coincident with ALE then CAS and address mUltiplexing are timed from the ClK high transition with tREl-MAX delay from RAs low to address notvalid. If ACX occurs 20 ns or more after ALE, then CAS and address multiplexing are timed from the ClK low transition.84TEXAS INSTRUMENTS4-135INCORPORATED

TMS4500ADYNAMIC RAM CONTROLLERtypical access/refresh/access cycle(three cycle, TWST = 0)Nz:z------ - :J....JoUMC'oe::4-136TEXAS INSTRUMENTSINCORPORATED184

TMS4500ADYNAMIC RAM CONTROLLERtypical access/refresh/access cycle(four cycle, TWST = 0)I-z«a:(!).,.----Ul --Ulw()()«I~Ul --Wa:u.. ~wa:~.,.----Ul(J)w()--()«----- - z --- ----~:J...J--- -0()---------- - --------- ---- - I(J)w0:u..w0:--- - z~,--- -:J...J0()-------- ---- --C/)Q)(J"SQ)C+oJ...0C.C.~C/'J... >0EQ)~"CCca~

TMS4500ADYNAMIC RAM CONTROLLERtypical access/refresh/access cycle(three cycle, TWST = 1)z~::>..JUo___________ _.0'

TMS4500ADYNAMIC RAM CONTROLLERtypical access/refresh/access cycle(fou r cycle, TWST = 1)z~:;)--loUf-Z~a: vC~ w--l--lu ~---I~x~~I~15Ii>-0a:Texas Instruments reserves the right to make changes at any time in order to improve design and to supply the best product possible.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752654-139

c-

Alphanumeric Index, Table of Contents, Selection GuideInterchangeability GuideGlossary/Timing Conventions/Data Sheet StructureDynamic RAM and Memory Support DevicesDynamic RAM ModulesEPROM DevicesROM DevicesStatic RAM and Memory Support DevicesApplications Information ..Logic SymbolsMechanical Data

ATTENTIONThese devices contain circuits to protect the inputs and outputs against damagedue to high static voltages or electrostatic fields; however, it is advised thatprecautions be taken to avoid application of any voltage higher than maximumratedvoltages to these high-impedance circuits.Unused inputs must always be connected to an appropriate logic voltage level,preferably either supply voltage or ground.Additional information concerning the handling of ESD sensitive devices isavailable from Texas Instruments in a document entitled "Guidelines forHandling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies. " -Please contactto obtain this brochure.Texas InstrumentsP.O. Box 401560Dallas, Texas 75240

•••••MOSLSI65,536 X 4 OrganizationSingle + 5·V Supply (10% Tolerance)22·Pin Single-In-Line Package (SIP)Utilizes Four 64K Dynamic RAMs in PlasticChip CarrierLong Refresh Period ... 4 ms (256 cycles)All Inputs, Outputs, Clocks Fully TTLCompatible3-State OutputsPerformance of Unmounted RAMs:ACCESS ACCESS READTIME TIME ORROW COLUMN WRITEADDRESS ADDRESS CYCLE(MAX) (MAX) (MIN)TMS4164-12 120 ns 75 ns 230 nsTMS4164-15 150 ns 100 ns 260 nsTMS4164-20 200 ns 135 ns 330 nsCommon CAS Control with Separate Data-Inand Data-Out LinesLow Power Dissipation:OPERATING STANDBY(TYP)(TYP)TM4164EC4-12 800 mW 70mWTM4164EC4-15 700 mW 70 mWTM4164EC4-20 540 mW 70 mW• Operating Free-Air Temperature ... 0 DC to70 D C• Upward Compatible with 256K X 4. SingleIn-Line PackagedescriptionTM4164EC465,536 BY 4·B11 DYNAMIC RAM MODULEREAD,MODIFY,WRITECYCLE(MIN)260 ns285 ns345 nsAO-A7CAS01-04NC01-04RASVooVSSW22·PINSINGLE·IN·L1NE PACKAGE(TOP VIEW)NC(1)VDD (2)D1 (3)01 (4)CAS (5)A7 (6)A5 (7)A4 (8)D2 (9)02 (10)W(11)A1 (12)A3 (13)A6 (14)03 (15)D3 (16)A2 (17)AO(18)RAS (19)D4 (20)04 (21)VSS (22)PIN NOMENCLATUREAddress InputsColumn Address StrobeData InputsNo ConnectionData OutputsRow Address Strobe+ 5-V SupplyGroundWrite EnableNOVEMBER 1983rnQ):;"Co::?i::?iCThe TM4164EC4 is a 256K, dynamic random-access memory module organized as 65,536 x 4 bits in a 22-pin singlein-linepackage comprising four TMS4164FPL, 65,536 x 1 bit dynamic RAM's in 18-lead plastic chip carriers mountedon top of a substrate together with two 0.2JLF decoupling capacitors. Each TMS4164FPL is described in the TMS4164data sheet and is fully electrically tested and processed according to TI's MIL-STD-883B (as ammended for commercialapplications) flows prior to assembly. After assembly onto the substrate, a further set of electrical tests is performed.The TM4164EC4 is rated for operation from OOC to 70 o C.upward compatibilityFuture 256K x 4 memory modules in single-in-line packages will have identical pin functions and spacing, but will be5,1 mm (0.2 inches) longer than the TM4164EC4; the length of the 256K x 4 (TM4256EE4) will be 61,0 ± 0,6 mmMAX (2.400±0.025 inches MAX). To ensure compatibility between the two devices, enough clearance should beallowed on the PC board design to accomodate the increased length of the TM4256EE4. Pin 1 of the TM4256EE4module will be memory address A8.34PRODUCT PREVIEWThis document contains information on a product underdevelopment. Texas Instruments reserves the right tochange or discontinue this product without notice. .TEXASINSTRUMENTSPOST OFFIC(SOX 225012 • DALLAS, TEXAS 75265Copyright © 1983 by Texas Instruments Incorporated5-1

TM4164EC465,536 BY 4·BIT DYNAMIC RAM MODULEop~rationThe TM4164EC4 operates as four TMS4164s connected as shown in the functional block diagram. Refer to theTMS4164 data sheet for details of its operation.specificationsFor TMS4164 electrical specifications, refer to the TMS4164 data sheet.single-in-Iine package and componentsPC substrate: 0,79 mm (0.031 inch) minimum thicknessBypass capacitors: Multilayer ceramicLeads: Tin over brassC

TM4164EC465,536 BY 4·BIT DYNAMIC RAM MODULEMECHANICAL DATA22-pin single-In-line package56.52 (2.225155,25 (2.17515,08 (0.2001-r-----iMAX I IPIN SPACING 2,54 (0.100) T.P.--I---I(See Note 8)0.305 (0.01210.203 (0.008)II 0.51 (0.020)--11--0.41 (0.016)ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHESNOTE 8. Each pin centerline is located within 0.25 (0.010) of its true longitudinal position.TI single-in-line package nomenclatureTMT QQ4164 E c(55,9 x 11.4 mm)(2.2 x 0.45 inches)4 -15cibMax Access-12 120 ns-15 150 ns-20 200 nsLenCD3"'Co~~«a:(,)·eC'ac>CTexas Instruments reserves the right to make changes at any time in order to improve design and to supply the best product possible.4TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752655-3

c-s:s:o0-CCDen5-4

MOSLSITM4164EL965,536 BY 9·BIT DYNAMIC RAM MODULENOVEMBER 19B3• 65,536 X 9 Organization• Single + 5-V Supply (10% Tolerance)• 30-Pin Single-In-Line Package (SIP)• Utilizes Nine 64K Dynamic RAMs in PlasticChip Carrier• Long Refresh Period ... 4 ms (256 cycles)• All Inputs, Outputs, Clocks Fully TTL.Compatible• 3-State Outputs• Performance of Unmounted RAMs:ACCESS ACCESS READTIME TIME ORROW COLUMN WRITEADDRESS ADDRESS CYCLE(MAX) (MAX) (MIN)TMS4164-12 120 ns 75 ns 230 nsTMS4164-15 150 ns 100 ns 260 nsTMS4164-20 200 ns 135 ns 330 ns• Common CAS Control for Eight CommonData-In and Data-Out Lines• Separate CAS Control for One Separate Pairof Data-In and Data-Out Lines• Low Power Dissipation:OPERATING STANDBY(TYP)(TYP)TM4164EL9-12 1800 mW 157.5 mWTM4164EL9-1 5 1575 mW 157.5 mWTM4164EL9-20 1215 mW 157.5 mW• Operating Free-Air Temperature ... OOC to 70°CREAD,MODIFY,WRITECYCLE(MIN)260 ns285 ns345 nsVDD (1)CAS (2)D01 (3)AO (4)A1 (5)D02 (6)A2 (7)A3 (8)Vss (9)D03 (10)A4 (11 )A5 (12)D04 (13)A6 (14)A7 (15)D05 (16)NC (17)NC (18)NC (19)D06 (20)W (21)VSS (22)D07 (23)NC (24)D08 (25)09 (26)RAS (27)CAS9 (28)D9 (29)VDD (30)30-PINSINGLE-IN·L1NE PACKAGE(TOP VIEW)DoDoDoDoDoDoDoDoDenQ)"5"'C0~~

1M4164EL965,536 BY 9-B11 DYNAMIC RAM MODULEfunctional block diagramAOA1A2A3A4A5A6A7(4)(5)(7)(8)(11)(12)(14)(15)(27)(2)(21)C's:s:0Q.I:Ci)enOQ1OQ2(10)OQ3(13)OQ4CAS909VOOVOOVSSVSS(3)(6)(28)(29)(1)(30)(9)(22)8M1.... ~ AO-A7RAS,.... - CAS..... Iii01 Voo.1M28AO-A7.... ~ RASIv~~nOQ5 (16)..r---- CAS,....ViOQ6 (20)o QnVOO VSS8M3~~-RASAO-A7t-CAS,....WIo Q~VOO VSSI II M4 I8~ AO-A7RAS.r---,CAS,.... - WfC1···fC8~OQ7 (23)D D~ DOS ""VOO VSS8,-~,....t-~P-.... I----J::::>..r---r--I8~~..r---r--ItM5AO-A7- RASCASIiio Q~Voo VssIII M61AO-A7RASCAS- WoVOO VSS.1 .1j M7jAO-A7-RASCASWQQo Q~VOO VSSI M818AO-A7~~ RAS.r---, - CASr-- - WIIVOOoVSSQlII M918AO-A7~ RAS..r--- - CAS..r--- -w0 Q~ Q9VOO VSSIII5-6TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

TM4164EL965,536 BY 9-BIT DYNAMIC RAM MODULEoperationThe TM4164EL9 operates as nine TMS4164s connected as shown in the functional block diagram. Refer to theTMS4164 data sheet for details of its operation.specificationsFor TMS4164 electrical specifications, refer to the TMS4164 data sheet.single-in-line package and capacitorsPC substrate: 0,79 mm (0.031) minimum thicknessBypass capacitors: Multilayer ceramicLeads: Tin over brass30-pin single-in-line packageMECHANICAL OAT AI 76,84 (3.025) I75,57 (2.975) 5,08 (O.200)TiI ========"'~~"'DDDDDDDDDMAXI dl~",.m, ."PIN SPACING 2,54 (0.100) T.P.----1---I(See Note a)0,305 (0.012)0,203 (0.008)-II- 0,51 (0.020)0.41 (0.016)ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHESNOTE a. Each pin centerline is located within 0,25 (0.010) of its.true longitudinal position.TI single-in-line package nomenclatureTMT~4164 L176,2 x 16,5 mm)(3.0 x 0.65 inches)9 -15GbMax Access-12 120 ns-15 150 ns-20 200 ns,LTexas (nstruments reserves the right to make changes at any time in order to improve design and to s'upply the best product possible.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752655-7

5-8

••••••••0MOSLSI65,536 X 8 OrganizationSingle +5-V Supply (10% Tolerance)30-Pin Single-In-Line Package (SIP)Utilizes Eight 64K Dynamic RAMs in PlasticChip CarrierLong Refresh Period ... 4 ms (256 cycles)All Inputs, Outputs, Clocks Fully TTLCompatible3-State OutputsPerformance of Unmounted RAMs:ACCESS ACCESS READTIME TIME ORROW COLUMN WRITEADDRESS ADDRESS CYCLE(MAX) (MAX) (MIN)TMS4164-12 120 ns 75 ns 230 nsTMS4164-15 150 ns 100 ns 260 nsTMS4164-20 200 ns 135 ns 330 nsCommon CAS Control with Common Data-In and Data-Out LinesLow Power Dissipation:OPERATING STANDBY(TYP)(TYP)TM4164FL8-12 1600 mW 140 mWTM4164FL8-1 5 1400 mW 140mWTM4164FL8-20 1080 mW 140 mWdescriptionOperating Free-Air Temperature ... 0 DC to70 D CThe TM4164FL8 series is a 51 2K, dynamic randomaccessmemory module organized as 65,536 x 8 bitsin a 30-pin single-in-line package comprising eightTMS4164FPL, 65,536 x 1 bit dynamic RAMs in18-lead plastic chip carriers mounted on top of asubstrate together with eight 0.2 p.F decouplingcapacitors. Each TMS41 64FPL is described in the datasheet and is fully electrically tested and processed accordingto Tl's MIL-STD-8838 (as ammended for commercialapplications) flows prior to assembly. Afterassembly onto the SIP, a further set of electrical testsis performed. The TM4164FL8 is rated for operationfrom OOC to 70°C.TM4164FL865,536 BY 8-BIT DYNAMIC RAM MODULEREAD,MODIFY,WRITECYCLE(MIN)260 ns285 ns345 ns3D-PINSINGLE-IN-L1NE PACKAGE(TOP VIEW)VDD (1)CAS (2)DQ1 (3)AO (4)A1 (5)DQ2 (6)A2 (7)A3 (8)Vss (9)DQ3 (10)A4 (11 )A5 (12)DQ4 (13)A6 (14)A7 (15)DQ5 (16)NC (17)NC (18)NC (19)DQ6 (20)W (21)VSS (22)DQ7 (23)NC (24)DQ8 (25)NC (26)RAS (27)NC (28)NC (29)VDD (30)NOVEMBER 19B3DoDoDoDoDoDoDoDoPIN NOMENCLATUREAO-A7 Address InputsCAS Column Address Str?beDQ1-DQ8 Data In/Data OutNC No ConnectionRAS Row Address StrobeVDD +5-V SupplyVSS GroundW Write EnableenQ):;"C0~~-CPRODUCT PREVIEWThis document contains information on a product underdevelopment. Texas Instruments reserves the right tochange or discontinue this product without notice.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265Copyright © 1983 by Texas Instruments Incorporated5-9

TM4164FL865,536 BY 8·BIT DYNAMIC RAM MODULElogic symbol t0s:s:0Q.CCDenAOA1A2A3A4A5A6A7RASCASVii006007008(4)(5)(7)(8)(11 )(12)(14)(15)(27) ........(2)" (21) ........(3)r-:-001(6)002(10)003(13)004(16)005..(20) -(23)(25)Z30Z31Z32Z33Z34Z35Z36Z37Z38Z39Z40.,\742Z41RAM 64K X 830 - 2008/21 DO -3132 -33-f- 034 > A 65.535353637 20015/2107_38 ~C20[ROW]38· I- G23/[REFRESH ROW]38 24 [PWR OWN]39 ~ C21[COL]39 G2439 &I> 23C224040 23.210 24EN41 A.220 AZ42r-tThis symbol is in accordance with IEEE Std 91/ANSI Y32.14 and recent decisions in IEEE and IEC. See explanation on page 10-1.5-10, TEXASINSTRUMENTSPOST OFFICE BOX 225012 • OALLAS, TEXAS 75265

TM4164FL865,536 BY 8·BIT DYNAMIC RAM MODULEfunctional block diagram(41AO(51A1(71A2(81A3(111A4(121A5(141A6(151A7(271RAS(21CAS(211ViOQ1OQ2(101OQ3(131OQ4VOOVOO(31(61(11(301(91VSS(221·VSSM1~.... f--,t:::. AO-A7RAS.... - CASr-.. - WIVoo°Vf~~II M21~ AO-A7~f--.J::::.. RAS..... - CAS.1'---I8- WVOO ° VSS Q~I II M3 I~~ AO-A7RAS..... CAS.....WI ° Q~VOO VSSI IJM48~ AO-A7RAS"..... CAS -wI °IOQ5 (161OQ6 (201OQ7 (231a l DaB ''''Voo Vss1fC1"'fC88~~...."I8~~....r--..I~~f--.J::::............fM5AO-A7RAS- CASVio Q~v~o VssI M61AO-A7RASCAS- WVOO ° VSS Q~I II M7 IAO-A7RAS- CASWVOO ° VSS Q~I II M8 I8AO-A7~ RAS..... - CAS.... - wvio ° Vss Q~IIenQ)~"Co:2:2

TM4164FL865,536 BY 8·BIT DYNAMIC RAM MODULEoperationThe TM4164FL8 series operates as eight TMS4164s connected as shown in the functional block diagram. Refer tothe TMS4164 data sheet for details of its operation.specificationsFor TMS4164 electrical specifications, refer to the TMS4164 data sheet.single-in-line packagesPC substrate: 0,79 mm (0.031) minimum thicknessBypass capacitors: Multilayer ceramicLeads: Tin over brassMECHANICAL DATA30-pin single-in-line packagec

Alphanumeric Index, Table of Contents, Selection GuideInterchangeability GuideGlossary/Timing Conventions/Data Sheet StructureDynamic RAM and Memory Support DevicesDynamic RAM ModulesEPROM DevicesROM DevicesStatic RAM and Memory Support DevicesApplications InformationLogic SymbolsMechanical Data

TI EPROMS INCORPORATE FAST PROGRAMMING CAPABILITYThe TMS2764 64K EPROM and TMS27128 128K EPROM (industry standard JEDEC approved pin outs) maybe programmed with the fast programming algorithm reducing programming time by a factor of 5 to 10X.The TMS2516 16K EPROM, TMS2532 32K EPROM, TMS2564 64K EPROM and TMS2732A 32K EPROM(JEDEC approved pin out) may be programmed with either the standard 50-millisecond pulse or a fast10-millisecond pulse.To take advantage of fast programming on TI EPROMs commercial programmers require the revision shownbelow ..DATA 1/0TMS2516TI EPROMsTMS2764PROGRAMMERS TMS2532 TMS27128TMS2564TMS2732AModel 120A/121 Revision G/V07 * Revision D*Unipak Revision V07 * Revision V04 *Unipak 2 Revision V05 * Revision V03 *PROLOGM980/M910A Control UnitPM9080 Personality Module Update PROM UDP4 No Update PROM is requiredPA28/80B Pin Out Adapter• Subsequent revisions are also validm~::J:Jo3:cCD

MOSLSITMS2516. SMJ251616.384-BIT ERASABLE PROGRAMMABLE REA.O-ONLY MEMORIESDECEMBER 1979 - REVISED AUGUST 1983• Organization ... 2048 X 8• Single + 5-V Power Supply'• Pin Compatible with Existing ROMs andEPROMs (16K, 32K, and 64K) .• JEDEC Standard Pinout• All Inputs/Outputs Fully TTL Compatible• Static Operation (No Clocks, No Refresh)• Max Access/Min Cycle Time:'2516-35'2516-45350 ns450 ns• 8-Bit Output for Use in Microprocessor-Based Systems \• N-Channel Silicon-Gate Technology• 3-State Output BuffersooLow Power Dissipation:Active ... 285 mW TypicalStandby ... 100 mW TypicalGuaranteed DC Noise Immunity withStandard TTL Loads• No Pull-Up Resistors Required• Available in Full Military Temperature RangeVersion (SMJ2516)descriptionThe '2516 series are 16,384-bit, ultraviolet-lighterasable, electrically-programmable read-onlymemories. These devices are fabricated usingN-channel silicon-gate technology for high speed andsimple interface with MOS and bipolar circuits. All inputs(including program data inputs) can be driven bySeries 54/74 TTL circuits without the use of externalpull-up resistors, and each output can drive one Series54/74 TTL circuit without external resistors. The dataoutputs are three-state for connecting multiple devicesto a common bus. The '2516 is plug-in compatiblewith the '401616K static RAM.A6A5A4A3AlQlTMS2516 .•. JL PACKAGESMJ2516 ... J PACKAGE(TOP VIEW)A7VeeA6A8A5A9A4VppA3 SA2A10A1PD/PGMAO 0801 0702 0603 05VSS 04SMJ2516 .•. FG PACKAGE(TOP VIEW)ur-. U U U U U U~ Z zz>z z4 3 2 13231305 6. 29 A86 28 A97 27 NC8 26 Vpp9 25 S10 24 Al011 23 PD/PGM12 22 Q813 21 Q714 15 1617181920NM (/)U~L!l

1MS2516, SMJ251616,384-B11 ERASABLE PROGRAMMABLE READ-ONLY. MEMORIESThe TMS2516s are offered in a dual-in-line cerpak package (JL suffix), rated for operation form ooe to 70oe. TheSMJ' devices are offered in a 24-pin dual-in-line ceramic package (J) and in a 32-pad lead less ceramic chip carrier(FG). The J package is designed for insertion in mounting-hole rows on 600-mil (15,2 mm) centers, whereas the FGpackage is intended for surface mounting on solder pads on 0.050-inch (1,27 mm) centers. The FG package offersa three layer rectangular chip carrier with dimensions 0.450 x 0.550 x 0.1 00 (11,42 x 13,97 x 2,54).Since these EPROMs operate from a single + 5 V supply (in the read mode), they are ideal for use in microprocessorsystems. One other ( + 25 V) supply is needed for programming but all programming signals are TTL level, requiringa single 10-ms pulse. For programming outside of the system, existing EPROM programmers can be used. Locationsmay be programmed singly, in blocks, or at random. Total programming time for all bits is 20 seconds.operationMODEFUNCTIONOutput Start Inhibit Program(PINS) Read Power DownDisable Programming Programming VerificationPD/PGM Don't Pulsed VIL(18)VILCareVIHto VIHVILVILSDon't(20)VIL VIHCareVIH VIH VILVpp+25 V+5 V +5 V +5V +25 V +25 V(21) (or +5 VIVCC(24)Q+5 V +5 V+5 V +5 V +5 V +5 V(9 to 11, Q HI-Z HI-Z D HI-Z Q13 to 17)m"'0::Dos:cCD

TMS2516, SMJ251616,384-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIESin parallel (8 bits) on pins 01 through 08. Once addresses and data are stable, a 1 a-millisecond TTL high-level pulseshould be applied to the PGM pin at each address location to be programmed. Maximum pulse width is 55 milliseconds.Locations can be programmed in any order. Several '2516s can be programmed simultaneously when the devicesare connected in parallel.inhibit programmingWhen two or more devices are connected in parallel, data can be programmed into all devices or only chosen devices.'2516s not intended to be programmed (i.e., inhibited) should have a low level applied to the PD/PGM pin and a highlevelapplied to the Spin.program verificationA verification is done to see if the device was programmed correctly. A verification can be done at any time. It canbe done on each location immediately after that location is programmed. To do a verification, V~p may be kept at+25 V.logic symbol t(8)AO(7)A1(6)A2(5)A3(4)A4(3)A5(2)A6(1 )A7(23)A8(22)A9(19)A10PD/PGM(18).. "'"b(20)0EPROM 2048x8A\]A\]0 A\]>A 2047 A\]A\]A\]A\]A\]107f:Nl(9)01(10) 02(11 ) 03(13) 04(14)05(15)06(16) 07(17) 08U)Q)(,)'S;Q)C~0a:c..wtThis symbol is in accordance with IEEE Std 91/ANSI Y32.14 and recent decisions in IEEE and IEC. See explanation on page 10-1.absolute maximum ratings over operating free-air temperature range (unless otherwise noted) tSupply voltage, Vee (see Note 1) ............................................. - 0.3 V to 7 VSupply voltage, Vpp (see Note 1) ............................................ - 0.3 V to 28 VAll input voltages (see Note 1) ............................................... -:- 0.3 V to 7 VOutput voltage (operating, with respect to VSS) .................................. - 0.3 V to 7 VOperating free-air temperature range: TMS' ...................................... ooe to 70°COperating case temperature range: SMJ'. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55 °e to 125°eStorage temperature range ................................................ - 65 °C to 150 °et Stresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functionaloperation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specificationis not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.NOTE: 1. Under absolLte maximum ratings, voltage values are with respect to the most negative supply voltage, VSS (substrate).TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752656-3

1MS251616.384-BI1 ERASABLE PROGRAMMABLE READ-ONLY MEMORIESrecommended operating conditionsPARAMETERTMS2516-35TMS2516-45MIN NOM MAX MIN NOM MAXSupply voltage, VCC (see Note 2) 4.75 5 5.25 4.75 5 5.25 VSupply voltage, Vpp (see Note 3) VCC VCC VSupply voltage, VSS 0 0 VHigh-level input voltage, VIH 2 VCC+ 1 2 VCC+ 1 VLow-level input voltage, VIL -0.1 0.8 -0.1 0.8 VRead cycle time, tc(rd) 350 450 nsOperating free-air temperature, T A 0 70 0 70 °cUNITNOTES:2. Vee must be applied before or at the same time· as Vpp and removed after or at the same time as Vpp. The device must not be inserted intoor removed from the board when Vpp or Vee is applied.3. Vpp can be connected to Vee directly (except in the program mode). Vee supply current in this case would be ICC + Ipp. During programming.Vpp must be maintained at 25 V (± 1 V).electrical characteristics over full ranges of recommended operating conditionsm"'0~PARAMETER(active)o3: t Typical values are at T A = 25°C and nominal voltages.cCD

TMS251616,384·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORIESswitching characteristics over full ranges of recommended operating conditions (see Note 4)PARAMETERTEST CONDITIONS TMS2516-35 TMS2516-45(SEE NOTES 4 AND 5) MIN Typt MAX MIN Typt MAXtalA) Access time from address 250 350 280talS) Access time from chip select 120talPR) Access time from PD/PGM 250 350 280Output data valid aftertv(A)address changeCL = 100 pF,0 0tdislS)Output disable time from chipselect during read onlyiOutput disable time from chip1 Series 74 TTL load,trS 20 ns,tfs20 ns0 100 0tdislS) select during program 120and program verify itdislPR)Output disable timefrom PD/PGM i0 100450150450100120100UNITnsnsnsnsnsnsnst All typical values are at T A = 25°C and nominal voltages.~ Value calculated from 0.5 volt delta to measured output level.recommended timing requirements for programming T A 25°C (see Note 4)TMS2516PARAMETERMIN Typt MAXtw(PR) Pulse duration, program pulse 955trlPR) Rise time, program pulse 5tflPR) Fall time, program pulse 5tsulA) Address setup time 2tsulS) Chip-select setup time 2tsulD) Data setup time 2tsulVPP) Setup time from Vpp 0thlA) Address hold time 2thiS) Chip-select hold time 2thlD) Data hold time 2t Typical values are at nominal voltages.NOTES: 4. Timing measurement reference levels: inputs O.B V and 2 V, outputs 0.65 V and 2.2 V.5. Common test conditions apply for tdis except during programming. For talA). taIS), and tdis' PDIPGM = S = VIL'UNITmsnsnsflsflSflsnsflSflSflsCI)Q)(.)'S;Q)C~oa::a..w4TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752656-5

SMJ251616,384-B11 ERASABLE PROGRAMMABLE READ-ONLY MEMORIESrecommended operating conditionsPARAMETERSMJ2516-35SMJ2516-45MIN, NOM MAX MIN NOM MAXSupply voltage, VCC (see Note 2) 4.5 5 5.5 4.5 5 5.5 VSupply voltage, Vpp (see Note 3) Vec Vee VSupply voltage, VSS 0 0 VHigh-level input voltage, VIH 2 VCC+ 1 2 VCC+ 1 VLow-level input voltage, VIL -0.1 0.8 -0.1 0.8 VRead cycle time, tc(rd) 350 450 nsOperating case temperature, T C -55 125 -55 125 °cUNITNOTES:2. Vee must be applied before or at the same time as Vpp and removed after or at the same time as Vpp. The device must not be inserted intoor removed from the board when Vpp or Vee is applied.3. Vpp can be connected to Vee directly (except in the program mode). Vee supply current in this case would be ICC + Ipp. During programming.Vpp must be maintained at 25 V (± 1 V).electrical characteristics over full ranges of recommended operating conditionsocPARAMETERVOH High-level output voltageVOL Low-level output voltageII Input current (leakage)10 Output current (leakage)IpP1 Vpp supply currentVpp supply currentIpP2(during program pulse)VCC supply currentICC1(standby)m""CVCC supply current:lJICC2(active)3!: t Typical values are at Te = 25°C and nominal voltages.TEST CONDITIONS10H = -400/LAIOL = 2.1 mAVI = 0 V to 5.5 VVo = 0.4 V to 5.5 VVpp = 5.25 V, PD/PGM = VILPD/PGM = VIHPD/PGM = VIHS = PDIPGM = VILSMJ2516MIN Typt MAX2.40.45±10±1063020 3057 100~ capacitance over recommended supply voltage arid operating case temperature ranges, f 1 MHzt(i'CD(I)PARAMETERTEST CONDITIONSCi Input capacitance VI = 0 V, f = 1 MHzCo Output capacitance Vo = 0 V, f = 1 MHzSMJ2516TYP:t MAX4 68 12UNITVV/LA/LAmArnAmAmAUNITpFpFt Capacitance measurements are made on a sample basis only.* Typical values are at T e = 25°C and nominal voltages.6-6TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 7526518

SMJ251616,384-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIESswitching characteristics over full ranges of recommended operating conditions (see Note 4)talA)ta(S)ta(PR)tv(A)tdis(S)tdis(S)tdis(PR)PARAMETERAccess time from addressAccess time from chip selectAccess time from PD/PGMOutput data valid afteraddress changeOutput disable time from chipselect during read onlytOutput disable time from chipselect during programand program verifytOutput disable timefrom PD/PGMtTEST CONDITIONS SMJ2516-35 SMJ2516-45(SEE NOTES 4 AND 5) MIN Typt MAX MIN Typt MAX250 350280 450120150250 350280 450CL = 100 pF,001 Series 54 TTL load,t r :520 ns,0 100 0100tf:520 ns1201200 100100UNITnsnsnsnsnsnsnst All typical values are at T C = 25°C and nominal voltages.t Value calculated from 0.5 volt delta to measured outputrecommended timing requirements for programming T C 25°C (see Note 4)SMJ2516PARAMETERMIN Typt MAXtw(PR) Pulse duration, program pulse955tr(PR) Rise time, program pulse5tf(PR) Fall time, program pulse5tsu(A) Address setup time2tsu(S) Chip-select setup time2tsu(D) Data setup time2tsu(VPP) Setup time from VPP0th(A) Address hold time2thIS) Chip-select hold time2th(D) Data hold time2t Typical values are at nominal voltages.NOTES: 4. Timing measurement reference levels: inputs 0.8 V and 2 V, outputs 0.65 V and 2.2 V.5. Common test conditions apply for tdis except during programming. For talA), taIS)' and tdis' PDIPGM = 5 = VIL'UNITmsnsnsp'sp'sp'snsp'sp'sp'senQ)(,)·SQ)c~oa:a.wTEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752656-7

TMS2516, SMJ251616,384-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIESPARAMETER MEASUREMENT INFORMATIONV = 2.09 V= 7800OUTPUTUNDER TEST-JRLl' CL =.100 pFFIGURE 1 -TYPICAL OUTPUT LOAD CIRCUIT.m"'tJjJ03:0CD

o 441MS2516, SMJ251616,384·B11 ERASABLE PROGRAMMABLE READ·ONLY MEMORIESprogram cycle timingADDRESSES::: -_..-J)i ADDRESSI ..PROGRAM~PROGRAM---J1 VERIFY 1PD/PGMVppQ1-Q8tdislSI--i ~N : ~r:-A~-D-:E-!-Si---tSUIAI--1r--thIAI~ :I ItalS'r ~ r-tdiSISI: : I ~/i! I I \~ /' ~VIL __---I II tWIPrl I" -I I t IIJ _I I thlDIM j.- ~tsUISI~ .: I I I I: inl't'"'-i I rVIL---------~ ! !I ~+25VRPI trIPRI....., I+- I II /. tSUIVPPI...j! --.f j.-t: IPRI I- .~ ,.. -I tsulDI I+5V-, I II I I I::::,: DATA OUT ~~ DATAIN }HIOZ{ D:~: }-cICI)Q)(,)os:Q)c:Eoa:c..wTexas Instruments reserves the right to make changes at any time in order to improve design and to supply the best product possible.14TEXASINSfRUMENlSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752656-9

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MOSLSITMS2532, SMJ253232,768·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORIESDECEMBER 1979 - REVISED SEPTEMBER 1983• Organization ... 4096 X 8• Single + 5·V Power Supply• Pin Compatible with Existing ROMs andEPROMs (8K, 16K, 32K, and 64K)• JEDEC Standard Pinout• All Inputs/Outputs Fully TTL Compatible• Static Operation (No Clocks, No Refresh)• Max Access/Min Cycle Time:'2532·30'2532·35'2532-45300 ns350 ns450 ns• 8-Bit Output for Use in Microprocessor-Based Systems• N-Channel Silicon-Gate. Technology• 3-State Output Buffers• Low Power Dissipation:- Active ... 400 mW Typical- Standby ... 100 mW Standby• Guaranteed DC Noise Immunity withStandard TTL Loads• No Pull-Up Resistors Required• Available in Full Military Temperature RangeVersion (SMJ2532)descriptionThe '2532 series are 32,76B-bit, ultraviolet-lighterasable,electrically-programmable read-onlymemories. These devices are fabricated using Nchannel silicon-gate technology for high speed andsimple interface with MOS and bipolar circuits. All inputs(including program data inputs) can be driven bySeries 54/74 TTL circuits without the use of externalpull-up resistors, and each output can drive one Series54/74 TTL circuit without external resistors. The dataoutputs are three-state for connecting multiple devicesto a common bus. The TMS2532 series are plug-incompatible with the TMS4732 32K ROM.A5A4,NCA3A2A1AO0102TMS2532 ... JL PACKAGESMJ2532 ... J PACKAGE(TOP VIEW)A7VCCA6A8A5A9A4VppA3PD/PGMA2A10A1A11AO 0801 Q702 0603 05Vss 04SMJ2532 ... FE PACKAGEITOP VIEW)UCO ..... UU UUC:O

TMS2532, SMJ253232,768-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIESoperationSince these EPROMs operate from a single + 5 V supply (in the read model. they are ideal for use in microprocessorsystems. One other ( + 25 V) supply is needed for programming but all programming signals are TTL level, requiringa single lams pulse. For programming outside of the system, existing EPROM programmers can be used. Locationsmay be programmed singly, in blocks, or at random. Total programming time for all bits is 41 seconds.FUNCTION(PINS)ReadMODEOutputStartInhibitPower DownDisable Programming ProgrammingPD/~ VIL VIH VIH Pulsed V,H VIH(20) to V,LVpp +5V +5 V +5V +25 V +25V(21)Vec +5V +5V +5V +5V +5V(24)Q Q HI·Z HI·Z D HI-Z(9 to 11,13 to 17)read/out disableWhen the outputs of two or more '2532s are connected on the same bus, the output of any particular device in thecircuit can be read with no interference from the competing outputs of the other devices. The device whose outputis to be read should have a low-level TTL signal applied to the PD/PGM pin. All other devices in the circuit shouldhave their outputs disabled by applying a high-level signal to this pin. Output data is accessed at pins Ql through Q8.power downm"'U::Do~c

TMS2532, SMJ253232,768-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIESprogram verificationThe '2532 program verification is simply the read operatio.n, which can be performed as soon as Vpp returns to + 5 Vending the program cycle.logic symboltEPROM 4096 X 8AO ..:(.;;.8)~_-i 0A1 (7)A2 (6)A3 (5)A4 (4)A5 (3)A6 (2)A7 (1)A8 (23)A9 (22)A10 (19)A11 (181PD/PGM ...;(_20.;;..;1_e_--iA\lA\lA\loA 4095 A\lA\lA\l(91 01(101 02(111 03(131 04(14) 05(151 06(16) 07(171 08t This symbol is in accordance with IEEE Std 91/ANSI Y32.14 and recent decisions by IEEE and IEC. See explanation on page 10-1.absolute maximum ratings over operating free-air temperature range (unless otherw'ise noted):j:Supply voltage, Vee (see Note 1) ............................................ . -0.3 V to 7 VSupply voltage, Vpp (see Note 11 ..................................... _..... . -0.3 V to 28 VAll input voltages (see Note 11 ............................................... - 0.3 V to 7 VOutput voltage (operating, with respect to VSSI .................................. -0,3 V to 7 VOperating free-air temperature range: TMS2532 .................................. ooe to 70 0 eOperating case temperature range: SMJ2532. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 °C to 125 °eStorage temperature range ................................................ - 65 °C to 150 0 een(1)(,)'S;(1)C~oa:Q.Wt Stresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functionaloperation of the device at these or any other conditions beyolld those indicated in the" Recommended Operating Conditions" section of this specificationis not implied. Exposure to absolute·maximum-rated conditions for extended periods may affect device reliability.NOTE 1: Under absolute maximum ratings, voltage values are with respect to the most negative supply voltage, VSS (substrate).TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752656-13

TMS253232,768-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIESrecommended operating conditionsPARAMETERTMS2532-30 TMS2532-35 TMS2532-45MIN NOM MAX MIN NOM MAX MIN NOM MAXUNITSupply voltage, VCC (see Note 2) 4.75 5 5.25 4.75 5 5.25 4.75 5 5.25 VSupply voltage, Vpp (see Note 3) Vcc Vee Vee VSupply voltage, VSS 0 0 0 VHigh-level input voltage, VIH 2 Vee+ 1 2 Vee+ 1 2 Vee+ 1 VLow-level input voltage, VIL -0.1 0.8 -0.1 0.8 -0.1 0.8 VRead cycle time, tc(rd) 300 350 450 nsOperating free-air temperature, T A 0 70 0 70 0 70 °cNOTES:2. VCC must be applied before or at the same time as Vpp and removed after or at the same time as Vpp. The device must not be inserted intoor removed from the board when Vpp is applied.3. Vpp can be connected to VCC directly (except in the program mode). VCC supply current in this case would be ICC + Ipp. During programming,Vpp must be maintained at 25 V (± 1 V).electrical characteristics over full ranges of recommended operating conditionsm.":0os:cCD

TMS253232,768-BI1 ERASABLE PROGRAMMABLE READ-ONLY MEMORIESrecommended timing requirements for programming T A 25°C (see Note 4)tw(PR)tr(PR)tf(PR)tsu(A)tsu(D)tsu(VPP)th(A)th(D)th(PR)th(VPP)PARAMETERPulse duration, program pulseRise time, program pulseFall time, program pulseAddress setup timeData setup timeSetup time from VPPAddress hold timeData hold timeProgram pulse hold timeVPP hold timeTMS2532MIN Typt MAXUNIT9 55 ms5 ns5 ns2 p's2 p.s0 ns2 p's2 p's0 ns2 p'st Typical values are at nominal voltages.NOTES: 4. Timing measurement reference levels: inputs 0.8 V and 2 V, outputs 0.65 V and 2.2 V.5. Common test conditions apply for tdis except during programming. For talA) and tdis. PDIPGM = VIL'(I)Q)CJ'SQ)c~oa:c..w14TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752656-15

SMJ253232,768-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIESrecommended operating conditionsPARAMETERSMJ2532-35SMJ2532-45MIN NOM MAX MIN NOM MAXSupply voltage, VCC (see Note 2) 4.5 5 5.5 4.5 5 5.5 VSupply voltage, Vpp (see Note 3) VCC VCC VSupply voltage, VSS 0 0 VHigh-level input voltage, VIH 2 VCC+ 1 2 VCC+ 1 VLow-level input voltage, VIL -0.1 0.8 -0.1 0.8 VRead cycle time, tc(rd) 350 450 nsOperating case temperature, TC -55 125 -55 125 °cUNITNOTES:2. VCC must be applied before or at the same time as Vpp and removed after or at the same time as Vpp. The device must not be inserted intoor removed from the board when Vpp is applied.3. Vpp can be connected to VCC directly (except in the program model. VCC supply current in this case would be ICC + Ipp. During programming,Vpp must be maintained at 25 V (± 1 V).electrical characteristics over full ranges of recommended operating conditionsm"tI:0os:ccc:;"

SMJ253232,768-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIESrecommended timing requirements for programming TC 25°C (see Note 4)PARAMETERSMJ2532MIN Typt MAXtw(PR) Pulse duration, program pulse 9 55 mstr(PR) Rise time, program pulse 5 nstf(PR) Fall time, program pulse 5 nstsu(A) Address setup time 2 p.stsu(D) Data setup time 2 p'stsu(VPP) Setup time from VPP 0 nsth(A) Address hold time 2 p'sth(D) Data hold time 2 p'sth(PR) Program pulse hold time 0 nsth(VPP) VPP hold time 2 p'st Typical values are at nominal voltages.NOTES: 4. Timing measurement reference levels: inputs 0.8 V and 2 V, outputs 0.65 V and 2.2 V.5. Common test conditions apply for tdis except during programming. I'or talA) and tdis' PD/PGM = VIL'UNITenQ)(,)·SQ)c~oa:0-W4TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752656-17

TMS2532, SMJ253232,768-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIESPARAMETER MEASUREMENT INFORMATIONV = 2.09 VJRL = 780nOUTPUTUNDER TESTFCL = 100 p1, .FIGURE 1 -TYPICAL OUTPUT LOAD CIRCUITread cycle timing"rt---------tc(rd)-------... ~Im"0:0os:cCI)

TMS2532, SMJ253232,768-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIESstandby modeADDRESSESPD/PGMQ1-08VIHVILVIHVILVOHVOLADDRESS NXIADDRESSISTANDBY~ ~ACTIVE\4- tdis1 ~ta(PRltN + mVALID }-HIZ---{ VALIDt ta(PR) referenced to PD/PGM or the address, whichever occurs last.program cycle timingADDRESSESPD/PGMVPP01-08+25 V+5Vr 4~--------PROGRAM--------__ ·r4~-PROGRAM*~VERIFY I-----Jx ADDRESS N: :X"'I-A-~D-:-E-!-S-I+---- tsu(A)--+( !4 th(A)--+j I. };'WIPRIit !~ :~ tsu(VPP) j4-1 tf(PR)-.i I I I I I~~ ~th(PR) I~ '''PRI-I I- :! t ---+I i'"PRI II L th(VPP)...! ~ Itsu(D)-+i I~ ~ 14- th(D)--------------~, DATU }HI.Z{ D;~: }-CCI)Q)CJ-S;Q)c~oa:0-W• Program verify equivalent to read mode.Texas Ins:ruments reserves the right to make changes at any time in order to improve design and to supply the best product possible.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752656-19

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MOSLSITMS2564, SMJ256465,536-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIESMAY 1981 - REVISED SEPTEMBER 1983~. ~,i~000000Organization ... 8192 X 8Single + 5-V Power SupplyPin Compatible with Existing ROMs andEPROMs (8K, 16K, 32K, and 64K)All Input/Outputs Fully TTL CompatibleStatic Operation (No Clocks, No Refresh)Max Access/Min Cycle Time:TMS2564-35 ... 350 nsTMS2564-45 ... 450 nsSMJ2564-45 ... 450 nso 8-Bit Output for Use in Microprocessor-Based SystemsON-Channel Silicon-Gate Technologyo 3-State Output Bufferso Guaranteed DC Noise Immunity withStandard TTL Loadso No Pull-Up Resistors Requiredo Low Power Dissipation:Active ... 400 mW TypicalStandby ... 125 mW Typicalo Available in Full Military Temperature RangeVersion (SMJ2564)descriptionThe '2564 is a 65,536-bit ultraviOlet-light-erasable, electrically-programmableread-only memory. This device isfabricated using N-channel silicon-gate technology for highspeedand simple interface with MOS and bipolar circuits.All inputs (including program data inputs) can be driven bySeries 54/74 TTL circuits without the use of externalresistors. The data outputs are three-state for connectingmUltiple devices to a common bus.The TMS2564 is offered in a dual-in-line ceramic package(JL or JDL suffix) rated for operation from OOC to 70 0 C.The SMJ2564 is offered in a 28-pin dual-in-line ceramicpackage (J) and a leadless ceramic chip carrier (FE), ratedfor operation from - 55°C to 125°C. The J package isdesigned for insertion in mounting-hole rows on 600-mil(15,2 mm) centers, whereas the FE package is intended forsurface mounting on solder pads on 0.050-inch (1,27 mm)centers. The FE package offers a three-layer rectangularchip carrier with dimensions 0.450 x 0.550 x 0.1 00(11,43 x 13,97 x 2.54 mm).TMS2564 ... JL OR JDL PACKAGESMJ2564 ... J PACKAGE(TOP VIEW)A2A1AO0102vcc tVPP51 S2A7vcc tA6ASA5A9A4A12\A3 PD/PGMA2A10A1A11.AOOS01 Q702 A603 05Vss 04SMJ2564 ... FE PACKAGE(TOP VIEW)+-c. U U(Or--~C.UNU IUl >C")UUl~UL!)(OOZ~dzOOteonnected internally. Vee need besupplied to only one of thesetwo pins.PIN NOMENCLATUREA(N)Address InputsNCNo ConnectionPD/PGM Power Down/ProgramO(N)Input/OutputSIN)Chip SelectsVCC + 5-V Power SupplyVPP+ 25-V Power SupplyVSSO-V GroundrnCDCJ'S;CDC~oa:c.w84ADVANCE INFORMATIONMILITARY PRODUCTS (SMJ) ONLYThis document contains information on a newproduct. Specifications are subject to changewithout notice.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1983 by Texas Instruments Incorporated6-21

1MS2564, SMJ256465,536·B11 ERASABLE PROGRAMMABLE READ·ONLY MEMORIESoperationSirlce this EPROM operates from a single + 5-V supply (in the read mode), it is ideal for use in microprocessor systems.One other supply (+ 25 V) is needed for programming. Programming requires a single TTL-level pulse per location.For programming outside of the system, existing EPROM programmers can be used. Locations may be programmedsingly, in blocks, or at random.The '2564 is compatible with other 5-volt ROMs and EPROMs, including those in a 24-pin package.FUNCTION(PINS) Read Output Disable Power DownPD/PGM(22)S1(2)S2(27)Vpp(1)VILVIHXXVIHMODEStartProgrammingPulsed VIHto VILInhibitProgrammingVIH X XVIL X VIH X X VIL X VIH XVIL X X VIH XVIL X X VIH+5 V +5 V +5 V +25 V +25 VVCC t +5 V +5 V +5 V +5 V +5 V(26/28)Q(11 to 13, Q HI-Z HI-Z 0 HI-Z15 to 19)x = Don't care.tOo not use the internal jumper of 26-28 to conduct PC board currents.m"'tJ:uos:cc

TMS2564, SMJ256465,536-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIESinhibit programmingWhen two or more '2564's are connected in parallel, data can be programmed into all devices or only chosen devices.'2564's not intended to be programmed should have a high level applied to PD/PGM or 51 or 52.logic symbol tAO (10)Al (9)EPROM 8192x80A2 (8)(7) A'l(11 )01A3 (12)(6) A\) 02A4 (13)(5) A\) 03AS (15)(4) A_O_ A\) 04A6 (16)(3)8191 A\) 05A7 (171(25) A\) 06A8 (18)(24) A'l 07A9 (19)(21) A\) 08Al0All (20)(23)A1212(22)PD/PGMSl . (2)52(27)tThis symbol is in accordance with IEEE Std 91/ANSI Y32.14 and recent decisions in IEEE and IEC. See explanation on page 10-1.absolute maximum ratings over operating free-air temperature range (unless otherwise noted):j:ENSupply voltage, Vee (see note 1) ............................................. -0.3 V to 7 VSupply voltage, Vpp (see note 1) ............................................ -0.3 V to 28 VAll input voltages (see Note 1) ............................................... -0.3 V to 7 VOutput voltage (operating with respect to VSS) ................................... -0.3 V to 7 VOperating free-air temperature range: TMS2564 .................................. ooe to 70 0 eOperating case temperature range: SMJ2564. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55 DC to 125 °eStorage temperature range ................................................ - 65 DC to 150 0 eII)Q)(.)-:;Q)c~oa:c..wt Stresses beyond those listed under" Absolute maximum Ratings" may cause perm~nent damage to the device. This is a stress rating only and functionaloperation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specificationis not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTE 1:Under absolute maximum ratings, voltage values are with respect to the most-negative supply voltage, VSS (substrate).84TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752656-23

1MS2564.65,536-BI1 ERASABLE PROGRAMMABLE READ-ONLY MEMORIESrecommended operating conditionsPARAMETERTMS2564-35TMS2564-45MIN NOM MAX MIN NOM MAXSupply voltage, VCC (see Note 2) 4.75 5 5.25 4.75 5 5.25 VSupply voltage, Vpp (see Note 3) VCC VCC VSupply voltage, VSS 0 0 VHigh-level input voltage, VIH 2.2 VCC+ 1 2.2 VCC+ 1 VLow-level input voltage, VIL -0.1 t 0.8 -0.1 t 0.8 VRead cycle time, tc(rd) 350 450 nsOperating free-air temperature, T A 0 70 0 70 DCNOTES:2. Vee must be applied before or atlthe same time as Vpp and removed after or at the same time as Vpp. The device must not be inserted intoor removed from the board when Vpp or Vee is applied so that the device Is not damaged.3. Vpp can be connected to Vee directly (except in the program mode). Vee supply current in this case would be lee + Ipp. During programming.Vpp must be maintained at 25 V (± 1 V).t The algebraic convention, where the more negative limit is designated as minimum. is used in this data sheet for logic voltage levels and time intervals.electrical characteristics over full ranges of recommended operating conditionsUNITm"0:co3:cCD

TMS256465,536-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIESswitching characteristics over full ranges of recommended operating conditions (see Note 4)PARAMETERTEST CONDITIONS TMS2564-35 TMS2564-45(SEE NOTES 4 AND 5) MIN MAX MIN MAXtalA) Access time from address 350 450 nsAccess time from S1 and S2ta(S) CL = 100 pF, 120 120 ns(whichever occurs last)1 Series 54/74 TTL Loadta(PR) Access time from PD/PGM 350 450 nst r :520 ns,tv(A) Output data valid after address change0 0 nstf:520 nsOutput disable time from chip selecttdis(S)See Figure 1 0 100 O. 100 nsduring read only (whichever occurs last) ttdis(PR) Output disable time from PD/PGM during standbyi 0 100 0 100 nst All typical values are at T A = 25 DC and nominal voltages.t Value calculated from 0.5 volt delta to measured output level.recommended timing requirements for programming T A 25°C (see Note 4)UNITPARAMETERTMS2564MIN Typt MAXtw(PR) Pulse duration, program pulse 9 55 mstr(PR) Rise time, program pulse 5 nstf(PR) Fall time, program pulse 5 nstsu(A) Address setup time 2 p.stsu(D) Data setup time 2 p'stsu(VPP) Setup time from VPP 0 nsth(A) Address hold time 2 p'sth(D) Data hold time 2 p'sth(PR) Program pulse hold time 0 nsth(VPP) VPP hold time 2 p.st Typical values are at nominal voltages.NOTES: 4. Timing measurement reference levels: inputs 0.8 V and 2.2 V, outputs 0.65 V and 2.2 V. and Vpp during programming; 25 V ± 1 V.5. Common test conditions apply for tdis except during programming. For talA). ta(S). and tdis. PD/PGM = Vil'UNITenQ)CJ·SQ)c:Eoa:0..W84TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752656-25

SMJ256465,536-BI1 ERASABLE PROGRAMMABLE READ-ONLY MEMORIESrecommended operating conditions, PARAMETERSMJ2564MIN NOM MAXSupply voltage, VCC (see Note 2) 4.5 5 5.5 VSupply voltage, Vpp (see Note 3) VCC VSupply voltage, VSS 0 VHigh-level input voltage, V,H 2.2 VCC+ 1 VLow-level input voltage, V,L -0.1 t 0.8 VRead cycle time, tc(rd) 450 nsOperating case temperature, T C -55 125 °cUNITNOTES:2. Vee must be applied'before or at the same time as Vpp and removed after or at the same time as Vpp. The device must not be inserted intoor removed from the board when Vpp or Vee is applied so that the device is not damaged.3. Vpp can be connected to Vee directly (except in the program model. Vee supply current in this case would be ICC + Ipp. During programming,Vpp must be maintained at 25 V (± 1 V). .t The algebraic convention, where the more negative limit is designated as minimum, is used in this data sheet for logic voltage levels and time intervals.electrical characteristics over full ranges of recommended operating conditionsm"'C::aos:cCD

SMJ256465,536-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIESswitching characteristics over full ranges of recommended operating conditions (see Note 4)PARAMETERTEST CONDITIONSSMJ2564(SEE NOTES 4 AND 5) MIN MAXtalA) Access time from address 450 nsAccess time from S 1 and S2ta(S)(whichever occurs last)CL = 100 pF. 150 ns1 Series 54/74 TTL Loadta(PR) Access time from PD/PGM450 nsttv(A) Output data valid after address changer :520 ns.0 nstf:520 nsOutput disable time from chip selecttdis(S)See Figure 1 0 100 nsduring read only (whichever occurs last):j:tdis(PR) Output disable time from PD/PGM during standby:!: 0 100 nst All typical values are at T C = 25°C and nominal voltages.t Value calculated from 0.5 volt delta to measured output level.recommended timing requirements for programming TC 25°C (see Note 4)UNITPARAMETERSMJ2564MIN Typt MAXtw(PR) Pulse duration. program pulse 9 55 mstr(PR) Rise time. program pulse 5 nstf(PR) Fall time. program pulse 5 nstsu(A) Address setup time 2 JlStsu(D) Data setup time 2 Jlstsu(VPP) Setup time from Vpp 0 nsth(A) Address hold time 2 Jlsth(D) Data hold time 2 JlSth(PR) Program pulse hold time 0 nsth(VPP) Vpp hold time 2 JlSt Typical values are at nominal voltages.NOTES: 4. Timing measurement reference levels: inputs 0.8 V and 2.2 V. outputs 0.65 V and 2.2 V. and V~ring programming = 25 V ± 1 V.5. Common test conditions apply for tdis except during programming. For talA). tarS). and tdis. PD/PGM = VIL.UNIT..t/)Q)(,)oSQ)C~oa:c..wTEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752656-27

TMS2564, SMJ256465,536-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIESPARAMETER MEASUREMENT INFORMATIONUND~RU;=~; ~:LV = 7BO 0~ CL=100pFFIGURE 1 -TYPICAL OUTPUT LOAD CIRCUITread cycle timingADDRESSESS1 & S2VIHVILVIHVIL--~I\-----X-m"0XI0s:CCDc:ri"CDenPD/PGMVIHVILVOH01-08standby modeADDRESSESVOLVIHVILVIHPD/PGM -01-08VILVOHVOL____ HC-t.IAI=i VALID ____________ A_D_D_R_ES_S_N __________ J~~----------A-D-D-R-ES-s--N-+-m----____ _____________ ~ STANDBY1'Sl_____ A_C_T_IV_Etdis(PR) -il~·--_~I I.. -I ta(PR) r________________ __________ V_A_L_ID ______}- HI-Z -{~-_-----V-A-L-ID---------t talPR) referenced to PD/PGM or the address, whichever occurs last.Sl and 52 in Don't Care State in Standby Mode.6-28 TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

TMS2564 r SMJ256465 r536-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIESprogram cycle timingADDRESSES01-08S1 & S2PD/PGMVPPVIHVILVOHiVlHVOLiVlL++VIHVILII"IPROGRAM ----~.j....-PROGRAM* -'VERIFY ~xl~____V'A-______AD_D_R_ES_S_N _____ -:--___ADDRESSN+mI I ~I------14-- th(A) .1 I______--

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MOSLSITMS2708, TMS27L08, SMJ2708, SMJ27LOe1024-WORD BY 8-BITERASABLE PROGRAMMABLE READ-ONLY MEMORIESDECEMBER 1979 -REVISED AUGUST 19B3ooooo1024 X 8 OrganizationAll Inputs and Outputs Fully TTLCompatibleStatic Operation (No Clocks, No Refresh)Max Access/Min Cycle Time'2708-35'2708-45'27L08-45350 ns450 ns450 ns3-State Outputs for OR-TiesoN-Channel Silicon-Gate Technologyooooodescription8-Bit Output for Use in MicroprocessorBased SystemsPower Dissipation'27L08'2708580 mW Max Active800 mW Max Active10% Power Supply Tolerance(TMS27L08-45 and all SMJ' versions)Plug-Compatible Pin-Outs Allowing Interchangeability/Upgradeto 16K WithMinimum Board ChangeAvailable in Full Military Temperature RangeVersions (SMJ2708)The '2708-35, '2708-45, and '27L08-45 areultraviolet light-erasable, electrically programmableread-only memories. They have 8,192 bits organizedas 1024 words of 8-bit length. The devices arefabricated using N-channel silicon-gate technology forhigh speed and simple interface with MOS and bipolarcircuits. All inputs (including program data inputs) canbe driven by Series 54/74 TTL circuits without the useof external pull-up resistors. Each output can drive oneSeries 54/74 or 54LS/74LS TTL circuit without externalresistors. The '27L08 guarantees 200 mV dcnoise immunity in the high state and 250 mV in thelow state. The data outputs for the '2708-35,'2708-45, and 'Z7L08-45 are three-state for OR-tyingmUltiple devices on a common bus.A5A4NCA3A2A1AO0102AO-A7NCPGM01-08S(PE)VBBVCCVDDVSSTMS2708 ... JL PACKAGESMJ2708 ... J PACKAGE(TOP VIEW)A7VCCA6A8A5A9A4VBBA3S(PE)A2VDDA1PGMAO 0801 0702 0603 05VSS 04SMJ2708 ... FE PACKAGE(TOP VIEW)U(O!'oUUUUCO z

TMS2708. TMS27L08SMJ2708. SMJ27L081024·WORD BY 8·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORIESThese EPROMs are designed for high-density fixed-memory applications where fast turn arounds and/or program changesare required. The TMS' Series is supplied in a 24-pin dual-in-line ceramic cerdip (JL suffix) package designed for insertionin mounting-hole rows on 600-mil (15.2 mm) centers. They are designed for operation from OoC to 70°C.The SMJ' Series is offered in a 24-pin dual-in-line ceramic package (J) and also in a 32-pin lead less ceramic chip carrier(FE). The J package is designed for i,nsertion in mounting-hole rows on 600-mil (15.2 mm) centers whereas theFE package is intended for surface mounting on solder pads on 0.05-inch (1.27 mm) centers. The FE package is athree-layer 32-pad rectangular chip carrier with dimensions of 0.450 x 0.550 xO.1 00 inches (11.43 x 13.97 x 2.54mm). This series is designed for operation from - 55°C to 125°C.operation (read mode)address (AO-A9)The address-valid interval determines the device cycle time. The 10-bit positive-logic address is decoded on-chip toselect one of the 1024 words of 8-bit length in the memory array. AO is the least-significant bit and A9 is the mostsignificantbit of the ,Word address.chip select, program enable [5 (PE)]When the chip select is low, all eight outputs are enabled and the eight-bit addressed word can be read. When thechip select is high, all eight outputs are in a high-impedance state.data out (Q1-Q8)The chip must be selected before the eight-bit output word can be read. Data will remain valid until the address ischanged or the chip is deselected. When deselected, the three-state outputs are in a high-impedance state. The outputswill drive TTL circuits without external components.programThe program pin must be held below VCC in the read mode.m::c "os:cCD

TMS270B, TMS27LOBSMJ270B, SMJ27LOB1024·WORD BY B·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORIESProgramming continues in this manner until all words have been programmed. This constitutes one of N program loops.The entire sequence is then repeated N times with N x tw(PR} 2: 100 ms. Thus, if tw(PR} = 1 ms; then N = 100,the minimum number of program loops required to program the EPROM.to stop programmingAfter cycling through the N program loops, the last program pulse is brought to 0 V, then Program Enable [5 (PE)]is brought to VIL which takes the device out of the program mode. The data supplied by the programmer must beremoved before the address is changed since the program inputs are now data outputs and change of address couldcause a voltage conflict' on the output buffer. 01-08 outputs are invalid up to 10 microseconds after the programenable pin is brought from VIH(PE} to VIL.logic symbol tAO 0EPROM 1024x8(9)A\l(10) 01A\l(11) 02A\l(13) 03A_ O _ A\l1023 (14) 04A\l 05A\l(15)06A\l 07A\l 08tThis symbol is in accordance with IEEE Std 91/ANSI Y32.14 and recent decisions in IEEE and IEC. See explanation on page 10-1.absolute maximum ratings over operating free-air temperature range (unless otherwise noted):t:Supply voltage, VBB (see Note 1) ...........................................'. . .. - 0.3 V to 7 VSupply voltage, Vee (see Note 1) ............................................. , -0.3 V to 15 VSupply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 20 VSupply voltage, VSS (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 15 VAll input voltage (except program) (see Note 1) ................................... , - 0.3 V to 20 VProgram input (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 35 VOutput voltage (operating, with respect to VSS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -2 V to 7 VOperating free-air temperature range: TMS' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . oDe to 70 0 eOperating case temperature range: SMJ' ...................................... , - 65°C to 150 DeStorage temperature range ................................................. , - 55 DC to 125 DC(/)Q)(.)'S;Q)C~oa:a..wt Stresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functionaloperation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specificationis not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.NOTE 1: Under absolute maximum ratings, voltage values are with respect to the most-negative supply voltage. VSS (substrate), unless otherwise noted.Throughout the remainder of this data sheet, voltage values are with respect to VSS.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752656-33

TMS2708. TMS27L081024·WORD BY 8·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORIES.m"'0::lJos:cCD

TMS2708. TMS27L081024·WORD BY 8·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORIESswitching characteristics over recommended supply voltage range and operating free-air temperature rangePARAMETERTEST CONDITIONSTMS2708-35TMS2708TMS27LOBMIN MAX MIN MAXtalA) Access time from Address 350 450 nsta(S) Access time from S CL = 100 pF 120 120 nstv(A) Output data valid after addresschange 1 Series 54/14 TTL load 0 0 nstdis Output disable time t tf(S), tf(A) = 20 ns 0 120 0 120 nstc(rd) Read cycle time 350 450 nsUNITtValue calculated from 0.5 volt delta to measured output level.recommended timing requirements for programming T APARAMETERtwJPR) Pulse duration, program pulse 0.1 1 mstt Transition times (except program pulse) 20 nstt(PR) Transition times, program pulse 50 2000 nstsu(A) Address setup time 10 p'stsu(D) Data setup time 10 p'stsu(PE) Program enable setup time 10 p'sth(A) Address hold time 1000 nsthIDA) Address hold time after program input data stopped 0 nsth(D) Data hold time 1000 nsth(PE) Program enable hold time 500 nstSLAX Delay time, S(PE) low to address change 0 nsMINTMS'MAX'UNITenQ)U'S;Q)C~oa:Q.WTEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752656-35

SMJ2708, SMJ27L081024-WORD BY 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIESrecommended operating conditionsPARAMETERSMJ2708-35SMJ2708-45SMJ27L08-45MIN NOM MAX MIN NOM MAXSupply voltage, VBB -4.75 -5 -5.25 -4.5 -5 -5.5 VSupply voltage, Vee 4.75 5 5.25 4.5 5 5.5 VSupply voltage, VDD 11.4 12 12.6 10.8 12 13.2 VSupply voltage VSS 0 0 VHigh-level input voltage, VIH(except program and program enable2.4 Vee+ 1 2.2 Vee+ 1High-level program enable input voltage, VIHIPE) 11.4 12 12.6 10.8 12 13.2 VHigh-level program input voltage, VIH(PR) 25 26 27 25 26 27 VLow-level input voltage, VIL (except program) VSS 0.65 VSS 0.65 VLow-level program input voltage, VIL(PR)Note: VIL(PR) max :5 VIH(PR) - 25 VUNITVSS 1 VSS 1 VHigh-level program pulsle input current (sink), IIH(PR) 40 40 mALow-level program pulse input current (source). IIL(PR) 3 3 mAOperating case temperature, ,Tc -55 125 -55 125 °eelectrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)m"'C:Do~CI'D

SMJ2708, SMJ27L081024·WORD BY 8·BIT ERASABLE PROGRAMMABLE READ·ONL Y MEMORIESswitching characteristics over recommended supply voltage range and operating case temperature rangePARAMETERTEST CONDITIONSSMJ2708-35SMJ2708SMJ27L08MIN MAX MIN MAXtalA) Access time from Address 350 450 nstarS) Access time from S CL = 100pF 120 120 nstv(A) Output data valid after address change 1 Series 54/74 TTL load 0 0 nstdis Output disable time t tf(S), tf(A) = 20 ns 0 120 0 120 nstc(rd) Read cycle time 350 450 nsUNITtValue calculated from 0.5 volt delta to measured output level.recommended timing requirements for programming TCPARAMETERSMJ'MIN MAXUNITtw(PR) Pulse duration, program pulse 0.1 1 mstt Transition times (except program pulse) 20 nstt(PR) Transition times, program pulse 50 2000 nstsu(A) Address setup time 10 JlStsu(D) Data setup time 10 JlStsu(PE) Program enable setup time 10 Jlsth(A) Address hold time 1000 nsthIDA) Address hold time after program input data stopped 0 nsth(D) Data hold time 1000 nsth(PE) Program enable hold time 500 nstSLAX Delay time, S(PE) low to address change 0 nstilC1)CJ.S;C1)c:Eoa:c..wTEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752656-37

TMS2708. TMS27L08SMJ2708. SMJ27L081024-WORD BY 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIESPARAMETER MEASUREMENT INFORMATIONv = 2.4 VJRL = 310 nOUTPUTUNDER TESTJ CL = 100 pFm"'tJ:00~CCDIXtv(A) --I I+- I1 OF N* PROGRAM LOOPSNOT VAllO t((~tdiS~VALIDth(PE)E1rtfIILr-}----HI-Z-~ADDRESSES ADDRESS 0 ADDRESS 1 ... 1022ProgramPulseVILVIH(PR)VIL(PR)01-08PROGRAMVIH3INPUTS VILt ~tsu(A).., ~ th(A) ~ M; tsulA) th(A):ILt- twlPR) -+I1-tWI'RI~'Ltsu(D) +I I+- thlD) -.I -p;- 1+ th(D)~ -PrX t'UI , :. OUTPUTINPUTUT·s IPE) is at + 12 V through N program loops where N < 1 00 msitw (PR).NOTE: 01-08 outputs are invalid up to 10 "sec after programming is (PE) goes lowl.All timing reference points in this data sheet (inputs and outputs) are 90% points.tINPUTthIDA)6-38 TEXASINSTRUMENTSPOST OFFICE BOX 225012 • OALLAS. TEXAS 75265

TMS2708, TMS27L08SMJ2708, SMJ27L081024·WORD BY 8·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORIESTYPICAL '27L08·45 CHARACTERISTICS800DEVICE POWER DISSIPATION vs TEMPERATURECURRENT vs TEMPERATURE40r----r----r---,---~----r---_r--_,:;:Ec0.;:::caCo.~i5700~~0a.. 300IQa..600/I.f.qX,............... ~/l.fI.J/I.f_500.............. wOr.s t~a.se~'t' 101).s400I--200E~:;(.)>---: C.Co~:::Ienr--r--:::':::' cYcle-r--10---r----:YPICAL - 65% I100S==5VoO~--~--~~--~--~----~--~--~o 10 20 30 40 50 60 70 o 10 20 30 40 50 60 70T A - Free-Air Temperature - DC T A - Free-Air Temperature - DC3020STATIC OUTPUT VOLTAGE vs OUTPUT CURRENTACCESS TIME vs TEMPERATURE>CD0154.543.5II 30>;Co;0.gcaen0.80.60.40.2~r------~~TYPICAL CONDITIONS..............~'-IO\. -' ~~...-..co ~ ~ oo 2 3 4 5 o 10 20 30 40 50 60 704003001'lP\C~,!--....-- ---~I----~CDEj:: 200..CDUU~100TYPICAL talCS)10 - Output Current - mA T A - Free-Air Temperature - °CTexas Instruments reserves the right to make changes at any time in orde~ to improve design and to supply the best product possible.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752656-39

IIm"'C:XJo~c(I)

MOSLSITMS27162048·WORD BY 8·BIT ERASABLEPROGRAMMABLE READ·ONLY MEMORI~SDECEMBER 1979 - REVISED OCTOBER 1983• 2048 X 8 Organization• All Inputs and Outputs Fully TTL Compatible• Static Operation (No Clocks, No Refresh)• Performance Ranges:TMS2716-30TMS2716-45ACCESS TIME(MAX)300 ns450 ns• 3·State Outputs for OR· Ties• N·Channel Silicon-Gate TechnologyCYCLE TIME(MIN)300 ns450 ns• 8-Bit Output for Use in MicroprocessorBased Systems• Low Power ... 315 mW (Typical)descriptionThe TMS2716 is an ultra-violet light-erasable, electricallyprogrammable read-only memory. It has16,384 bits organized as 2048 words of 8-bit length.The device is fabricated using N-channel silicon-gatetechnology for high-speed and simple interface withMOS and bipolar circuits. All inputs (including programdata inputs) can be driven by Series 74 circuitsAO-Al001-08SIPGM)VBBVee(PE)VDDVSSTMS2716 ... JL PACKAGE(TOPVIEWIA7Vee(PEIA6A8A5A9A4VBBA3Al0A2VDDAlS(PGM)AO 0801 0702 0603 05VSS 04PIN NOMENCLATUREAddressesData Outehip Select (Program)-5-V Supply+ 5-V Supply (Program Enable)+ 12-V Supplyo V Groundwithout the use of external pull-up resistors and each output can drive one Series 74 or 74LS TTL circuit withoutexternal resistors. The TMS2716 guarantees 250 mV dc noise immunity in the low state. Data outputs are threestatefor OR-tying multiple devices on a common bus. The TMS2716 is plug-in compatible with the TMS2708 andthe TMS27L08. Pin compatible mask programmed ROMs are available for large volume requirements.This EPROM is designed for high-density fixed-memory applications where fast turn arounds and/or program changesare required. It is supplied in a 24-pin dual-in-line cerpak (JL suffix) package designed for insertion in mounting-holerows on 600-mil (15,2 mm) centers. It is designed for operation from ooe to 70°C.operation (read mode)address (AO-A 10)The address-valid interval determines the device cycle time. The ll-bit positive-logic address is decoded on-chip toselect one of 2048 words of 8-bit length in the memory array. AO is the least-significant bit and A 1 0 most-significantbit of the word address.enCDCJ'SCDC~oa:c..wchip select, program [5 (PGM)]When the chip select is low, all eight outputs are enabled and the eight-bit addressed word can be read. When thechip select is high, all eight outputs are in a high-impedance state.programIn the program mode, the chip select feature does not function as pin 18 inputs only the program pulse. The programmode is selected by the Vee(PE) pin. Either 0 V or + 12 V on this pin will cause the TMS2716 to assume program cycle.data out (01-08)The chip must be selected before the eight-bit output word can be read. Data will remain valid until the address ischanged or the chip is deselected. When deselected, the three-state outputs are in a high-impedance state. The outputswill drive TTL circuits without external components.TEXASINSTRUMENlSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1983 by Texas Instruments Incorporated6-41

TMS27162048·WORD BY 8·BIT ERASABLEPROGRAMMABLE READ·ONLY MEMORIESoperation (program mode)eraseBefore programming, the TMS2716 is erased by exposing the chip through the transparent lid to high intensity ultravioletlight (wavelength 2537 angstroms). The recommended minimum exposure dose (= UV intensity x exposure time)is fifteen watt-seconds per square centimeter. Thus, a typical 12 milliwatt per square centimeter, filterless UV lampwill erase the device in a minimum of 21 minutes. The lamp should be located about 2.5 centimeters above the chipduring erasure. After erasure, all bits are in the high state.programmingProgramming consists of successively depositing a small amount of charge to a selected memory cell that is to bechanged from the erased high state to the low state. A low can be changed to a high only by erasure. Programmingbe normally accomplished on a PROM or EPROM Programmer, an example of which is TI's Universal PROM ProgrammingModule in conjunction with the 990 prototyping system. Programming must be done at room temperature (25 °elonly.to start programming (see program cycle timing diagram)First bring the Vee(PE) pin to + 12 V or 0 V to disable the outputs and convert them to inputs. This pin is held highfor the duration of the programming sequence. The first word to be programmed is addressed (it is customary to beginwith the "0" address) and the data to be stored is placed on the 01-08 program inputs. Then a + 26 V programpulse is applied to the program pin. After 0.1 to 1.0 milliseconds the program pin is brought back to 0 V. After atleast one microsecond the word address is sequentially changed to the next location, the new data is set up and theprogram pulse is applied.Programming continues in this manner until all words have been programmed. This constitutes one of N program loops.The entire sequence is then repeated N times with N x tw(PR) ~ 100 ms. Thus, if tw(PR) = 1 ms; then N = 100,the minimum number of program loops required to program the EPROM. .m"tJ::Do!:oCD

TMS27162048·WORD BY 8·BIT ERASABLEPROGRAMMABLE READ·ONLY MEMORIESabsolute maximum ratings over operating free-air temperature range (unless otherwise noted) tSupply voltage, VBB (see Note 1)Supply voltage, Vee (see Note 1)Supply voltage, VOO (see Note 1)Supply voltage, VSS (see Note 1)All input voltage (except program) (see Note 1) ................................. .-0.3 V to 7 V-0.3 V to 15 V-0.3 V to 20 V-0.3 V to 15 V-0.3 V to 20 VProgram input (see Note 1) ................................................ . -0.3 V to 35 VOutput voltage (operating, with respect to VSS) ................................... . -2 V to 7 VOperating free-air temperature range ........................................... . ooe to 70 e0Storage temperature range ................................................ - 55°C to 125°et Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functionaloperating of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specificationis not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTE 1: Under absolute maximum ratings, voltage values are with respect to the most-negative supply voltage, VSS (substrate), unless otherwise noted.Throughout the remainder of this data sheet, voltage values are with respect to VSS'recommended operating c.onditionsPARAMETER MIN NOM MAX UNITSupply voltage, Vaa -4.75 -5 -5.25 VSupply voltage, Vee 4.75 5 5.25 VSupply voltage, VOO 11.4 12 12.6 VSupply voltage, VSS 0 VHigh-level input voltage, VIH (except program and program enable) 2.4 Vee+ 1 VHigh-level program enable input voltage, VIH(PE) 11.4 12 12.6 VHigh-level program input voltage, VIH(PR) 25 26 27 VLow-level input voltage, VIL (except program) VSS 0.65 VLow-level program input voltage, VIL(PR)Note: VIL(PR) max :$ VIH(PR) - 25 VVSS 1 VHigh-level program pulse input current (sink), IIH(PR) 40 rnALow-level program pulse input current (source), IIL(PR) 3 rnAOperating free-air temperature, T A 0 70 °eelectrical characteristics over full ranges of recommended operating conditions (unless otherwise noted)PARAMETER TEST CONDITIONS MIN Typt MAX UNITVOH High-level output voltage10H = -100 p.A 3.710H = -1 rnA 2.4VVOL Low-level output voltage 10L = 1.6 rnA 0.45 VII Input current (leakage) VIL = 0 V to 5.25 V 1 10 p.A10 Output current (leakage) S (Program) = 5 V, \/0 = 0.4 V to 5.25 V 1 10 p.Alaa Supply current from Vaa All inputs high, 10 20 rnAICC Supply current from Vee S (Program) = 5 V, 1 8 rnA100 Supply current from VOOTA = ooe(worst case)26 45 rnAIpE Supply current from PE on Vee Pin VPE = VOO 2 4 rnATA = 70 0 e 540PO(AV) Power Oissipation TA = ooe S = 0 V 315 595 mWTA = ooe S = +5 V 375 720C/)Q)(,).S;Q)C~oa:Q.Wt All typical values are at T A = 25°C and nominal voltages.184TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752656-43

TMS27162048·WORD BY 8·BIT ERASABLEPROGRAMMABLE READ·ONLY MEMORIEScapacitance over recommended supply voltage range and operating free-air temperature range, fPARAMETER Typt MAXCi Input capacitance [except S (Program)) 4 6Ci(S) S (Program) input capacitance 20 30Co Output capacitance 8 121 MHzUNITpFpFpFt All typical values are at TA =' 25°C and nominal voltages.switching characteristics over recommended supply voltage range and operating free-air temperature rangeTMS2716-30PARAMETERTEST CONDITIONSMIN MAXtalA) Access time from address300CL = 100 pFta(S) Access time from S1201 Series 74 TTL Loadtv(A) Output data valid after address change0tf(S), tf(A) = 20 nstdis Output disable time t0 120See Figure 1tc(rd) Read cycle time300TMS2716-45MINMAXUNIT450 ns120 ns0 ns0 120 ns450 nst Value calculated from 0.5 volt delta to measured output level.T A = 25°C program characteristics over recommended supply voltage rangem··"C:lJos:cCDc:::(;'CD(I)tw(PR)tttt(PR)tsu(A)tsu(D)tsu(PE)th(A)thIDA)th(D)th(PE)tSLAXPARAMETERPulse duration, program pulseTransition times (except program pulse)Transition times, program pulseAddress setup timeData setup timeProgram enable setup timeAddress hold timeAddress hold time after program input data stoppedData hold timeProgram enable hold timeDelay time, S (Program) low to address changeMIN MAX UNIT0.1 1 ms20 ns30 2000 ns10 p's10 p's10 p's1000 ns0 ns1000 ns500 ns0 nsPARAMETER MEASUREMENT INFORMATIONv = 2.4 VOUTPUT ~ RL 3100UNDER TEST f 00 FrCl = 1 PFIGURE 1 -TYPICAL OUTPUT lOAD CIRCUIT6-44 TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265. 184

TMS27162048-WORD BY 8-BIT ERASABLEPROGRAMMABLE READ-ONLY MEMORIESread cycle timingADDRESSESS IPGM)VIHVILVIHVILVOH•I-IIIIIIII-01-08 HI-Z,VOLtclrd)ADDRESSES VALID\taIS)~(taIA)~-II- tclrd) -I!ADDRESSES VALIDIIII"II,II I-- talA) --"""1VALIDtvIA)--I 1_VALID~ t}-HI.Z_'NOT VALIDI~ ~tdis=program cycle timingVIHIPE)VeelPE)t ~~ADDRESSES1 OF Nt PROGRAM LOOPS ----------a--lltr--------:--------! j~-------4LVee ~ tsulPE) thlPE) ---iVILVIHIPR)~ I -H r- tSLAXI 1m,ADDRESS 0 ADDRESS 1 ... 2046 ( ADDRESS Z047 J.J:lJ.1r\LI.- thlA) -, -Fr ~ tsulAI theA) ~ -;;=r r.- tsulA) 1\ I: r-- tW(PR)--iul I ~ twIPR) --l=t;J I II I--- twIPR) ~ IS IPGM) --------"II I . I. I :VILIPR)--.tsulD) -1 f.- thlD) --j --F1 ~ tsulD) thID)., --l=1 I- tsu(D) thlD) ~ thIDA)=i;~AM :~~----IN-P-U-T---~X IN~T )t INPUTE~T-enQ)(,)'>Q)C~oa:c..wt VCC(PE) is at a v or + 12 V through N program loops where N

6-46

TMS2732A32,76B-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORYAUGUST 1983• Organization ... 4096 X 8• Single + 5-V Power Supply• ,All Inputs and Outputs Are TTL Compatible• Performance Ranges:TMS2732A-30TMS2732A-35TMS2732A-45ACCESS TIME(MAX)300 ns350 ns450 ns• Low Standby Power Dissipation ...158 mW (Maximum)CYCLE TIME(MIN)300 ns350 ns450 ns• JEDEC Approved Pinout ... IndustryStandard• 21-V Power Supply Required forProgramming• N-Channel Silicon-Gate Technology• 8-Bit Output for Use in MicroprocessorBased Systems• Static Operation (No Clocks, No Refresh)TMS2732A •.. JL PACKAGE(TOP VIEW)A7A6A5A4A3A2AlVeeA8A9AllGivppA1DEAD 0801 0702 0603 05GND 04PIN NOMENCLATUREAO -EAll Addressesehip EnableG/Vpp Output Enablel + 21 V01 - 08VeeOutputs+ 5-V Power Supply• Available with MIL-STD-883B Processing and L(OoC to 70°C), E(-400C to 85°C), or S(-55°C to100°C) Temperature Ranges in the FuturedescriptionThe TMS2732A is an ultraviolet light-erasable, electrically programmable read-only memory. It has 32,768 bits organizedas 4,096 words of 8-bit length. The TMS2732A only requires a single 5-volt power supply with a tolerance of ± 5%.The TMS2732A provides two output control lines: Output Enable (

TMS2732A ,32,768-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORYreadThe two control pins (E' and G/Vpp) must have low-level TTL signals in order to provide data at the outputs. Chipenable iE"l should be used for device selection. Output enable (G/Vpp) should be used to gate data to the output pins.power downThe power-down mode reduces the maximum power dissipation from 657 mW to 158 mW. A TTL high-level signalapplied to E selects the power down mode. In this mode, the outputs assume a high-impedance state, independentof G/Vpp.programThe programming procedure for the TMS2732A is the same as that for the TMS2532, except that in the programmode, G/Vpp is taken from a TTL low-level to 21 V.The program mode consists of the following sequence of events. With the level on G/Vpp equal to 21 V; data tobe programmed is applied in parallel to output pins Q8 - Q 1. The location to be programmed is addressed. Oncedata and addresses are stable, a 1 O-millisecond TTL low-level pulse is applied to E. The maximum width of this pulseis 55 milliseconds. The programming pulse must be applied at each location that is to be programmed. Locations maybe programmed in any order./Several TMS2732As can be programmed simultaneously by connecting them in parallel and following the programmingsequence previously described.program verifyAfter the EPROM has been programmed, the programmed bits should be verified. To verify bit states, G/Vpp and Eare set to VIL.program inhibitm""0:lJo3:cCD

TMS2732A32,768-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORYlogic symbol tAOA1A2A3A4A5A6A7A8A9A10A11EGIVpp(8) EPROM 4096 x 80(7)(6)(9)(5) A\l 01(4) A\l(10)02(3) A\l 03(2)A_O_A\l 04(1 ) 4095 A \l 05(23) A\l 06(22) A\l Q7(19) A\l 08(21)(18)11[PWR DWNI&(20) ENtThis symbol is in accordance with IEEE Std 91/ANSI Y32.14 and recent decisions by IEEE and IEC. See explanation on page 10-1.absolute maximum ratings over operating free-air temperature range (unless otherwise noted):t:Supply voltage, Vee ...... _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to 7 VSupply voltage, Vpp .................................. _ ...................... -0.3 V to 22 VAll input voltage (except program) .............................................. -0.3 V to 7 VOutput voltage ........ ' ......................... '. . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 7 VOperating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooe to 70 0 eStorage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 °e to 125°et Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functionaloperation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specificationis not implied. Exposure to absol~te-maximum-rated conditions for extended periods may affect device reliability.t/)Q)(.).S;Q)C~oa:c..wrecommended operating conditionsPARAMETERTMS2732A-30 TMS2732A-35 TMS2732A-45MIN NOM MAX MIN NOM MAX MIN NOM MAXSupply voltage, Vee (see Note 1) 4.75 5 5.25 4.75 5 5.25 4.75 5 5.25 VSupply voltage, Vpp (see Note 2) Vee Vee Vee VSupply voltage, VSS 0 0 0 VHigh-level input voltage, VIH 2 Vee+ 1 2 Vee+ 1 2 Vce+ 1 VLow-level input voltage, VIL -0.1 0.8 -0.1 0.8 -0.1 0.8 VRead cycle time, tc(rd) 300 350 450 nsOperating free-air temperature, T A 0 70 0 70 0 70 °eINOTES: 1. VCC must be applied before or at the same time as Vpp and removed after or at the same time as Vpp. The device must not be inserted intoor removed from the board when Vpp or VCC is applied.2. Vpp can be connected to VCC directly (except in the program model. VCC supply current in this case would be ICC + Ipp. During programming,Vpp must be maintained at 21 V (±0.5 VI.UNITTEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752656-49

TMS2732A32,768·BITERASABLE PROGRAMMABLE READ·ONLY MEMORY,electrical characteristics over full ranges of recommended operating conditionsPARAMETER TEST CONDITIONS MIN Typt MAX UNITVOH High-level output voltage 10H= -400 p.A 2.4 VVOL Low-level output voltage IOL=2.1 rnA 0.45 VII Input current (leakage) VI=O V to 5.25 V ±10 p.A10 Output current (leakage) VO=O.4 V to 5.25 V ±10 p.AICC1 VCC supply current (standby) E at VIH, G at VIL 20 30 rnAICC2 VCC supply current (active) E and G at VIL 70 125 rnAtTypical values are at T A = 25°C and nominal voltages.capacitance over recommended supply voltage range and operating free-air temperature range, f1 MHzCiPARAMETER TEST CONDITIONS MIN Typt UNITI All except G/Vpp 4 6Input capacitance I IT VI = 0 V pF/Vpp 20Co Output capacitance Vo = 0 V 12 pFtTypical values are at TA=25°C and nominal voltage.switching characteristics over recommended supply voltage range and operating free-air temperature rangem.":Do3:talA)talE)ten(Gltdis(E):j:tdis(G)+tv(A)PARAMETERAccess time from addressAccess time from EOutput enable time from GOutput disable time from EOutput disable time from GOutput data valid time afterchange of address, E, or G,TEST CONDITIONS(See Note 3)CL=100pF,1 Series 74 TTL Load,t r $20 ns,tf$20 ns,See Figure 1whichever occurs firstcCD< NOTE 3. Timing measurement reference levels: inputs 0.8 V and 2 VC:;" outputs 0.8 V and 2 V.~ tValue calculated from 0.5 V delta to measured output level.recommended conditions for programming, T A = 25°CTMS2732A-30 TMS2732A-35 TMS2732A-45UNITMIN MAX MIN MAX MIN MAX300350 450 ns300350 450 ns150150 150 ns100100 100 ns100100 100 ns00 0 nsVCCVppVIHVILtw(~tsu(A)tsu(D)tsu(VPP)th(A)th(D)th(VPP)trec(PG)tEHDPARAMETERSupply voltageSupply voltageHigh-level input voltageLow-level input voltageE pulse durationAddress setup timeData setup timeVpp setup timeAddress hold timeData hold timeVPP hold timeVPP recovery timeDelay time, data valid after E lowMIN TYP MAX UNIT4.75 5 5.25 V20.5 21 21.5 V2 VCC+1 V-0.1 0.8 V9 55 ms2 p'S2 p'S2 P.s0 p'S2 p'S2 P.s2 P.s1 P.s6-50TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 7526511

TMS2732A32,768·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORYprogramming characteristics. T A = 25 DCVIHVIIVOHVOLIIIppICCtdis(PR)PARAMETERHigh-level input voltageLow-level input voltageHigh-level output voltage (verify)Low-level output voltage (verify)Input current (all inputs)Supply currentSupply currentOutput disable timeTEST CONDITIONS!illi = - 400 p.AIOL =2.1 mAVI = VIL or VIHE=VIL. G = VppMIN TYP MAX UNIT2 VCC+l V-0.1 0.8 V2.4 V0.45 V10 p.A30 mA125 mA0 100 nsPARAMETER MEASUREMENT INFORMATIONOUTPUT ~UNOERTEST~V = 2.09 VRL ~ 780 0T CL = 100pFFIGURE 1 - TYPICAL OUTPUT LOAD CIRCUITenQ)(,).S;Q)C~aa:Q.w4TEXASINsrRUMENlSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752656-51

TMS2732A32,768-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORYread cycle timingADDRESSESGiVpp01-08standby modeVIHADDRESSESVILVIHEVILVOH01-08VOLXt \'d;'IEI~)--HI~~I»m-0::XJos:cCD

MOSLSITMS276465,536-BI1 ERASABLE PROGRAMMABLE READ-ONLY MEMORYJULY 1983 - REVISED JANUARY 1984• Organization ... 8192 X 8• Single + 5-V Power Supplyo Pin Compatible with TMS2732A EPROMo All Inputs and Outputs are TTL Compatible• Performance Ranges:TMS2764-20TMS2764-25TMS2764-30TMS2764-35TMS2764-45MAX ACCESSIMIN CYCLE TIME200 ns250 ns300 ns350 ns450 nso Low Active Current ... 100 rnA (Max)o JEOEC Approved Pinouto 21-V Power Supply Required forProgrammingo Fast Programming AlgorithmON-Channel Silicon-Gate Technologyo 8-Bit Output for Use in MicroprocessorBased Systems• Static Operation (No Clocks, No RefreshIt Available with MIL-STO-883B Processingand L(O °C to 70°C), E( - 40°C to 85 °C). orM( - 55°C to 125°C) Temperature Rangesin the FuturedescriptionTMS2764 ... JL PACKAGE(TOP VIEW)VPPVCCA12PGMA7NCA6A8A5A9A4A11A3GA2A10A1EAO 0801 Q702 0603 05GND 04PIN NOMENCLATUREAO-A 12 AddressesEChip EnableOutput EnableGGNDNCPGM01-08VCCVPPGroundNo ConnectionProgramoutputs+ 5-V Power Supply+21-V Power SupplyThe TMS2764 is an ultraviolet light-erasable, electrically programmable read-only memory. It has 65,536 bits organizedas 8,192 words of 8-bit length. The TMS2764-20 only requires a single 5-volt power supply with a tolerance of ±5%,and has a maximum access time of 200 ns. This access time is compatible with high-performance microprocessors.The TMS2764 provides two output control lines: Output Enable (G) and Chip Enable {E). This feature allows the Gcontrol line to eliminate bus contention in microprocessor systems. The TMS2764 has a power-down mode that reducesmaximum active current from 100 mA to 35 mA when the device is placed on standby.This EPROM is supplied in a 28-pin, 600-mil dual-in-line ceramic package and is designed for operation from 0 DC to 70 DC.enQ)CJ'S;Q)C~oa:Q.WoperationThe six modes of operation for the TMS2764 are listed in the following table.34ADVANCE INFORMATIONThis document contains Information on 8 new product.Specifications are subject to change without notice.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265Copyright © 1984 by Texas Instruments Incorporated6-53

1MS276465,536-B11 ERASABLE PROGRAMMABLE READ-ONLY MEMORYFUNCTION(PINS)E(20)G(22)PGM(27)Vpp(1)Vee(28)01-08ReadMODEOutput Power Down Fast Program InhibitDisable (Standby) Programming Verification ProgrammingVIL X VIH VIL VIL VIHVIL VIH XVIH VIL XVIH VIH X VIL VIH XVee Vee Vee Vpp Vpp XVee Vee Vee Vee Vee Vee(11 to 13, 0 HI-Z HI-Z 0 0 HI-Z15 to 19)readThe dual control pins (E and G) must have low-level TTL signals in order to provide data at the outputs. ehip eanble(E) should be used for device selection. Output enable (G) should be used to gate data to the output pins.power downThe power-down mode reduces the maximum active current from 100 mA to 35 mAo A TTL high-level signal appliedto E selects the power-down mode. In this mode, the outputs assume a high-impedance state, independent of G.m."::rJo3:cm

TMS276465,536·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORYmUltiple device programmingSeveral TMS2764's can be programmed simultaneously by connecting them in parallel and following the programmingsequence previously described.program inhibitIThe program inhibit is useful when programming multiple TMS2764's connected in parallel with different data. Programinhibit can be implemented by applying a high-level signal to E or PGM of the device that is not to be programmed.DEVICEFAILEDINCREMENTADDRESSDEVICEFAILEDU)Q)(,)':;Q)c:2:oa:a.wFIGURE 1 -FAST PROGRAMMING FLOWCHARTTEXASINSTRUMENlSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752656-55

. TMS276465,536·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORYlogic· symbol t(10) EPROM 8192x8AO 0(9)Al(8)A2(11 )(7) A\l Q1A3(6) A\l 02A4(5) A\l 03A5(4)o A \l 04A6 A-(3) 8191 A \l 05A7(25)A\l 06A8(24)A\l 07A9(21)A\l 08Al0(23)All(2)A1212(20)[PWR OWN)EG&(22) ENm"'0:lIo3:cCD

TMS276465,536-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORYelectrical characteristics over full ranges of recommended operating conditionsIIIPARAMETER TEST CONDITIONS MIN Typt MAX UNITVOH High-level output voltage IOH = -400 p,A 2.4 VVOL Low-level output voltage IOL = 2.1 rnA 0.45 VII Input current (load) VI = 0 V to 5.25 V ±10 p,A10 Output current (leakage) Vo = 0.4 V to 5.25 V ±10 p,AIpPl Vpp supply current (read) Vpp = 5.25 V 5 rnAIpP2 Vpp supply current (program) i: and ~ at VIL 50 rnAICCl VCC supply current (standby) Eat VIH 35 rnAICC2 VCC supply current (active) E and G at VIL 100 rnAt Typical values are at T A = 25°C and nominal voltages.capacitance over recommended supply voltage range and operating free-air temperature range, f1 MHzPARAMETER TEST CONDITIONS MIN Typt MAX UNITCi Input capacitance VI = 0 V 4 6 pFCo Output capacitance Vo = 0 V 8 12 pFt Typical values are at T A = 25°C and nominal voltages.switching characteristics over recommended supply voltage range and operating free-air temperature range,CL = 100 pF, 1 Series 74 TTL load (see note 2 and figure 2)PARAMETERTMS2764-20 TMS2764-25 TMS2764-30 TMS2764-35 TMS2764-45MIN MAX MIN MAX MIN MAX MIN MAX MIN MAXtalA) Access time from address 200 250 300 350 450 nstalE) Access time frm E 200 250 300 350 450 nsten (G) Output enable time from G 75 100 120 150 150 nstdis(G)t Output disable time from G 0 60 0 85 0 105 0 130 0 130 nsOutput data valid time aftertv (A) change of address, E, or G, 0 0 0 0 0 nswhichever occurs firstNOTE 2:Fall all switching characteristics and timing measurements, input timing reference levels are 0.8 V and 2 V; output timing reference levels are 0.8 Vand 2 V.t Value calculated from 0.5 volt delta to measured output level; tdis(G) is specified from G or f. whichever occurs first. Refer to read cycle timing diagram.UNITf/)Q)(.)-s;Q)c~oa:Q.W184TEXASINSTRUMENTSPOST OFFICE BOX 225012 • OALLAS. TEXAS 752656-57

TMS276465,536-BI1 ERASABLE PROGRAMMABLE READ-ONLY MEMORYrecommended conditions for fast programming routine. T Acycle timing diagram)25°C (see note 2 and fast programmingPARAMETER MIN NOM MAX UNITVcc Supply voltage (see Note 3) 5.75 6 6.25 VVPP Supply voltage (see Note 4) 20.5 21 21.5 Vtw(lPGM) PGM initial program pulse duration (see Note 5) 0.95 1 1.05 mstw(FPGM) PGM final pulse duration (see Note 6) 3.8 63 mstsu(A) Address setup time 2 p'stsu(D) Data setup time 2 p'stsu(VPP) VPP setup time 2 p'stsu(VCCI VCC setup time 2 p'sth(A) Address hold time 0 p'sth(D) Data hold time 2 p'stsu(E) E setup time 2 p'stsu(G) G setup time 2 ",sfast programming characteristics. T A25°C (see note 2 and fast programming cycle timing diagram)PARAMETER TEST CONDITIONS MIN TYP MAX UNITtdis(G)FP Output disable time from G (see Note 7) CL = 100 pF 0 130nsten(G)FP Output enable time from G 1 Series 74 TIL load 150m~:Ilos:cCD

TMS276465,536-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORYPARAMETER MEASUREMENT INFORMATIONv = 2.09 V. ~--.iRL' 7800UNO~~~:~~T CL = 100pFNOTE: tf ,; 20 ns and tr ,; 20 ns.FIGURE 2 -TYPICAL OUTPUT LOAD CIRCUITread cycle timingVIHADDRESSESVILEGVIHVILVIHVILXIIIIIXIYIY--tnQ)CJ-:;Q)c~0a:0..w01-08VOHVOLHIGH ZHIGH Z34TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752656-59

TMS276465,536·BIT ERASABLE PROGRAMMABLE READ·ONL Y MEMORYfast program cycle timing------j .... IIrl-----PROGRAM I---ADDRESSESADDRESS STABLEI-'-tSU(AI1 IQl_~~/VOH ___ -C{ DATi IN STABLE }-HI-ZVIL/VOLVPPVPPVee'-------------'1-.I-'-tSU (DI1IADDRESS N + 1VIH--------"""PGMtw(lPGMI HItfu(GI1.----.1 ten(GIF!tw(FPGMI ~ I I '

MOSLSITMS27128131,072·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORYOCTOBER 1983 - REVISED JANUARY 1984• 16,384 X 8 Organization• Single +S-V Power Supply• Pin Compatible with TMS2764 EPROM• All Inputs and Outputs Are TTL Compatible• Max Access/Min Cycle Time:TMS27128-25TMS27128-30TMS27128-45250 ns300 ns450 ns• Low Active Current- 100 rnA (Maximum)• JEDEC Approved Pinout• Fast Programming AlgorithmdescriptionThe TMS27128 is an ultraviolet light-erasable, electricallyprogrammable read-only memory. It has131,072 bits organized as 16,384 words of 8-bitlength. The TMS27128 only requires a single 5-voltpower supply. The TMS27128-25 provides an accesstime of 250 ns, which is compatible with high-speedmicroprocessors.TMS27128 .•• JL PACKAGE(TOP VIEW)AO-A 13EGGNDPGM01-08VeeVPPVPPA12A7A6A5A4A3A2AlveePGMA13A8A9AllGAl0EAO 0801 0702 0603 05GND 04PIN NOMENCLATUREAddressesehip Enable/Power DownOutput EnableGroundProgramOutputs+ 5-V Power Supply+21-V Power SupplyThe TMS27128 provides two output control lines: Output Enable (GI and Chip Enable/Power Down {EL This featureallows the G control line to eliminate bus contention in microprocessor systems. The TMS27128 has a standby modethat reduces the maximum power dissipation from 525 mW to 210 mW when the device is placed on standby.operationThis EPROM is supplied in a 28-pin dual-in-line ceramic package (JL suffix). It is pin compatible with the TMS2764EPROM and is designed for operation from OOC to 70°C.The six modes of operation for the TMs27128 are listed in the following table.FUNCTION(PINS)E(20)G(22)PGM(27)Vpp(1)Vee(28)01-08ReadMODEOutput Power Down Fast Program InhibitDisable (Standby) Programming Verification ProgrammingVIL X VIH VIL VIL VIHVIL VIH X VIH VIL XVIH VIH X VIL VIH XVeeVeeVee Vpp Vpp XVee Vee Vee Vee Vee Vee(11 to 13. 0 HI-Z HI-Z D 0 HI-Z15 to 19)(I)Q)CJ'>Q)Q:!oa:c.w4PRODUCT PREVIEWThis document contains Information on a product underdevelopment. Texas Instruments reserves the right tochange or discontinue this product without notice.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1983 by Texas Instruments Incorporated6-61

1MS27128131,072·811 ERASABLE PROGRAMMABLE READ·ONLY MEMORYreadThe dual control pins (E and G) must have low-level TIL signals in order to provide data at the outputs. ehip enable(E') should be used for device selection. Output enable (G) should be used to gate data to the output pins.power downThe'power-down mode reduces the maximum active curr~nt from 100' mA to 40 mAo A TTL high-level signal appliedto E selects the power-down mode. In this mode, the outputs assume a high-impedance state, independent of G.erasureBefore programming, the TMS27128 is erased by exposing the chip to shortwave ultraviolet light that has a wavelengthof 253.7 nanometers (2537 angstroms). The recommended minimum exposure dose (UV intensity x exposure time)is fifteen watt-seconds per square centimeter. A typical 12 mW/cm 2 UV lamp will erase the device in approximately20 minutes. The lamp should be located about 2.5 centimeters (1 inch) above the chip during erasure. After erasure,all bits are at a high level. It should be noted that normal ambient light contains the correct wavelength for erasure.Therefore, when using the TMS27128, the window should be covered with an opaque label.fast programmingNote that the application of a voltage in excess of 22 V to VPP may damage the TMS27128.After erasure, logic "O's" are programmed into the desired locations. Programming consists of the following sequenceof events. With the level on VPP equal to 21 V and E at TTL low, data to be programmed is applied in parallel tooutput pins 08-01. The location to be programmed is addressed. Once data and addresses are stable, a TTL low-levelpulse is applied to PGM. Programming pulses must be applied at each location that is to be programmed. Locationsmay be programmed in any order.m"'0:co3:cCD

TMS27128131,072·BI1 ERASABLE PROGRAMMABLE READ·ONLY MEMORYDEVICEFAILEDINCREMENTADDRESSDEVICEFAILEDFIGURE 1 -FAST PROGRAMMING FLOWCHARTen(1)(.).S;(1)c:?ioa:Q.w34TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752656-63

TMS27128131,072·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORYlogic symbol tAD (10)A1 (9)A2 (8)EPROM 16384 X 8oA3 (7)A4 (6)A5 (5)A6 (4)(3)A7-----4A8 (25)A9 (24)(21)A10-----1(23)A11-----1A 12 _(2_) __ --1(26)A13 13_ (20)E--.... - ...G (22)ENm."~os:c~< c:;.~entThis symbol is in accordance with IEEE Std 91/ANSI Y32.14 and recent decisions by IEEE and IEC. See explanation on page 10-1.absolute maximum ratings over operating free-air temperature range (unless otherwise noted)+Supply voltage, Vee ..................................................... . -0.6 V to 7 VSupply voltage, Vpp ..................................................... . -0.6 V to 22 VAll input voltage ......................................................... . -0.6 V to7 VOutput voltage .......................................................... . -0.6 V to 7 VOperating free-air temperature range ............................................ ooC to 70 0 CStorage temperature range ................................................ - 65°C to 150 0 C* Stresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functionaloperation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specificationis not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.recommended operating conditionsPARAMETERTMS27128MIN NOM MAXUNITSupply voltage, Vee 4.75 5 5.25 VSupply voltage, Vpp Vee VHigh-level input voltage, VIH 2 Vee+ 1 VLow-level input voltage, VIL (see Note 1) -0.1 0.8 VOperating free-air temperature, T A 0 70 °eNOTE 1:The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic voltage levels only.6-64 TEXASINSTRUMENlSPOST OFFICE BOX 225012 • DALLAS, TEXAS 7526518

TMS27128131,072·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORYelectrical characteristics over full ranges of .recommended operating conditionsPARAMETER TEST CONDITIONS MIN Typt MAX UNITVOH High-level output voltage 10H = -400/lA 2.4 VVOL Low-level output voltage 10L = 2.1 rnA 0.45 VII Input current (leakage) VI = 0 V to 5.25 V ±10 /lA10 Output current (leakage) Vo = 0.4 V to 5.25 V ±10 /lAIpP1 Vpp supply current (read) Vpp = 5.25 V 5 rnAIpP2 Vpp supply current (program) E and PGM at VIL 50 rnAICC1 VCC supply current (standby) Eat VIH 40 rnAICC2 VCC supply current (active) E and G at VIL 100 rnAt Typical values are at T A = 25°C and nominal voltages.capacitance over recommended supply voltage range and operating free-air temperature range, f1 MHzPARAMETER TEST CONDITIONS MIN Typt MAX UNITCi Input capacitance VI = 0 V 4 6 pFCo Output capacitance Vo = 0 V 8 12 pFt Typical values are at T A = 25°C and nominal voltages.switching characteristics over recommended supply voltage range and operating free-air temperature range,CL = 100 pF, 1 Series 74 TTL load (see note 2 and figure 2)PARAMETERTMS27128-25 TMS27128-30 TMS27128-45MIN MAX MIN MAX MIN MAXtalA) Access time from address 250 300 450 nstalE) Access time from E 250 300 450 nsten(G) Output enable time from G 100 120 150 nstdis(G)+ Output disable time from G 0 60 0 105 0 130 nstv(A)Output data valid time after change of address,0 0 0 nsE, or 13, whichever occurs firstNOTE 2: For switching characteristics and timing measurements, input timing reference levels are 0.8 V and 2 V; output timing reference levels are 0.8 Vand 2 V.* Value calculated from 0.5 volt delta to measured output level; tdis(G) is specified from G or r, whichever occurs first. Refer to read cycle timing diagram.recommended conditions for fast programming routine, TA = 25°C (see note 2 and fast programmingcycle timing diagram)UNITCI)Q)CJ.S;Q)c:2:oa:D.WPARAMETER MIN NOM MAX UNITVCC Supply voltage (see Note 3) 5.75 6 6.25 VVPP Supply voltage (see Note 4) 20.5 21 21.5 Vtw(lPGM) PGM initial program pulse duration (see Note 5) 0.95 1 1.05 mstwIFPGM) PGM final Dulse duration (see Note 6) 3.8 63 mstsu(A) Address setup time 2 /lstsu(D) Data setup time 2 ,.stsu(VPP) VPP setup time 2 ,.stsu(VCC) VCC setup time 2 ,.sth(A) Address hold time 0 ,.sth(D) Data hold time 2 ,.stsu(E) E setup time 2 p.stsu(G) G setup time 2 p.s14TEXASINsrRuMENlSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752656-65'

TMS27128131,072·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORYfast programming characteristics, T A25°C (see note 2 and fast programming cycle timing diagram)PARAMETER TEST CONDITIONS MIN Typt MAXtdis(GlFP Output disable time from G (see Note 7) CL = 100 pF o 130ten(G)FP Output enable time from G 1 Series 74 TTL load 150NOTES:2. For all switching characteristics and timing measurements, input timing reference levels are 0.8 V and 2 V; output timing reference levels are0.8 V and 2 V.3. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.4. When programming the TMS27128, connect a 0.1 I'F capacitor between Vpp and GND to suppress spurious voltage transients which maydamage the device.5. The Initial program pulse duration tolerance is 1 ms ± 5%.6. The length of the Final pulse will vary from 3.8 ms to 63 ms depending on the number of Initial pulse applications (X).7. This parameter is only sampled and is not 100% tested.PARAMETER MEASUREMENT INFORMATIONv = 2.09 VRL = 780 (}OUTPUT-1UNDER TEST·TCL = 100 pFNOTE: tf S 20 ns and tr S 20 ns.m"'0~0 read cycle timing3:CCD

TMS27128131,072·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORYfast program cycle timingADDRESSESVIH-rt------ PROGRAM ------1j .. I----~ tsu{Al --iADDRESS STABLE. IQ 1_~:iVOH ___ -(f""----D-A-T-~-I-N-S-T-A-BL-E----"j}- HI-ZVILiVOLVPPVPPVee\-,.,------------'1-.~ tsu{Dl --iIADDRESS N + 1PGMVIH--------....tw(lPGMl HtfU{Gl I '1.---.1 ten{GlF!tw{FPGMl ~ I IG ~:~---------~--~------....~IenQ)CJ':;Q)c:Eoa:Q.WTexas Instruments reserves the right to make changes at any time in order to improve design and to supply the best product possible.14TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752656-67

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Alphanumeric Index, Table of Contents, Selection GuideInterchangeability GuideGlossary/Timing Conventions/Data Sheet StructureDynamic RAM and Memory Support DevicesDynamic RAM Modules ..EPROM Devices ..ROM Devices ~Static RAM and Memory Support DevicesApplications Information ..Logic SymbolsMechanical Data

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MOSLSITMS46648192·WORD BY 8·BIT READ·ONLY MEMORYJUNE 1983 - REVISED OCTOBER 1983• 8192 X B Organization• Partitioned into Two 4K X 8 Banks• Fully Static (No Clocks, No Refresh)• All Inputs and Outputs TTL Compatible• Single 5·V Power Supply• Two Chip·Selects for Flexibility and PowerDown Option• Maximum Access Time from Address... 450 ns• Typical Active Power Dissipation... 275 mW• Available in Chip-on-Board Package AlsoTMS4664 .•. NL PACKAGE(TOP VIEW)A7 veeA6A8A5A4A3 51/51A2AlAO010203VssPIN NOMENCLATUREAO - AllAddresses01 - 08Data Out51/51,52/52VccVSSChip Selects+5-V SupplyGrounddescriptionthe TMS4664 is a 65,536-bit read-only memory organized as 8192 words of 8-bit length. The array is partitionedinto two 4096-words of 8-bit length banks. This makes the TMS4664 ideal for microprocessor based systems. Thedevice is fabricated using N-channel silicon-gate technology for high speed and simple interface with bipolar circuits.All inputs can be driven directly by Series 74 TTL circuits without the use of any external pull-up resistor. Each outputcan drive two Series 74 or 74S loads without external resistors. The data outputs are three-state for OR-tieing multipledevices on a common bus. Two chip-select controls allow data to be read. These controls are programmable, providingadditional system decode flexibility. The data is always available, it is not dependent on external clocking ofthe control pins.enQ)(J'S;Q)C~oa:The TMS4664 is designed for high-density fixed-memory consumer applications.This ROM is supplied in a 24-pin dual-in-line plastic (NL suffix) package designed for insertion in mounting-hole rowson 600-mil centers. It is also available in the chip-an-board package. The device is designed for operation from OOCto 70°C.operationaddress (AO-A 11)The address-valid interval determines the device cycle time. The 12-bit positive-logic address is decoded on-chip toselect one of 8192 words of 8-bit length in the memory array. AO is the least-significant bit and A 11 the most-significantbit of the word address. Additionally each bank of the array is activated by a particular address. Address FF8 willallow entry and access to the low order bank and FF9 will allow entry and access to the high order bank. After aset of A 12 (FF9 or FF8), a normal read cycle must be completed before another set is performed.All address changes must be made within 30 ns of when the first address changes to prevent address skewing.chip select/output enable (pins 20 and 21)Each of these pins can be programmed during mask fabrication to be active with either a high or a low level input.When both signals are active, all eight outputs are enabled and the eight-bit addressed word can be read. When eithersignal is not active, all eight outputs are in a high-impedance state.84ADVANCE INFORMATION. ThIa document contaIna information an a new product.Specifications are subject to change without notice.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265Copyright © 1983 by Texas Instruments Incorporated7-1

TMS46648192·WORD BY 8·BIT READ·ONLY MEMORYdata out (Q1-Q8)The eight outputs must be enabled by both pins 20 and 21 before the output word can be read. Data will remainvalid until the address is changed or the outputs are disabled (chip deselected). When disabled, the three-state outputsare in a high-impedance state. Q1 is considered the least-significant bit, Q8 the most-significant.The outputs will drive two Series 54/74 TTL circuits without external components.functional block diagramDA T A OUTPUTSQ1-0S-VCC-vss51/51 --... -r---:C:-H='P-S:':E::-L=-EC=T::-LO-G='-C---'52/52 t--"'-tOUTPUT BUFFERSY DECODEY GATING:Do3:cCD

TMS46648192·WORD BY 8·BIT READ·ONL Y MEMORYelectrical characteristics, T A5 V ± 10% (unless otherwise noted)PARAMETER TEST CONDITIONS MIN MAX UNITVOH High-level output voltage Vce=4.5 V, IOH= -400 p.A 2.4 VVOL Low-level output voltage Vee-4.5 V, IOL-3.2 mA 0.4 VII Input current Vee=5.5 V, OVSVINS5.5 V 10 p.A10 Output leakage current VO=0.4 V to Vee, Chip deselected ±10 p.AleCl Supply current from Vee (active) Vee=5.5 V, VI=Vec output not loaded 80 mAei Input capacitanceVO-O V, TA-25 o e.f= 1 MHz6 pFCo Output capacitanceVO=O v.f=l MHzTA=25 o e.12 pFswitching characteristics, T A 5 V ± 10%, 2 series 74 TTL loads, CL 100 pFtPARAMETER MIN MAX UNITtalA) Access time from address 1: 450 nsta(S) Access time from chip select+ 200 nstv(A) Output data valid after address change 20 nstdis Output disable time from chip select 150 nstAli AC measurements are made at 10% and 90% points* Access time from page select is double normal access time.NOTE 1: All address changes must be made within 30 ns of when the first address changes to prevent address skewing.read cycle timingAO-AllEtS01-08I:::~----.................... --------..... --..... ------..... --..... ~~~--------------..J l.-I I tv(A) I I--~:-~\i_ I I I:I ~I ______________________________"""'~:-J: I-----~ t'IAI ¢1---' ~ tdisI ---t ta(S) ~ I IVAL'DIIW-enQ)(.)'SQ)c~oa:PROGRAMMING DATAPROGRAMMING REQUIREMENTS: The TMS4664 NL is a fixed program memory in which the programming is performedby TI at the factory during the manufacturing cycle to the specific customer inputs supplied in the format below. The deviceis organized as 8192 8-bit words with address locations numbered 0 to 8191. The 8-bit words can be coded as a 2-digithexadecimal number between 00 and FF. All data words and addresses in the following format are coded in hexadecimalnumbers. In coding all binary words must be in positive logic before conversion to hexadecimal. Q1 is considered the leastsignificant bit and Q8 the most significant bit. For addresses. AO is least significant bit and A 11 is the most significant.The input media containing the programming data can be in the form of cards or EPROMs.Either 16K, 32K, or 64K EPROMs ·can be used or any combination of them.The following is a description of how the cards must be formatted, should they be used instead of EPROMs.84TEXASINSTRUMENTSPOST OFFICE BOX 225012 • OALLAS. TEXAS 752657-3

TMS46648192·WORD BY 8·BIT READ·ONLY MEMORYINPUT CARD FORMATEach code deck submitted by customer shall consist of the following:1 . Title Card2. Comment Cards3. Start of Data Card4. Data CardsThe cards shall be standard 80 column cards with the information in the following format:TITLE CARD:0os:cCD

TMS46648192·WORD BY 8·BIT READ·ONLY MEMORYCOMMENT CARDSAny number of comment cards may be used for specifying the customer's name, individual to contact, telephone number,address, any special instructions, etc. The format for these cards is as follows: The Letter 'C' (for comment) must be pun·ched in column 1, columns 2 - 4 must be blank, and comments can be punched in columns 5 - 80.START OF DATA CARDThis card is to identify that the next card will be the beginning of customer's code. Format is as follows: Columns 1 -4must have '&ROM' punched in them. The remainder of card is blank.DATA CARDSThere will be 256 data cards supplied for each customer code. Each card will contain (in hexadecimal) the data for 32 memorylocations. Each data card shall be in the following format:Card Column1 - 45,67 - 7071, 7273 - 7680InformationHexadecimal address of first word on the card, four bits in length.Blank.Data. Each 8-bit data byte is represented by two ASCII characters to represent ahexadecimal value of '00' to 'FF'.Checksum. The checksum is the negative of the sum of all 8-bit bytes in the recordfrom columns 1 to 70, evaluate modulo 256 (carry from high order bit ignored). Forpurposes of calculating the checksum, the value of columns 5 and 6 are d~fined tobe zero. Adding together, modulo 256, all 8-bit bytes from columns 1 to 70 (columns5 and 6 = 0), then adding the checksum, results in zero.Blank.Card sequence number, in decimal.(right justified).rnQ)(,)'S:Q)c~oa:Texas Instruments reserves the right to make changes at any time in order to improve design and to supply. the best product possible.94TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752657-5

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MOSLSITMS47324096~WORD BY B·BIT READ·ONLY MEMORYMAY 1977 - REVISED JULY 1983• 4096 X 8 Organization• All Inputs and Outputs TTL Compatible• Fully Static (No Clocks, No Refresh)• Single 5·V Power Supply• Maximum Access Time From Address:oTMS4732-30TMS4732-35TMS4732-45300 ns350 ns450 nsTypical Power Dissipation ... 275 mW• 3-State Outputs for OR-Ties• Pin-Compatible with TMS2532 EPROM• Two Output Enable Controls for Chip SelectFlexibilityTMS4732 ••• JL OR NL PACKAGE(TOP VIEW)A7VCCA6A8A5A9A4 52/52A3 51/51A2Al0AlAllAO 0801 0702 0603 05V55AO - All01 - 08S1/S1, S2/52VccVS5PIN NOMENCLATUREAddressesData OutChip Selects+5-V SupplyGrounddescriptionThe TMS4732 is a 32,768-bit read-only memory organized as 4096 words of 8-bit length. This makes the TMS4732ideal for microprocessor based systems. The device is fabricated using N-channel silicon-gate technology for highspeed and simple interface with bipolar circuits.All inputs can be driven directly by Series 74 TTL circuits without the use of any internal pull-up resistor. Each outputcan drive one Series 74 or 74Sload without external resistors. The data outputs are three-state for OR-tieing multipledevices on a common bus. Two chip-select controls allow data to be read. These controls are programmable, providingadditional system decode flexibility. The data is always available, it is not dependent on external clocking ofthe control pins.operationThe TMS4732 is designed for high-density fixed-memory applications such as logic function generation andmicroprogramming. The part is pin compatible with the TMS2532 4096 x 8 EPROM, which aids in prototyping andcode verification.This ROM is supplied in 24-pin dual-in-line-plastic (NL suffix) or ceramic (JL suffix) packages designed for insertionin mounting-hole rows on 600-mil centers or chip on board. The device is designed for operation from OOC to 70°C.address (AO - A 11)The address-valid interval determines the device cycle time. The 12-bit positive-logic address is decoded on-chip toselect one of 4096 words of 8-bit length in the memory array. AO is the least-significant bit and A 11 the most-significantbit of the word address.chip select/output enable (pins 20 and 21)Each of these pins can be programmed during mask fabrication to be active with either a high- or a low-level input.When both signals are active, all eight outputs are enabled and the eight-bit addressed word can be read. When eithersignal is not active, all eight outputs are in a high-impedance state.TEMS .INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265Copyright © 1983 by Texas Instruments Incorporated7-7

TMS473240aS-WORD BY 8-BIT READ-ONLY MEMORYdata out (01 - aS)The eight outputs must be enabled by pins 20 and 21 before the output word can be read. Data will remain validuntil the address is changed or the outputs are disabled (chip deselected). When disabled, the three-'state outputsare in a high-impedance state. 01 is considered the least-significant bit, 08 the most-significant bit.The outputs will drive two Series 54/74 TTL circuits with()ut external components.logic symbol t:D0~Cm

TMS47324096·WORD BY 8·BIT READ·ONLY MEMORYfunctional block diagram~VCC.--VssOAT A OUTPUTS01-08S152---....._"CHIP SElECT LOGICOUTPUT BUFFERSY GATING4096 X 8 MEMORY MATRIXabsolute maximum ratingsSupply voltage to ground potential (see Note 1) .................................... - 0.5 V to 7 VApplied output voltage (see Note 1) ............................................. -0.5 V to 7 VApplied input voltage (see Note 1) .............................................. - 0.5 V to 7 VPower dissipation. . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 500 mWOperating free-air temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O°C to 70°CStorage temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55 DC to 150 DCC/)Q)(,)'S;Q)o~oa:NOTE 1: Voltage values are with respect to vss.recommended operating conditionsPARAMETER MIN NOM MAX UNITSupply voltage, Vee 4.5 5 5.5 VHigh-level input voltage, VIH 2 2.4 Vee+ 1 VLow-level input voltage, VIL -0.5 0.8 VOperating free-air temperature, T A 0 70 °eTEXASIN srRUMENlSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752657-9

·TMS47324096-WORD BY 8-BiT READ-ONLY MEMORYelectrical characteristics, T A o °e to 70 o e, Vee 5 V ± 10% (unless otherwise noted)PARAMETER TEST CONDITIONS MIN MAXVOH High-level output voltage VCC=4.5 V, 10H= -400 /LA 2.4VOL Low-level output voltage VCC=4.5 V, IOL=3.2 mA 0.4II . Input current VCC=5.5 V, OV:5VIN:55.5 V 1010 Output leakage current Vo =0.4 V to Vcc, Chip deselected ±10ICCl Supply current from VCC (active) VCC=5.5 V, VI=VCC output not loaded 80Ci Input capacitanceVO=O V,TA=25°C,f=l MHz6Co Output capacitanceVO=O V,TA =25°C,f=l MHz12UNITVV/LA/LAmApFpFswitching characteristics, TA=Ooe to 70 o e, Vee=5 V ±10%, 2 series 74 TTL loads, eL=100 pFtPARAMETERTMS4732-30 TMS4732-35 TMS4732-45MIN MAX MIN MAX MIN MAXtalA) Access time from address 300 350 450tarS) Access time from chip select 120 120 120tv(A) Output data valid after address change 20 20 20tdis Output disable time from chip select 100 100 100UNITnsnsnsns::co3:c.CD

TMS47324096·WORD BY 8·BIT READ·ONLY MEMORYPROGRAMMING DATAPROGRAMMING REQUIREMENTS: The TMS4732 is a fixed program memory in which the programming is performed byTI at the factory during the manufacturing cycle to the specific customer inputs supplied in the format below. The deviceis organized as 4096 8-bit words with address locations numbered 0 to 4095. The 8-bit words can be coded as a 2-digithexadecimal number between 00 and FF. All data words and addresses in the following format are coded in hexadecimalnumbers. In coding, all binary words must be in positive logic before conversion to hexadecimal. Q1 is considered the leastsignificant bit and Q8 the most significant bit. For addresses, AO is the least significant bit and A 11 is the most significant.The input media containing the programming data can be in the form of cards or EPROMs.Either 16K, 32K, or 64K EPROMs can be used, or any combination of them.The following is a description of how the cards must be formatted, should they be used instead of EPROMS.INPUT CARD FORMATEach code deck submitted by customer shall consist of the following:1. Title Card2. Comment Cards3. Start of Data Card4. Data CardsThe cards shall be standard 80 column cards with the information in the following format:Card Column567, 89 - 141516 - 30313233 - 363738 - 40TITLE CARDInformationThe word 'TITLE' shall be punched in these columns.BlankThe letters 'ZA' shall be punched in these columns.Leave blank. A special device code number will be assigned by Texas Instruments.(left justified)BlankCustomer's Part Number, if required. (left justified)BlankCustomer's Part Number to be included as part of device symbolization.Options:Y = YesN = NoBlankType of PackageOptions:C = ceramicP = plasticB = chip on boardBlankt/)Q)(.)os:Q)C~oa:TEXASINSTRUMENlSPOST OFFICE BOX 225012 • OALLAS. TEXAS 752657-11

TMS47324096·WORD BY B·BIT READ·ONLY MEMORY4142434445 - 49Logic Level for device pin 20.Options:1 = chip-select mode outputs enabled with high level.o = chip-select mode, outputs enabled with low level.Logic Level for device pin 21Options:1 = chip-select mode outputs enabled with high level.o = chip-select mode, 'outputs enabled with low level.BlankBlankTexas Instruments Device Series (4732B, 4732C, etc.)(left justified)COMMENT CARDS:aos:cCD

MOSLSITMS47648192·WORD BY 8·BIT READ·ONLY MEMORYJUNE 1981 - REVISED JULY 1983• 8192 X 8 Organization• Fully Static (No Clocks, No Refresh)• All Inputs and Outputs TTL Compatible• Single 5-V Power Supply• Maximum Access Time From Address:TMS4764-30TMS4764-35TMS4764-45300 ns350 ns450 ns• Typical Active Power Dissipation... 275 mWTMS4764 ••. JL OR NL PACKAGE(TOP VIEWIA5A4A3Vss .......... _~:.r--VCCA8descriptionPIN NOMENCLATUREAO - A12 Addresses01 - 08 Data OutSISChip SelectVCC+5-V SupplyVSSGroundThe TMS4764 is a 65,536-bit read-only memory organized as 8192 words of 8-bit length. This makes the TMS4764ideal for microprocessor based systems. The device is fabricated using N-channel silicon-gate technology for highspeed and simple interface with bipolar circuits.enQ)(JoS;Q)c:?!oa:All inputs can be driven directly by Series 74 TTL circuits without the use of any internal pull-up resistor. Each outputcan drive two Series 74 or 74S loads without 'external resistors. The data outputs are three-state for OR-tieing multipledevices on a common bus. Pin 20 is programmable, providing additional system flexibility. The data is alwaysavailable, it is not dependent on external clocking of pin 20.The TMS4764 is designed for high-density fixed-memory applications such as logic function generation andmicroprogramming. It is pin compatible with TI's full line of ROMs and EPROMs.This ROM is supplied in 24-pin dual-in-line-plastic (NL suffix) or ceramic (JL suffix) packages designed for insertionin mounting-hole rows on 600-mil centers or chip on board. The device is designed for operation from OOC to 70°C.operationaddress (AO - A 12)The address-valid interval determines the device cycle time. The 13·bit positive-logic address is decoded on-chip toselect one of 8192 words of 8-bit length in the memory array. AD is the least-significant bit and A 12 the most-significantbit of the word address.chip select (S or 51Pin 20 can be programmed during mask fabrication to be active with either a high- or a low-level input. When thesignal is active, all eight outputs are enabled and the eight-bit addressed word can be read. When the signal is notactive, all eight outputs are in a high-impedance state.'TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265'Copyright © 1983 by Texas Instruments Incorporated7-13

TMS47648192·WORD BY 8·BIT READ·ONLY MEMORYdata out (a1 -a8)The eight outputs must be enabled by pin 20 before the output word can be read. Data will remain valid until theaddress is changed or the outputs are disabled (chip deselected). When disabled, the three-state outputs are in a highimpedancestate. 01 is considered the least-significant bit, 08 the most-significant bit.The outputs will drive two Series 54/74 TTL circuits without external components.logic symbol t~0s:CCDc:5'CDenIIAOA1ROM8192x8A2 (9)A3A4ASA6 (14)A7A10A11A12S5 ~L.E_N __:J_.......a1a20304a50607a8Pin 20 can be active-high as shown in the upper symbol or active-low asshown in the lower (partial) symbol.tThis symbol is in accordance with IEEE Std 91/ANSI Y32.14 and recent decisions by IEEE and lEe. See explanation on page 10-1.7-14 TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

TMS47648192·WORD BY 8·BIT READ·ONLY MEMORYfunctional block diagram.-Vcc+-VSSDATA OUTPUTS01-08SISCHIP SELECT LOGICOUTPUT BUFFERSY DECODEY GATINGX DECODE8192 X 8 MEMORY MATRIXabsolute maximum ratingsSupply voltage to ground potential (see Note 1) .................................... - 0.5 V to 7 VApplied output voltage (see Note 1) ............................................. - 0.5 V to 7 VApplied input voltage (see Note 1) .............................................. - 0.5 V to 7 VPower dissipation ..................................................... : . . . . . . . . .. 500 mWOperating free-air temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OOC to 70°CStorage temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 150°CenQ)(,)'S;Q)C~oa:NOTE 1: Voltage values are with respect to Vss.recommended operating conditionsPARAMETER MIN NOM MAX UNITSupply voltage, Vee 4.5 5 5.5 VHigh-level input voltage, VIH 2 Vce+ 1 VLow-level input voltage, VIL -0.5 0.8 VOperating free-air temperature, T A 0 70 °eTEXASINsrRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752657-15

TMS47648192·WORD BY 8·BIT READ·ONLY MEMORYelectrical characteristics, T A ooe to 70 D e, Vee 5 V ± 10% (unless otherwise noted)PARAMETER TEST CONDITIONS MIN MAX UNITVOH High-level output voltage VCC=4.5 V, 10H= -400 itA 2.4 VVOL Low-level output voltage VCC=4.5 V, IQL=3.2 mA 0.4 V'IInput current VCC=5.5 V, OVSVIN=55.5 V 10 flA10 Output leakage current Vo =0.4 V to VCC, Chip deselected ±10 flAICCl Supply current from VCC (active) VCC=5.5 V, VI =VCC output not loaded 80 mACi Input capacitanceVO=O V,TA=25°C,f= 1 MHz6 pFCoOutput capacitanceVO=O V,f=l MHzTA=25°C,switching characteristics, TA=Ooe to 70 o e, Vee=5 V ±10%, 2 series 74 TTL loads, eL=100 pFtPARAMETERTMS4764-30 TMS4764-35 TMS4764-45MIN MAX MIN MAX MIN MAX12 pFtalA) Access time from address 300 350 450 nsta(S) Access time from chip select 120 120 120 nstv(A) Output data valid after address change 20 20 20 nstdis Output disable time from chip select 100 100 100 nsUNITtAli AC measurements are made at 10% and 90% points.tV(A)--Iread cycle timing:::-------------------""IxII....------AO-A12I10-I\1_ I : I:~------------------------~:~ : III --I ,..- tdisI ---f ta(S) r-- I I IQ1-Q8::: _____ ~ t.IAI ~ VALtD __I7-16 TEXASINsrRUMENlSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

TMS47648192·WORD BY 8·BIT READ·ONLY MEMORYPROGRAMMING DATAPROGRAMMING REQUIREMENTS: The TMS4764 is a fixed program memory in which the programming is performed byTI at the factory during the manufacturing cycle to the specific customer inputs supplied in the format below. The deviceis organized as 8192 8-bit words with address locations numbered 0 to 8191. The 8-bit words can be coded as a 2-digithexadecimal number between 00 and FF. All data words and addresses in the following format are coded in hexadecimalnumbers. In coding, all binary words must be in positive logic before conversion to hexadecimal. Q1 is considered the leastsignificant bit and Q8 the most significant bit. For addresses, AO is least significant bit and A 12 is the most significant.The input media containing the programming data can be in the form of cards or EPROMs.Either 16K, 32K, or 64K EPROMs can be used, or any combination of them.The following is a description of how the cards must be formatted, should they be used instead of EPROMS.PROGRAMMING INSTRUCTIONS -64K ROMEach code deck submitted by customer shall consist of the following:1. Title Card2. Comment Cards3. Start of Data Card4. Data CardsThe cards shall be standard 80 column cards with the information in the following format:Card Column1 - 567,89 - 1415TITLE CARDInformationThe word 'TITLE' shall be punched in these columns.BlankThe letters 'ZA' shall be punched in these columns.Leave blank. A special device code number will be assigned by Texas Instruments.(left justified)Blankt/)Q)CJ.S;Q)C~oa:16 - 30313233 - 363738 - 40Customer's Part Number, if required. (left justified)BlankCustomer's Part Number to be included as part of device symbolization.Options:Y = YesN = NoBlankType of PackageOptions:C = ceramicP = plasticB = chip on boardBlankTEXASINSTRUMENTSPOST OFFICE BOX 225012 • OALLAS, TEXAS 752657-17

TMS47648192·WORD BY 8·BIT READ·ONLY MEMORY4142 - 4445 - 49Logic Level for pin 20 on 24-pin package.Options:1oBlankchip-select mode outputs enabled with high level.chip-select mode, outputs enabled with low level.Texas Instruments Device Series (ie. 4764B, 4764C, etc.)(left justified)COMMENT CARDSAny number of comment cards may be used for specifying the customer's name, individual to contact, telephone number,address, any special instructions, etc. The format for these cards is as follows: The letter 'C' (for comment) must be punchedin column 1, columns 2-4 must be blank, and comments can be punched in columns 5-80.START OF DATA CARDThis card is to identify that the next card will be in the beginning of customer's code. Format is as follows: Columns 1-4must have '&ROM' punched in them. The remainder of card is blank.::rJos:cCD

MOSLSI, TMS49648192·WORD BY 8·BIT READ·ONLY MEMORYJUNE 1983 - REVISED OCT08ER 1983• 8192 X 8 Organization• Partitioned into Eight 1 K X 8 Pages• Fully Static (No Clocks, No Refresh)• All Inputs and Outputs TTL Compatible• Single 5·V Power Supply• Two Chip-Selects for Flexibility and PowerDown Option• Maximum Access Time from Address... 450 ns• Typical Active Power Dissipation... 275 mW• Available in Chip-on-Board Package AlsodescriptionTMS4964 ... NL PACKAGE(TOP VIEW)A7A6A5VeeA8A9A4 52/S2A3 51/S1A2AlAl0AllAO 0801 Q702 0603 05VSS 04PIN NOMENCLATUREAO - All Addresses01 - 08 Data Out51/S1,52/S2VeeVSSehip Selects+5-V SupplyGroundThe TMS4964 is a 65,536-bit read-only memory organized as 8192 words of 8-bit length. The array is subdividedinto eight 1024 bits x 8 pages. The device is fabricated using N-channel silicon-gate technology for high speed andsimple interface with bipolar circuits.All inputs can be driven directly by Series 74 TTL circuits without the use of any external pull-up resistor. Each outputcan drive two Series 74 or 74S loads without external resistors. The data outputs are three-state for OR-tieing multipledevices on a common bus. Two chip-select controls allow data to be read. These controls are programmable, providingadditional system decode flexibility. The data is always available, it is not dependent on external clocking ofthe control pins.rnQ)(J':;Q)c::?ioa:The TMS4964 is designed for high-density fixed-memory consumer applications.This ROM is supplied in a 24-pin dual-in-line plastic (NL suffix) package designed for insertion in mounting-hole rowson 600-mil centers. It is also available in the chip-on-board package. The device is designed for operation from ooeto 70 o e.operationaddress (AO-A 11 )The address-valid interval determines the device cycle time. The 12-bit positive-logic address is decoded on-chip toselect one of 8192 words of 8-bit length in the memory array. AO is the least-significant bit and A 11 the most-significantbit of the word address. Additionally 24 addresses can generate traps which allow the selection of any 3 of 7 pagesto be active at any point in time. The 8th page is always active. After a write to a pointer register, a normal readcycle must be completed before another write is performed. A normal read is an address outside of the range FEO to FE7.All address changes must be made within 30 ns of when the first address changes to prevent address skewing.chip select/output enable (pins 20 and 21)Each of these pins can be programmed during mask fabrication to be active with either a high or low level input. Whenboth signals are active, all eight outputs are enabled and the eight-bit addressed word can be read. When either signalis not active, all eight outputs are in a high-impedance state.ADVANCE INFORMATIONThis document contains information on 8 new product.Specifications are subject to change without notice.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265Copyright © 1983 by Texas Instruments Incorporated7-19

TMS49648192·WORD BY 8·BIT READ·ONLY MEMORYdata out (Q1-Q8)The eight outputs must be enabled by both pins 20 and 21 before the output word can be read. Data will remainvalid until the address is changed or the outputs are disabled (chip deselected). When disabled, the three-state outputsare in a high-impedance state. 01 is considered the least-significant bit, 08 the most-significant bit.The outputs will drive two Series 54/74 TTL circuits without external components.page operationThe ROM is organized into 8K x 8-bit bytes. Only 12 address bits or a maximum of 4K bytes may be accessed atone time. The 4K address space is segmented into four 1 K banks and memory is partitioned into eight 1 K pages.Bank 3 containing page 7 is always resident. Any three of the eight pages, 0 thru 7, are immediately accessable.The banks, which are defined by page pointers, are selected by address bits A3 and A4 (see Table 1).TABLE 1A4 A3 BANK ADDRESS RANGEL L 0 000 - 3FFL H 1 400 - 7FFH L 2 BOO - BFFResident 3 COO - FDF:llo3:oCD

TMS49648192·WORD BY 8·BIT READ·ONLY MEMORYWhen an address outside the range FEO to FF7 is accessed, address bits A 11 and A 10 select pointer 0, 1 or 2 andthe pointer content is mapped to the internal address bits A 12, A 11 and A 10. When A 10 and A 11 are both high,page 7 is selected (see Table 4). Internal address bits A9 thru AO are the same as the external address bits A9 thru AO.TABLE 4A11 A10 SELECTEDL L Pointer 0L H Pointer 1H L Pointer 2H H Page 7H = high level, L = low levelAs an example, suppose it is desired to select the third 1 K ROM page by addresses 400 thru 7FF. This address spaceis represented by pointer 1 because of the condition of A 11 and A 10. To write to pointer 1; bits A4, A3 = LH. Thecontents of the pointer is 3; bits A2, A 1, AO = LHH. Therefore, location FEB is accessed.functional block diagram51/S1 ---II>--r-------------,52/52 CHIP SELECT LOGIC t--.... -tDATA OUTPUTS01-08OUTPUT BUFFERS-Vcc-VSSU)Q)(.)'S;Q)C~oa:Y GATING8192 X 8 MEMORY MATRIXPAGEPAGESELECTLOGICFEO to FF7TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752657-21

TMS49648192·WORD BY 8·BIT READ·ONLY MEMORYabsolute maximum ratingsSupply voltage to ground potential (see Note 1) .................................... - 0.5 V to 7 VApplied output voltage (see Note 1) ............................................. - 0.5 V to 7 VApplied input voltage (see Note 1) .............................................. - 0.5 V to 7 VPower dissipation ......................................................... .' . . . . .. 500 mWOperating free-air temperature ....................................... ' ........... , O°C to 70°CStorage temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .. - 55°C to 150°CNote 1: Voltage values are with respect to VSSrecommended operating conditionsPARAMETER MIN NOM MAX UNITSupply voltage, Vee 4.5 5 5.5 VHigh-level input voltage, VIH 2 Vee+ 1 VLow-level input voltage, VIL -0.5 0.8 VOperating free-air temperature, T A 0 70 °e:0o3:caI

TMS49648192·WORD BY 8·BIT READ·ONLY MEMORYread cycle timingIIAO-A1101-08:::~------------------------------------~~~-------------I tV(A)--.J I.-- 1IIEli; ---~:--\I. I : I:I ~I ____________________________________________ ~I-J I::: _____ =-II -.I ,.-- tdisI --f ta(S) r-- I I'.(A, ¢ VALID •IPROGRAMMING DATAPROGRAMMING REQUIREMENTS: The TMS4964NL is a fixed program memory in which the programming is performedby TI at the factory during the manufacturing cycle to the specific customer inputs supplied in the format below. The deviceis organized as 8192 8-bit words with address locations numbered 0 to 8191. The 8-bit words can be coded as a 2-digithexadecimal number between 00 and FF. All data words and addresses in the following format are coded in hexadecimalnumbers. In coding all binary words must be in positive logic before conversion to hexadecimal. Q1 is considered the least·significant bit and Q8 the most signific~nt bit. For addresses, AO is least significant bit and A 11 is the most significant.The input media containing the programming data can be in the form of cards or EPROMs.(I)Q)CJ'S;Q)c:?!oc:Either 16K, 32K, or 64K EPROMs can be used or any combination of them.The following is a description of how the cards must be formatted, should they be used instead of EPROMs.INPUT CARD FORMATEach code deck submitted by customer shall consist of the following:1. Title Card2. Comment Cards3. Start of Data Card4. Data CardsThe cards shall be standard 80 column cards with the information in the following format:TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752657-23

TMS49648192·WORD BY 8·BIT READ·ONLY MEMORYTITLE CARD-~os:cCD

TMS49648192·WORD BY 8·BIT READ·ONLY MEMORYCOMMENT CARDSAny number of comment cards may be used for specifying the customer's name, individual to contact, telephone number,address, any special instructions, etc. The format for these cards is as follows: The letter 'c' (for comment) must be punchedin column 1, columns 2-4 must be blank, and comments can be punched in columns 5-80.START OF DATA CARDThis card is to identify that the next card will be the beginning of customer's code. Format is as follows: Columns 1-4 musthave '&ROM' punched in them. The remainder of card is blank.DATA CARDSThere will be 256 data cards supplied for each customer code. Each card will contain (in hexadecimal) the data for 32 memorylocations. Each data card shall be in the following format:Card Column1-45,67-7071,7273-7677-80InformationHexadecimal address of first word on the card, four bits in length.Blank.Data. Each 8-bit data byte is represented by two ASCII characters to represent ahexadecimal value of '00' to 'FF'.Checksum. The checksum is the negative of the sum of all a-bit bytes in the recordfrom columns 1 to 70, evaluate modulo 256 (carry from high order bit ignored). Forpurposes of calculating the checksum, the value of columns 5 and-6 are defined tobe zero. Adding together, modulo 256, all a-bit bytes from columns 1 to 70 (columns5 and 6 = 0), then adding the checksum, results in zero.Blank.Card sequence number, in decimal.(right justified).en(1)CJ'S;(1)C~oa:Texas Instruments reserves the right to make changes at any tima in order to improve design and to supply the best product possible.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • OALLAS, TEXAS 752657-25

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MOSLSITMS4712816,384·WORD BY 8·BIT READ·ONLY MEMORYJUNE 1983• 16,384 X 8 Organization• Fully Static (No Clocks, No Refresh)• All Inputs and Outputs TTL Compatible• Single 5-V Power Supply• Optional Power Down or Chip Select• 64K Bank Select Option• Maximum Access Time from Address orPower Down:TMS47128-25TMS47128-35TMS47128-45250 ns350 ns450 ns• Worst Case Active Power Dissipation... 330 mW• Worst Case Standby Power Dissipation... 66mWTMS47128 " .. JL OR NL PACKAGEtSTANDARD ROMITOPVIEW)NCVCCA12 52/52A7A13A6ASA5A9A4A11A3 51/51A2A10A1E/E/S3/s3AOQSQ1Q7Q2Q6Q3Q5VssQ4t The package for the bank select ROM is shown on page 2.descriptionThe TMS47128 is a 131 ,072-bit read-only memoryorganized as 16,384 words of 8-bit length. This makesthe TMS47128 ideal for microprocessor basedsystems. The device is fabricated using N-channelsilicon-gate technology for high speed and simple interfacewith bipolar circuits.There are two versions of the TMS47128: the standardROM with options on chip selects and powerdown, and the bank select ROM with similar options.The operation section of this data sheet describes bothversions.PIN NOMENCLATURESTANDARD ROMAO-A13 AddressesE/E/S3/s3 Chip Enable/Power Down or Chip SelectNCNo ConnectionQ1-QS Data Out51/51,52/52 Chip SelectsVCC+5-V SupplyVssGroundThe TMS47128 is fully compatible with Series 74, 74S, or 74LS TTL. The data outputs are three-state for OR-tieingmultiple devices on a common bus. Pins 20, 22, and 27 are mask-programmable, providing additional system flexibility.The data is always available, it is not dependent on external clocking of pins 20, 22, or 27.The TMS47128 is designed for high-density fixed-memory applications such as logic function generation andmicroprogramming. It is pin compatible with Tl's full line of ROMs and EPROMs.This ROM is supplied in 28-pin dual-in-line plastic (NL suffix) or ceramic (JL suffix) packages designed for insertionin mounting-hole rows on 600 mil centers. The device is designed for operation from ooe to 70 0 e.U)Q)t)'S;Q)C~0a:operation, standard ROMaddress (AO-A 13)The address-valid interval determines the device cycle time. The 14-bit positive-logic address is decoded on-chip toselect one of 16,384 words of 8-bit length in the memory array. AO is the least-significant bit and A 13 the mostsignificantbit of the word address.chip select (S1 or S1 and S2 or S2)Pins 22 and 27 can be programmed during mask fabrication to be active with either a high- or a low-level input. WhenPRODUCT PREVIEWThis document contains Information on I product underdevelopment. Texas Instruments re ••.ves the right tochange or discontinue thi' product without notice.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1983 by Texas Instruments Incorporated1'-27

TMS4712816,384-WORD BY 8-BIT READ-ONLY MEMORYthe signals on pins 20, 22, and 27 are active, all eight outputs are enabled; and the eight-bit addressed word canbe read. When any of the signals on pins 20, 22, and 27 are not active, all eight outputs are in a high-impedance state.power down (E orE) or chip select (S3 or 83)Pin 20 can be programmed during mask fabrication to be a chip-enable/power-down pin (E or E) or a third chip-selectpin (S3 or 53). Each option can be active-high or active-low. When the chip-enable/power-down pin is inactive, thechip is put into the standby mode. This reduces ICC1, which in the active state is 60 mA, to a standby ICC2 of 12mAo With the chip-select option, pin 20 is functionally identical to pins 22 and 27.data out (01-08)The eight outputs must be enabled by pins 20, 22, and 27 before the output word can be read. Data will remain validuntil the address is changed or the outputs are disabled (chip deselected). When disabled, the three-state outputsare in a high-impedance state. 01 is considered the least-significant bit, 08 the most-significant bit.•::0os:cCD

TMS4712816,384·WORD BY 8·BIT READ·ONLY MEMORYlogic symbols tSTANDARD ROMSROM0 .... 16.384 X 8(10)AO(9)A1(8)A2(7)A3(6)A4(5)A5(4)A6(3)A7(25)A8(24)A9(21)A10(23)A11(2)A12(26)A1313..-(20)E[PWR OWN]k:. ~(22) .......51EN(27) r......S2A\jA\jA\j0 A\j~ A 16.383A\jA\jA\jA\j(11 )(12)(13)(15)(16)(17)(18)(19)AO (10)(9)A1A2 (8)01 A3 (7)(6)02 A4(5)03 A504 A6 (4)05 A7 (3)(25)06 A8(24)07 A908 A10 (21)A11 (23)A12 (2)A13 (26)(22)S1S2 (27)S3 (20)ROM0" 16.384 X 813 ...0~ A 16.383I--&ENA\jA\jA\jA\jA\jA\jA\JA\j(11 )01(12)02(13)03(15)04(16)05(17)06(18)07(19)08Pins 20. 22 and 27 can be active-low as shown in the symbol on the left or active-high as shown in the symbol on theright. In addition. pin 20 can be either a third chip select (S3 or 83) or a chip enable/power down IE or E).tThis symbol is in accordance with IEEE Std 91/ANSI Y32.14 and recent decisions by IEEE and lEe. See explanation on page 10-1.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • OALLAS, TEXAS 752657-29

TMS4712816,384-WORD BY 8-BIT READ-ONt Y MEMORYfunctional block diagramsSTANDARD ROM4-- Vcc.-- VSSDATA OUTPUTSQl-Q8E/E/S3/S3CHIP SELECT/POWER DOWN LOGICXADDRESSBUFFER:aos:cCD

TMS4712816,384-WORD BY 8-BIT READ-ONLY MEMORYabsolute maximum ratingsSupply voltage to ground potential (see Note 1) .................................. -0.5 V to 7 VApplied output voltage (see Note 1) ............................................. - 1 V to 7 VApplied input voltage (see Note 1) .............................................. - 1 V to 7 VPower dissipation .............................................................. 500 mWOperating free-air temperature ................................................. DoC to 70°CStorage temperature ..................................................... - 55°C to 150°CNOTE 1:Voltage values are with respect to Vss.recommended operating conditionsPARAMETER MIN NOM MAX UNITSupply voltage, Vee 4.5 5 5.5 VHigh-level input voltage, VIH 2 Vee VLow-level input voltage, VIL -1 0.8 VOperating free-air temperature, T A 0 70 °eelectrical characteristics, T A o °e to 70 o e, VOO 5 V ± 10% (unless otherwise noted)PARAMETER TEST CONDITIONS MIN MAX UNITVOH High·level output voltage Vee = 4.5 V, 10H = -1 mA 2.4 VVOL Low-level output voltage Vee = 4.5 V, IOL = 2.1 mA 0.4 VII Input current Vee = 5.5 V, Ov ~ VIN ~ 5.5 V 10 p.A10 Output leakage current Vo = 0.4 V to Vee, ehip deselected ±10 p.Alee1 Supply current from Vee (active) Vee = 5.5 V, VI = Vee Output not loaded 60 mAlee2 Supply current from Vee (power down) Vee = 5.5 V 12 mAeieoInput capacitanceOutput capacitanceVo = 0 V,f = 1 MHzVo = 0 V,f = 1 MHzTA = 25°e,TA = 25°C,6 pF12 pFI/)Q)CJ'S;Q)C~aa:switching characteristics, T A ooe to 70 o e, Vee 5 V ± 10%, see figure 1 tPARAMETERTMS47128-25 TMS47128-35 TMS47128-45MIN MAX MIN MAX MIN MAXUNITta(AD) Access time from address 250 350 450ta(S) Access time from chip select 120 120 120ta(PD) Access time from power down/chip enable 250 350 450tv(A) Output data valid after address change 10 10 10 nstdis Output disable time from chip select/chip enable 100 100 100ten(S) Output enable time from chip select 10 10 10ten(E) Output enable time from chip enable 10 10 10t All AC measurements are made at 10% and 90% points.34TEXASINsrRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752657-31

TMS4712816,384-WORD BY 8-BIT READ-ONLY MEMORY64K bank decode switching characteristics tPARAMETERTMS47128-25TMS47128-35MIN MAX MIN MAXta(SB) Access time from bank select 250 350ten(SB) Output enable time from bank select 10 10tdis(SB) Output disable time from bank select 100 100TMS47128-45UNITMIN MAX45010 ns100t Previously defined switching characteristics remain unchanged.PARAMETER MEASUREMENT INFORMATIONv = 1.755 V= 6450OUTPUTUNDERTEST -JRLr CL = 100 pF:llo3:cCD

TMS4712816,384·WORD BY 8·BIT READ·ONLY MEMORYstandby modevlHAO-A13ADDRESS N__________________________ ~~~----------A-D-D-RE-S-S-N--+-m---------. VILEVIHVILVIH01-08 VALIDIfSTANDBY\tdis ..... I •--·~I ,. .1 ta(PD),11ACTIVE----------------------------VIL ______ ---f}--H+-~~+-----V-A-LlD----J.--.J-. t en( E)64K bank select mode read cycle timingAG-A12 ~:_1'---------------------------------1~'"------I tV(A)---, r-VIH-\!581'582 IVIL I I~ ta(SB) tdiS(SB)---1I~ta(AD)I01-08 --------HI-ZVALIDI141 • .---.t1-ten(SB)ll.IenQ)(.)':;Q)C~oa::14TEXASINSTRUMENPOST OFFICE BOX 225012 • DALLAS, EXAS 752657-33

TMS4712816,384-WORD BY 8-BIT READ-ONLY MEMORYPROGRAMMING DATAPROGRAMMING REQUIREMENTS: The TMS4 7128 is a fixed program memory in which the programming is performed byTI at the factory during the manufacturing cycle to the specific customer inputs supplied in the format below. The deviceis organized as 16,384 8-bit words with address locations numbered 0 to 16,383. The 8-bit words can be coded as a 2-digithexadecimal number between 00 and FF. All data words and addresses in the following format are coded in hexadecimalnumbers. In coding all binary words must be in positive logic before conversion to hexadecimal. Q1 is considered the leastsignificant bit and Q8 the most significant bit. For addresses, AO is least significant bit and A 13 is the most significant.The input media containing the programming data can be in the form of EPROMs, cards, or data formatted in card images(contact TI for details).Either 16K, 32K, or 64K EPROMs can be used or any combination of them.The following is a description of how the cards/card images must be formatted, should they be used instead of EPROMs.INPUT CARD FORMATEach code deck submitted by custome~ shall consist of the following:1 : Title Card2. Comment Cards3. Start of Data Card4. Data Cards:a The cards shall be standard 80 column cards with the information in 'the following format:os: TITLE CARDCCD

TMS4712816,384-WORD BY 8-BIT READ-ONLY MEMORY38394041424344454647 - 52Blank.Customer defined option for device mode pin 20Options:P = power downC = chip selectCustomer defined option for device modeOptions:S = standard ROMB = bank select ROMLogic level for pin 20Options:1 = power down or chip select higho = power down or chip select lowLogic level for pin 22Options:1 = chip select enable higho = chip select enable lowLogic level for pin 27Options:1 = bank select enable higho = bank select enable lowLogic level for pin 26 bank select (1) modeOptions:Blank = standard ROM no bank select (A 13)1 = bank select enable higho = bank select enable lowLogic level for pin 1 bank select (2) modeOptions:Blank = standard ROM no bank select (NC)1 = bank select enable higho = bank select enable lowPin 1 selects high order addresses.Blank.Texas Instruments Device Series (i.e., 47256, 47128)lIeft justified)rn(1)(.)-S;(1)c~oa:COMMENT CARDSAny number of comment cards may be used for specifying the customer's name, individual to contact, telephone number,address, any special instructions, etc. The format for these cards is as follows: The letter 'C' (for comment) must be punchedin column 1, columns 2 - 4 must be blank, and comments can be punched in columns 5 - 80.START OF DATA CARDThis card is to identify that the next card will be the beginning of customer's code. Format is as follows; Columns 1 -4must have '&ROM' punched in them. The remainder of card is blank.84. TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752657-35

TMS4712816,384·WORD BY 8·BIT READ·ONLY MEMORYDATA CARDSThere will be 512 data cards supplied for each customer code. Each card will contain (in hexadecimal) the data for 32 memorylocations. Each data card shall be in the following format:Card Column1 - 45,67 - 7071,7273 - 7677 - 80InformationHexadecimal address of first word on the card, four bits in length.Blank.Data. Each 8-bit data byte is represented by two ASCII characters to represent a hexadecimalvalue of '00' to 'FF'.Checksum. The checksum is the negative of the sum of all 8-bit bytes in the record fromcolumns 1 to 70, evaluate modulo 256 (carry from high order bit ignored). For purposesof calculating the checksum, the value of columns 5 and 6 are defined to be zero. Addingtogether, modulo 256, all 8-bit bytes from column 1 to 70 (columns 5 and 6 = 0), thenadding the checksum, results in zero.Blank.Card sequence number, in decimal (right justified).:xJo3:cCD

MOSLSITMS4725632.768·WORD BY 8·BIT READ·ONLY MEMORYJUNE 1983• 32,768 X 8 Organization• Fully Static (No clocks, No Refresh)• All Inputs and Outputs TTL Compatible• Single 5·V Power Supply• Optional Power Down or Chip Select• 64K Bank Select Option• Maximum Access Time from Address orPower Down:TMS47256-25TMS47256-35TMS47256-45250 ns350 ns450 ns• Worst Case Active PowerDissipation .•. 330 mW• Worst Case Standby PowerDissipation ... 66 mWdescriptionThe TMS47256 is a 262, 144-bit read-only memoryorganized as 32,768 words of 8-bit length. This makesthe TMS47256 ideal for microprocessor basedsystems. The device is fabricated using N-channelsilicon-gate technology for high speed and simple interfacewith bipolar circuits.There are two versions of the TMS47256: the standardROM with options on chip selects and powerdown, and the bank select ROM with similar options.The operation section of this data sheet describes bothversions.TMS47256 ••• JL OR NL PACKAGE tSTANDARD ROM(TOP VIEWINC 1 U28 VCCA12A7232726A14A13A6 r4 25 A8A5A4562423A9AllA3 ~7 22 Sl/SlA2 8 21 Al0Al ;;;920t:: E/E/S2/S2AOQl10111918Q8Q7Q2 =1217~ Q6Q3 13 16 Q5VSS [14 15J Q4t The package for the bank select ROM is shown on page 2.PIN NOMENCLATURESTANDARD ROMAO-A14 AddressesE/E/52/S2 Chip Enable/Power Down or Chip SelectNCNo Connection0l-Q8 Data Out51/51 Chip SelectVCC+5-V SupplyVSSGroundenQ)CJ'S;Q)C~0a:The TMS47256 is fully compatible with Series 74, 74S, or 74LS TTL. The data outputs are three-state for OR-tieingmultiple devices on a common bus. Pins 20 and 22 are mask-programmable, providing additional system flexibility.The data is always available, it is not dependent on external clocking of pins 20 and 22.The TMS47256 is designed for high-density fixed-memory applications such as logic function generation andmicroprogramming. It is pin compatible with TI's full line of ROMs and EPROMs.This ROM is supplied in 28-pin dual-in-line plastic (NL suffix) or ceramic. (JL suffix) packages designed for insertionin mounting-hole rows on 600 mil centers. The device is designed for operation from O°C to 70 0 C.operation, standard ROMaddress (AO-A 14)The address-valid interval determines the device cycle time. The 15-bit positive-logic address is decoded on-chip toselect one of 32,768 words of 8-bit length in the memory array. AO is the least-significant bit and A 14 the mostsignificantbit of the word address.chip select (S1 or 51)Pin 22 can be programmed during mask fabrication to be active with either a high- or low-level input. When the signal14PRODUCT PREVIEWThis document contains information on 8 product underdevelopment. Texas Instruments reserves the right tochange or discontinue this product without notice.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1983 by Texas Instruments Incorporated7-37

TMS4725632,768·WORD BY 8·BIT READ·ONLY MEMORYon both pins 22 and 20 are active, all eight outputs are enabled; and the eight-bit addressed word can be read. Whenthe signal on either pin 22 or 20 is not active, all eight outputs are in a high-impedance state.power down IE or E) or chip select (82 or 82)Pin 20 can be programmed during mask fabrication to be a chip-enable/power-down pin (E or E) or a secondary chipselectpin (82 or S2). Each option can be active-high or active-low. When the chip-enable/power-down pin is inactive,the chip is put into the standby mode. This reduces ICC1, which in the active state is 60 mA, to a standby ICC2of 12 mAo With the chip-select option, pin 20 is functionally identical to pin 22.data out (Q1-Q8)The eight outputs must be enabled by pins 20 and 22 before the output word can be read. Data will remain validuntil the address is changed or the outputs are disabled (chip deselected). When disabled, the three-state outputsare in a high-impedance state. Q1 is considered the least-significant bit, Q8 the most-significant bit.operation, bank select ROM option:Dos:cCD

TMS4725632.768·WORD BY 8·BIT READ·ONL Y MEMORYlogic symbols tSTANDARD ROMS(10)AO(9)A1(8)A2(7)A3(6)A4(5)A5(4)A6(3)A7(25)A8(24)A9(21)A10(23)A11(2)A12(26)A13(27)A14(20)Eb(22) ,.....,ROM0'" 32.768 X 8A'lA'lo A'l>A--32.767 A'l14[PWR OWN]MENA'lA'lA'lA'l(11 ) A401(12) A502(13) A603(15) A704(16) A805(17) A906(18)07A10(10)AO(9)A1(8)A2(7)A3(6)(5)(4)ROM0" 32.768 X 8(3) 0(25) >A32.767(24)(21)(23)(19) A1108 (2)A12(26)A13(27)A14(20) ~S2(22) & lENS1A'lA'lA'lA'lA'lA'lA'lA'l(11 )01(12)02(13)03(15)04(16)05(17)06(18)07(19)08Pins 20 and 22 can be active-low as shown in the symbol ,on the left or active-high as shown ~n the symbol on the right.In addition. pin 20 can be either a secondary chip select (82 or 52) or a chip enable/power down (E or 'ELtThis symbol is in accordance with IEEE Std 911ANSI Y32.14 and recent decisions by IEEE and lEe. See explanation on page 10-1.enQ)(.)·SQ)Q~oa:4TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752657-39

TMS4725632,768-WORD BY 8-BIT READ-ONLY MEMORYfunctional block diagramsSTANDARD ROMDATA OUTPUTSQ1-Q84--Vcc+-vss.BANK SELECT ROMDATA OUTPUTSQ1-Q84--Vcc4--VSS7-40TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265H

TMS4725632,768·WORD BY 8·BIT READ·ONLY MEMORYabsolute maximum ratingsSupply voltage to ground potential (see Note ·1) .................................. - 0.5 V to 7 VApplied output voltage (see Note 1) ............................................. - 1 V to 7 VApplied input voltage (see Note 1) .............................................. - 1 V to 7 VPower dissipation .............................................................. 500 mWOperating free-air temperature ................................................. OOC to 70°CStorage temperature ..................................................... - 55°C to 150°CNOTE 1:Voltage values are with respect to vss.recommended operating conditionsPARAMETER MIN NOM MAX UNITSupply voltage. VCC 4.5 5 5.5 VHigh-level input voltage. VIH 2 VCC VLow-level input voltage. VIL -1 0.8 VOperating free-air temperature. T A 0 70 °Celectrical characteristics, T A o °C to 70°C, VOO 5 V ±. 10% (unless otherwise noted)PARAMETER TEST CONDITIONS MIN MAX UNITVOH High-level output voltage Vee = 4.5 V. IOH = -1 rnA 2.4 VVOL Low-level output voltage VCC = 4.5 V. 10L = 2.1 rnA 0.4 VII Input current Vee 5.5 V. Ov :$ VIN :$ 5.5 V 10 p.A10 Output leakage current Vo = 0.4 V to Vcc. Chip deselected ±10 p.AICC1 Supply current from VCC (active) VCC = 5.5 V. VI = VCC Output not loaded 60 rnAICC2 Supply current from VCC (power down) VCC = 5.5 V 12 rnACi Input capacitanceVo = 0 V.TA = 25°C.f = 1 MHz6 pFCo Output capacitanceVo = 0 V.TA = 25°C.f = 1 MHz12 pFenQ)(J'S;Q)Q:2Eoa:switching characteristics, T A5 V ± 10%, see figure 1 tPARAMETER- TMS47256-25 TMS47256-35 TMS47256-45MIN MAX MIN MAX MIN MAXUNITta(AD) Access time from address 250 350 450ta(S) Access time from chip select 120 120 120ta(PD) Access time from power down/chip enable 250 350 450tvtA) Output data valid after address change 10 10 10 nstdis Output disable time from chip select/chip enable 100 100 100tentS) Output enable time from chip select 10 10 10ten(E) Output enable time from chip enable 10 10 10tAli AC measurements are made at 10% and 90% points.34TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 752657-41

TMS4725632,768-WORD BY 8-BIT READ-ONLY MEMORY64K bank decode switching characteristics tTMS47256-25 TMS47256-35PARAMETERMIN MAX MIN MAXta(SB) Access time from bank select 250 350ten(SB) Output enable time from bank select 10 10tdis(SB) Output disable time from bank select 100 100TMS47256-45MIN MAXUNIT45010 ns100t Previously defined switching characteristics remain unchanged.PARAMETER MEASUREMENT INFORMATIONV=1.755VOUTPUT-lRL = 645 nrUNDERTESTCL = 100 pF:xlo~cCD

TMS4725632,768-WORD BY 8-BIT READ-ONLY MEMORYstandby modeAO-A13VIHADDRESS N__ ~ ______________________ J~~ __________ A_D_D_RE_S_S_N __ +_m _________VILI"VIH1ESTANDBYACTIVE\VILtdis -f4-....-t·1 I.I.. .1 ta(PD)VIHQ1-Q8VALID_____---f}-HI.Zh(..............-__'V_AL_ID___VIL----------------------------j..-..I..- ten(E)64K bank select mode read cycle timing(/)Q)(J':;Q)C~oa:4TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752657-43

TMS4725632,768·WORD BY 8·BIT READ·ONLY MEMORYPROGRAMMING DATAPROGRAMMING REQUIREMENTS: The TMS47256 is a fixed program memory in which the programming is performed byTI at the factory during the manufacturing cycle to the specific customer inputs supplied in the format below. The deviceis organized as 16,384 8-bit words with address locations numbered 0 to 32,767. The 8-bit words can be coded as a 2-digithexadecimal number between 00 and FF. All data words and addresses in the following format are coded in hexadecimalnumbers. In coding all binary words must be in positive logic before conversion to hexadecimal. Q1 is considered the leastsignificant bit and Q8 the most significant bit. For addresses, AO is least significant bit and A 14 is the most significant.The input media containing the programming data can be in the form of EPROMs, cards, or data formatted in card images(contact TI for details).Either 16K, 32K, or 64K EPROMs can be used or any combination of them.The following is a description of how the cards/card images must be formatted, should they be used instead of EPROMs.INPUT CARD FORMATEach code deck submitted by customer shall consist of the following:IIos:cCD

TMS4725632,768-WORD BY 8-BIT READ-ONLY MEMORY38394041424344454647 - 52Blank.Customer defined option for device mode pin 20Options:P = power downC = chip selectCustomer defined option for device modeOptions:S standard ROMB = bank select ROMLogic level for pin 20Options:1 = power down or chip select higho = power down or chip select lowLogic level for pin 22 chip select or bank select (4) modeOptions:Blank = standard ROM no bank select (chip select)1 = chip select enable high or bank select enable higho = chip select enable low or bank select enable lowLogic level for pin 27 bank select (3) modeOptions:Blank = standard ROM no bank select (A 14)1 = bank select enable higho = bank select enable lowLogic level for pin 26 bank select (1) modeOptions:Blank = standard ROM no bank select (A 13)1 = bank select enable higho = bank select enable lowLogic level for pin 1 bank select (2) modeOptions:Blank = standard ROM no bank select (NC)1 = bank select enable higho = bank select enable lowPin 1 selects high order addresses.Blank.Texas Instruments Device (i.e., 47256, 47128)(left justified)t/)(1)(.)'$(1)C~oa:COMMENT CARDSAny number of comment cards may be used for specifying the customer's name, individual to contact, telephone number,address, any special instructions, etc. The format for these cards is as follows: The letter 'C' (for comment) must be punchedin column 1, columns 2 - 4 must be blank, and comments can be punched in columns 5 - 80.START OF DATA CARDThis card is to identify that the next card will be the beginning of customer's code. Format is as follows; Columns 1 - 4must have '&ROM' punched in them. The remainder of card is blank.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • OALLAS, TEXAS 752657-45

TMS4725632,76B-WORD BY B-BIT READ-ONLY MEMORYDATA CARDSThere will be 1024 data cards supplied for each customer code. Each card will contain (in hexadecimal) the data for 32memory locations. Each data card shall be in the following format:Card Column1 - 45, 67 - 7071,7273 - 7677 - 80InformationHexadecimal address of first word on the card, four bits in length.Blank.Data. Each 8-bit data byte is represented by two ASCII characters to represent a hexadecimalvalue of '00' to 'FF'.Checksum. The checksum is the negative of the sum of all 8-bit bytes in the record fromcolumns 1 to 70, evaluate modulo 256 (carry from high order bit ignored). For purposesof calculating the checksum, the value of columns 5 and 6 are defined to be zero. Addingtogether, modulo 256, all 8-bit bytes from column 1 to 70 (columns 5 and 6 = 0), thenadding the checksum, results in zero.Blank.Card sequence number, in decimal (right justified).:zJo3:cCD

Alphanumeric Index, Table of Contents, Selection GuideInterchangeability GuideGlossary/Timing Conventions/Data Sheet StructureDynamic RAM and Memory Support DevicesDynamic RAM ModulesEPROM ·Devices ..ROM Devices·"Static RAM and Memory Support DevicesApplications . Information ..Logic SymbolsMechanical Data

ATTENTIONThese devices contain circuits to protect the inputs and outputs against damagedue to high static voltages or electrostatic fields; however, it is advised thatprecautions be taken to avoid application of any voltage higher than maximumratedvoltages to these high-impedance circuits.Unused inputs must always be connected to an appropriate logic voltage level,preferably either supply voltage or ground.•Additional information concerning the handling of ESD sensitive devices isavailable from Texas Instruments in a document entitled "Guidelines forHandling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies."Please contactTexas InstrumentsP.O. Box 401560Dallas, Texas 75240to obtain this brochure.

MOSLSITMS2114, TMS2114L1024·WORD BY 4·BIT STATIC RAMSDECEMBER 1979 - REVISED AUGUST 1983• Previously Called TMS4045/TMS40L45• 1024 X 4 Organization• Single + 5·V Supply• High Density300·mil (7.62 mm) 18·PinPackage• Fully Static Operation (No Clocks. NoRefresh, No Timing Strobe)• 4 Performance Ranges:ACCESS READ OR WRITETIME CYCLE(MAX) (MIN)TMS2114-15, TMS2114L-15 150 ns 150 nsTMS2114-20. TMS2114L-20 200 ns 200 nsTMS2114-25, TMS2114L-25 250 ns 250 nsTMS2114-45, TMS2114L-45 450 ns 450 ns• 400-mV Guaranteed DC Noise Immunitywith Standard TTL Loads - No Pull-UpResistors Required• Common I/O Capability• 3-State Outputs and Chip Select Control forOR· Tie Capability• Fan-Out to 2 Series 74. 1 Series 74S, or 8Series 74LS TTL Loads• Low Power DissipationdescriptionTMS2114,TMS2114LMAX(OPERATING)550 mW330 mWTMS2114. TMS2114L •.• NL PACKAGEITOPVIEWIA6ASA4A3VCCA7ASA9AD 001A1 002A2 003S 004VSSWPIN NOMENCLATUREAO - A9Addresses001 - 004 Data In/Data OutSVCCVSSiNChip Select+5-V SupplyGroundWrite EnableU)G)CJoS;G)Ct:oc.c.::::stJ)~oEG):e"'CCas~~a:CJo~as~tJ)This series of static random-access memories is organized as 1024 words of 4 bits each. Static design results in reducingoverhead costs by elimination of refresh-clocking circuitry and by simplification of timing requirements. Because thisseries is fully static, chip select may be tied low to further simplify system timing. Output data is always availableduring a read cycle.All inputs and outputs are fully compatible with Series 74, 74S or 74LS TTL. No pull-Up resistors are required. This4K Static RAM series is manufactured using TI's reliable N-channel silicon-gate technology to optimize the costlperformance relationship.The TMS2114/2114L series is offered in the 18-pin dual-in-line plastic (NL suffix) package designed for insertion inmounting-hole rows on 300-mil (7.62 mm) centers. The series is guaranteed for operation from ooe to 70°C.84TEXASINsrRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265Copyright © 1983 by Texas Instruments Incorporated8-1

TMS2114, TMS2114L1024·WORD 8Y 4·81T STATIC RAMSoperationaddresses (AO - A9)The ten address inputs select one of the 1024 4-bit words in the RAM. The address inputs must be stable for theduration of a write cycle. The address inputs can be driven directly from standard Series 54/74 TTL with no externalpull-up resistors.chip select is)The chip-select terminal, which can be driven directly from standard TTL circuits, affects the data-in and data-outterminals. When chip select is at a logic low level, both terminals are enabled. When chip select is high, data-in isinhibited and data-out is in the floating or high-impedance state.write enable (W)The read or write mode is selected through the write enable terminal. A logic high selects the read mode; a logic lowselects the write mode. W or S must be high when changing addresses to prevent erroneously writing data into amemory location. The W input can be driven directly from standard TTL circuits.data-in/data-out (001 -OQ4)Data can be written into a selected device when the write enable input is low. The DO terminal can be driven directlyfrom standard TTL circuits. The three-state output buffer provides direct TTL compatibility with a fan-out of two Series74 TTL gates, one Series 74S TIL gate, or eight Series 74LS TTL gates. The DQ terminals are in the high-impedancestate when chip select (S) is high or whenever a write operation is being performed. Data-out is the same polarityas data-in.cCD

TMS2114, TMS2114L1024·WDRD BY 4·BIT STATIC RAMSlogic symboltRAM 1024x4(5)AO o ...(6)A1A2 (7)A3 (4)A4 (3)0A5 (2)>Ai023A6 (1)A7 (17)AS (16)A9 (15)9,S (S) -,....G1Vi (10) 1EN [READ)L:. 1C2 [WRITE)...., r001 (14) A,2DA,Z3k \73(13)002003 (12)004 (11)wLHXFUNCTION TABLES 001 - DQ4 MODEL VALID DATA WRITEL DATA OUTPUT READH HI-Z DEVICE DISABLEDtThis symbol is in accordance with IEEE Std 91/ANSI Y32.14 andrecent decisions by IEEE and lEe. See explanation on page 10-1.absolute maximum ratings over operating free·air temperature (unless otherwise noted) tSupply voltage, VCC (see Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 VInput voltage (any input) (see Note 1) ............................................. - 1 V to 7 VContinuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 WOperating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ooC to 70°CStorage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 150°CU)(1)(,)'S(1)c~oc.C.::l(/)~oE(1)~"'CCm~cd:a:(,)'';:;m...(/)t Stresses beyond those listed under" Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and functionaloperation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specificationis not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTE 1: Voltage values are with respect to the ground material.recommended operating conditionsTMS2114PARAMETER TMS2114L UNITMIN NOM MAXSupply voltage, VCC 4.5 5 5.5 VSupply voltage, VSS 0 VHigh-level input voltage, VIH 2 5.5 VLow-level input voltage, VIL (see Note 2) -1 O.B VOperating free-air temperature, T A 0 70 °cNOTE 2:The algebraic convention, where the more negative (less positive) limit is designated as minium, is used in this data sheet for logic voltage levels only.84TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752658-3

TMS2114, TMS2114L1024-WORD BY 4-BIT STATIC RAMSelectrical characteristics over recommended operating free-air temperature range (unless otherwise noted)PARAMETER TEST CONDITIONSt MINVOH High-level voltage IOH = -1 rnA Vee = MIN (operating) 2.4VOL Low-level voltage IOL = 3.2 rnA Vee = MIN (operating)II Input current VI- 0 V to MAX10Z Off-state output currentSat 2 VorWatO.8 VVo = 0 V to MAXlee Supply current from Veeei Input capacitanceeo Output capacitancelo=OmA,I TMS 2114 IVee = MAXTA = oOe (worst case)I TMS2114L IVee = MAXVI = a V,f= 1 MHzVo = 0 V,f = 1 MHzTYP* MAX UNITV0.4 V10 IJA±10 IJA90 100rnA50 608 pF8 pFt For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.* All typical values are at VCC = 5 V, T A = 25° C.timing requirements over recommended supply voltage range, T A = 0 °C to 70 o C, 1 Series 74 TTL load,Cl=100 pFPARAMETERTMS2114-15 TMS2114-20 TMS2114-25 TMS2114-45TMS2114L-15 TMS2114L-20 TMS2114L-25 TMS2114L-45MIN MAX MIN MAX MIN MAX MIN MAXtc(rd) Read cycle time 150 200 250 450 nstc(wr) Write cycle time 150 200 250 450 nstw(W) Write pulse width 80 100 100 200 nstsu(A) Address set up time 0 0 0 0 nstsu(S) ehip select set up time 80 100 100 200 nstsu(D) Data set up time 80 100 100 200 nsth(D) Data hold time 0 0 0 0 nsth(A) Address hold time 0 0 0 20 nsUNIT8-4TEXAS. INsrRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265184

TMS2114. TMS2114L1024·WORD BV 4·BIT STATIC RAMSswitching characteristics over re~ommended voltage range, T A == O°C to 70°C, 1 Series 74 TTLload, CL == 100 pFPARAMETERTMS2114-15 TMS2114-20 TMS2114-25 TMS2114-45TMS2114L-15 TMS2114L-20 TMS2114L-25TMS2114L-45MIN MAX MIN MAX MIN MAX MIN MAXtalA) Access time from address 150 200 250 450Access time from chip selecttatS)(or output enable) low70 85 100 120ta(W) Access time from write enable high 70 85 100 120tv(A) Output data valid after address change 20 20 20 20tdis(S)Output disable time after chip select(or output enable) high50 60 60 100tdis(W) Output disable time after write enable low 50 60 60 100read cycle timing tADDRESS. AVIHVILtc(rd)~~ADDRESS VALIDX~I~"{S{-cVIHCHIP SELECT. 5VILtV(AIHVIHOUTPUT DATA. Q HI-Z---{ II-HI-Z-VILta(A)--t>IAll timing reference points are 0.8 V and 2.0 V onlnputs and 0.6 V and 2.2 Von outputs (90% points). Input rise and fall times equal 10 nanoseconds.tWrite enable is high for a read cycle.I \ I J~~;'{SJearly write cycle timing~----------------------tc(wrl .....----------------------~~VIH~~~~ ~~----------------------------------------------,ADDRESS. AWRITE ENABLE. WADDRESS VALIDVIL~~~Y ~~--------------------------------------------~tq------irl' ..... t su (A)VIH ----------!I..UNITnsnsnsnsnsnst oc.C.::::JCJ).. >oEQ)2"CE:(Q~c:(a:VIHCHIP SELECT. SVILINPUT DATA. DVOHOUTPUT. Q VOL -----------------HI-Z84TEXAS .INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752658-5

TMS2114, TMS2114L1024-WORD BY 4-81T STATIC RAMSread-write cycle timingVIHADDRESS. AVIHWRITE ENABLE. WVILVIHCHIP SELECT. SVILVIHINPUT DATA. DVIL---xr----------...x"----VILf.- tsu(A) -toI th(A) j4 .. II \ Ije---i~tW(W)~""'S'-.,---~I---''t II IOUTPUT. aVOHVOLIIITYPICAL APPLICATION DATAEarly write cycle avoids DQ conflicts by controlling the write time with S. On the diagram above. the write operation willbe controlled by the leading edge of S. not W. Data can only be written when both Sand Ware low. Either S or W beinghigh inhibits the write operation. To prevent erroneous data being written into the array. the addresses must be stable duringthe write cycle as defined by tsu(A). tw(W). and th(A).Texas Instruments reserves the right to make changes at any time in order to improve design and to supply the best product possible.8-6TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 7526518·

ADVANCED MEMORYDEVELOPMENT•Fast Address to Match Valid Delay - TwoSpeed Ranges: 45 ns, 55 ns0 512 X 9 Internal RAMTMS2150CACHE ADDRESS COMPARATORMARCH 1982 - REVISED SEPTEMBER 1983TMS2150 ... JDL PACKAGE(TOP VIEW)0 300-Mil 24-Pin Ceramic Side BrazedPackage0 Max Power Dissipation: 660 mW•On-Chip Parity Generation and Checking0 Parity Error Output/Force Parity Error Input0 On-Chip Address/Data Comparator0 Asynchronous, Single-Cycle Reset0 Easily Expandable0 Fully Static, TTL Compatible0 Reliable SMOS (Scaled NMOS) TechnologydescriptionA5A3A2VSS-..... __VCCAlAOABA7A6D5D4D7D6MATCH..r- SThe S-bit-slice cache address comparator consists of a high-speed 51 2 X 9 static RAM array. parity generator. andparity checker. and 9-bit high-speed comparator. It is fabricated using N-channelsilicon gate technology for high speedand simple interface with MOS and bipolar TTL circuits. The cache address comparator is easily cascadable for widertag addresses or deeper tag memories. Significant reductions in cache memory component count. board area. andpower dissipation can be achieved with this device.When S is low and W is high. the cache address comparator compares the contents of the memory location addressedby AO-AS with the data on 00-07 plus generated parity. An equality is indicated by a high level on the MATCH output.A low-level output from PE signifies a parity error in the internal RAM data. PE is an N-channel open-drain output foreasy OR-tieing. During a write cycle (S and W lowl. data on 00-07 plus generated even parity are written in the 9-bitmemory location addressed by AO-AS. Also during write. a parity error may be forced by holding PE low.A RESET input is provided for initialization. When RESET goes low. all 51 2 X 9 RAM locations will be cleared and theMATCH output will be forced high.~...oc.C.::::Jen~oEQ)2"0Cm2«a:(,).~m~enThe cach~ address comparator operates from· a single + 5 V supply and is offered in a 24-pin 300-mil side brazedpackage. The device is fully TTL compatible and is guaranteed to operate from 0 DC to 70 DC.MATCH OUTPUT DESCRIPTIONFUNCTION TABLEMATCH = VOH if:or:or:or:MATCH = VOL if:[AO-AS) = 00-07 +parity.RESET = VIL.5 = VIH.IN = VIL[AO-AS) t 00-07 +parity.with RESET = VIH.5 = VIL. and VII = VIHOUTPUTFUNCTIONMATCH PE DESCRIPTIONL L Parity ErrorL H Not EqualH L Undefined ErrorH H Equal4TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1983 by Texas Instruments Incorporated8-7

TMS2150CACHE ADDRESS COMPARATORfunctional block diagram (positive logic)~------~~----~--------------------------------,COMPC/),..,.. mn":al>3:m=Q.3:CD3o-

TMS2150CACHE ADDRESS COMPARATORabsolute maximum ratings over operating free-air temperature range (unless otherwise specified)Supply voltage range, Vcc (see Note 1) ...................................... " -1.5 V to 7 VI nput voltage range, any input .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -1.5 V to 7 VContinuous power dissipation ...................................................... 1 WOperating free-air temperature range ............................................ O°C to 70°CStorage temperature range ................................................ _65°C to 150°CNOTE1: All voltage values are with respect to Vss.recommended operating conditionsPARAMETER MIN NOM MAX UNITSupply voltage. Vee 4.5 5 5.5 VHigh-level input voltage. VIH 2 6 VLow·level input voltage. VIL (See Note 21 -1 0.8 VOperating free-air temperature. T A 0 70 DeNOTE 2:The algebraic convention. where the more negative (less positivellimit is designated as minimum. is used in this data sheet for logic voltage levelsonly.electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)TMS2150-4TMS2150-5PARAMETER TEST CONDITIONS UNITMIN TYP MAX MIN TYP MAXVOH(M) MATCH high-level output voltage 10H= -2 rnA. VCC=4.5 V 2.4 2.4 VVOL(M) MATCH low-level output voltage IOL=4 rnA. VCC=4.5 V 0.4 0.4 VVOL(PE) PE low-level output voltage IOL=12 rnA. VCC=4.5 V 0.4 0.4 VII Input current VI=O V to 5.5 V 10 10 J1-A10L(PE) PE output sink current VOL =0.4 V. VCC=4.5 V 12 12 rnAShort-circuit MATCHlOSVCC=5.5 V. VO=GND -150 -150 rnAoutput currentICC1 Supply current (operative) RESET=VIH 95 135 85 128 rnAICC2 Supply' current (reset) RESET=VIL 115 145 110 140 mACi Input capacitance VI-O V. f-1 MHz 5 5 pFCo Output capacitance VO=O V. f=1 MHz 6 6 pFac test conditionst/)Q)CJoS;Q)C....-o0.0.::JCI'J~oEQ)~"CCCO~«a:CJ0';:;CO....CI'JInput pulse levelsGND to 3 VInput rise and fall times5 nsInput timing reference levels ....................................................... . 1.5 VOutput timing reference level ....................................................... 1.5 VOutput loading ..................................................... See Figures 1 A and 1 BTEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752658-9

TMS2150CACHE ADDRESS COMPARATORswitching characteristics over recommended ranges of supply voltage and operating free-air temperatureVJ1+m1+n°::Dl>3:m::::Jc.3:CD3o-

TMS2150CACHE ADDRESS COMPARATORPARAMETER MEASUREMENT INFORMATIONVeeTESTPOINTTESTPOINTVee41011FROM OUTPUTUNDERTEST----~-------.8201115 pFFIGURE 1A-PE OUTPUT LOAD CIRCUITcompare cycle timingAO-ASDO-D7

TMS2150CACHE ADDRESS COMPARATORwrite cycle timing::~~~~~~~~~~~~~~~~~~~~~)~~~~~~~~~~~~~~~~~~~~::.l~.-- ADDRESS __ tc_(W __ VALID ~je----- th(A) ---t...... menc:r;lJl>s::m:::Ic..s::CD3o-

MOSLSITMS40162048·WORD BY 8·BIT STATIC RAMFEBRUARY 1981 - REVISED AUGUST 1983• 2K X a Organization. Common I/O• Single + 5-V Supply• Fully Static Operation (No Clocks. NoRefresh)• JEDEC Standard Pinout• 24-Pin 600 Mil (15.2 mm) PackageConfiguration• Plug-in Compatible with 16K 5 V EPROMs• a-Bit Output for Use in Microprocessor-Based Systems• 3-State Outputs with S for OR-ties• G Eliminates Need for External Bus Buffers• All Inputs and Outputs Fully TTL Compatible• Fanout to Series 74, Series 74S or Series74LS TTL Loads• N-Channel Silicon-Gate Technology• Power Dissipation Under 385 mW Max• Guaranteed dc Noise Immunity of 400 mVwith Standard TTL Loads• 4 Performance Ranges:TMS4016-12TMS4016-15TMS4016-20TMS4016-25ACCESS TIME (MAX)120 ns150 ns200 ns250 nsTMS40l6 ... NL PACKAGE(TOP VIEW)DalVeeASA9PIN NOMENCLATUREAO - A10AddressesDa1 - Das Data In/Data Out~Output EnableChip Select+5-V SupplyGroundWrite EnableSVeeVSSWenG)UoS;G)C1::o0.0.:::slen~oEG)~"0Cca~~descriptionThe TMS4016 static random-access memory is organized as 2048 words of 8 bits each. Fabricated using provenN-channel, silicon-gate MOS technology, the TMS4016 operates at high speeds and draws less power per bit than4K static RAMs. It is fully compatible with Series 74, 74S, or 74LS TTL. Its static design means that no refresh clockingcircuitry is needed and timing requirements are simplified. Access time is equal to cycle time. A chip select controlis provided for controlling the flow of data-in and data-out and an output enable function is included in order to eliminatethe need for external bus buffers.Of special importance is that the TMS4016 static RAM has the same standardized pinout as TI's compatible EPROMfamily. This, along with other compatible features, makes the TMS4016 plug-in compatible with the TMS2516 (orother 16K 5 V EPROMsl. Minimal, if any modifications are needed. This allows the microprocessor system designercomplete flexibility in partitioning his memory board between read/write and non-volatile storage.The TMS4016 is offered in the plastic (NL suffix) 24-pin dual-in-line package designed for insertion in mounting holerows on 600-mil (15.2 mm) centers. It is guaranteed for operation from ooe to 70°C.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1983 by Texas Instruments Incorporated8-13

TMS40162048·WORD BY 8·BIT STATIC RAMoperationaddresses (AO - A 10)The eleven address inputs select one of the 2048 8-bit words in the RAM. The address-inputs must be stable forthe duration of a write cycle. The address inputs can be driven directly from standard Series 54/74 TTL with no externalpull-up resistors.output enable iGiThe output enable terminal, which can be driven directly from standard TTL circuits, affects only the data-out terminals.When output enable is at a logic high level, the output terminals are disabled to the high-impedance state.Output enable provides greater output control flexibility, simplifying data bus design.enS ...r;"::a»3:C»= Q.3:CD3o-

TMS4016204H-WORD BY H-BIT STATIC RAMlogic symboltAO (S)Al (7)(6)AZA3 (5)(4)A4(3)A5(2)AG(1)A7(Z3)AS(Z2)A9Al0 (19)S(1S) ....G (20) ...ViDOl(21)(9)DOZ (10)(11)D03(13)D04(14)D05(15)DOG(16)D07(17)DOS~RAM Z048xS010GlGZ> A2~71,2 EN [READ)lC3 [WRITE)...,rA,3Dl.- \74A,Z4W 5L LHXHLHLFUNCTION TABLEG Dal-Das MODEX VALID DATA WRITEL DATA OUTPUT READX HI-Z DEVICE DISABLEDH HI-Z OUTPUT DISABLEDtThis symbol is in accordance with IEEE Std 91/ANSI Y3Z_14 and recent decisions by IEEE and IEC_ See explanation on page 10-1.absolute maximum ratings over operating free-air temperature range (unless otherwise noted) tSupply voltage. VCC (see Note 1) _....... _....... _. __ .... _.. __ ... _. _....... __ . .. -0.5 V to 7 VInput voltage (any input) (see Note 1) __ ......... _.. _.. _......................... _. -1 V to 7 VContinuous power dissipation ... __ .... _.. _.... _. _....... _....... _. _.. __ ... _. _... _. _. . .. 1 WOperating free-air temperature range .... ___ ....... _.... _.. _. _.... _............ _.. _ O°C to 70°CStorage temperature range . __ ....... _...... __ ... _.. _......... _....... _. . . . .. - 55°C to 150°CenQ)(,)-$Q)c~O.CoCo:::lCJ)..>oEQ)~"t:ICca~«a:(,)-.;.....caCJ)t Stresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functionaloperation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specificationis not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.NOTE 1: Voltage values are with respect to the VSS terminal.recommended operating conditionsPARAMETER '. MIN NOM MAX UNITSupply voltage. Vee 4.5 5 5.5 VSupply voltage. VSS\0 VHigh-level input voltage. VIH \ 2 5.5 VLow-level input voltage. VIL (see Note 2) \-1 O.S VOperating free-air temperature. T A \0 70 °eNOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum. is used in this data s,et for logic voltage levels only.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265\\8-15

TMS40162048-WORD BY 8-BIT STATIC RAM...tnQ)...(=i"::ul>s:Q)::::JCos:ell3o-

TMS40162048-WDRD BY 8-BIT STATIC RAMPARAMETER MEASUREMENT INFORMATION+1.755VOUTPUTUNDER TESTtiming waveform of read cycle (see note 5)ADDRESSDQ(out)FIGURE 1 -OUTPUT LOADf4 1IIIt--------tc(rd)---------t~ ...~~------f'~'---111114t------ ta(A)I------'.~1 1N I ;1"--, 1---I I ~ta(G)-----I Il.-tV(A)~N ~',"IG~ 1!1 I Illf "i"G~:.:.:.-:..-=-.-----t-I "-j4 ..a (S-)--t---. Ī -JIIIIWI------ten(S)-----.~1 I tdis(S)~r ,,,' No

TMS40162048·WORD BY 8·BIT STATIC RAMtiming waveform of write cycle no. 1 (see note 6)---... ! '"w,) -l .,._____ADDRESS -A IX:I~ j4- t h(A)G -./I 4 \.(see note 8)I· t4--tsu(S)-----+I I\\1\\\~ ,,,' "" 10) (:?.I--l~Z,....Z,....Z.,...Z..,..Z~;W -I ,,2"A) I ..... 1 _____,,,' """ 9, 13)1 ~ ~DQ(out)~ tw(W)---IN(see note 7) - IDQ(in)timing waveform of write cycle no. 2 (see notes 6 and 11)t::~:;....-------tc(wr)------""",..cADDRESSc(I)

MOSLSITMS4044, TMS40L444096-WORD BY 1-BIT STATIC RAMSDECEMBER 1977 - REVISED MAY 1982• Single + s-v Supply (± 10% Tolerance)• High Density 300-mil (7.62 mm) 18-PinPackage• Fully Static Operation (No Clocks, No Refresh,No Timing Strobe)• 4 Performance Ranges:ACCESS READ OR WRITETIME CYCLE(MAX) (MIN)TMS4044-12, TMS40L44-12 120 ns 120 nsTMS4044-20, TMS40L44-20 200 ns 200 nsTMS4044-25, TMS40L44-25 250 ns 250 nsTMS4044-45, TMS40L44-45 450 ns 450 ns• 400-mV Guaranteed DC Noise Immunitywith Standard TTL Loads - No Pull-UpResistors Required• Common I/O Capability• 3-State Outputs and Chip Select Control forOR-Tie Capability• Fan-Out to 2 Series 74, 1 Series 74S, or 8Series 74LS TTL Loads• Low Power DissipationTMS4044TMS40L44MAX(OPERATING)303 mW220 mWMAX(STANDBY)84mW60 mWTMS4044/TMS40L44 ..• NL PACKAGE(TOP VIEW)AOA1A2A3A4A5QVeeA6A7ASA9A10A11ViDVss 5PIN NOMENCLATUREAD - A11 AddressesDQSVCCVSSiNData InData OutChip Select+5-V SupplyGroundWrite Enablef/)Q)CJoS;Q)Ct::oc.C.:::::Ien>...oEQ)~"Cc:~~

TMS4044, TMS40L444096·WDRD BY 1·BIT STATIC RAMSoperationaddresses (AO-A 11 )The twelve address inputs select one of the 4096 storage locations in the RAM. The address inputs must be stablefor the duration of a write cycle. The address inputs can be driven directly from standard Series 54/74 TTL with noexternal pull-up resistors.chip select (S)The chip-select terminal, which can be driven directly from standard TTL circuits, affects the data-in and data-outterminals. When chip select is at a logic low level, both terminals are enabled. When chip select is high, data-in isinhibited and data-out is in the floating or high-impedance state.tnr+Q)r+n'::%J»s:Q)jQ.s:CD3o-

TMS4044, TMS40L444096·WORD BY 1·BIT STATIC RAMSlogic symbolt(1)AO(2)Al(3)A2(4)A3(5)A4(6)A5(17)A6(16)A7(15)A8(14)A9(13)Al0(12)(1O)(8)AllSViD(11),..RAM 4096xl0"11~ .Gl~ A40095lEN [READ]L". lC2 [WRITE]"""lrA,2D A\7(7)QFUNCTION TABLEINPUTS OUTPUTS W QMODEH X HI-Z DEVICE DISABLEDL L HI-Z WRITEL H DATA OUT READtThis symbol is in accordance with IEEE Std 91/ANSI Y32.14 andrecent decisions by IEEE and IEC. See explanation on palle 10-1.absolute maximum ratings over operating free-air temperature (unless otherwise noted) tSupply voltage, VCC (see Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V[nput voltage (any input) (see Note 1) ............................................. - 1 V to 7 VContinuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 WOperating free-air temperature range . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 DC to 70°CStorage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 150°CNOTE 1: Voltage values are with respect to the ground terminal.t Stresses beyond those listed under" Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functionaloperation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specificationis not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.U)CD(,)oSCDC.......oCoCo:JC/)...>oECD~"CCCO~«a:(,)0';'CO....C/)recommended operating conditionsPARAMETER MIN NOM MAX UNITTMS4044-12 Operating 4.5 5 5.5TMS40L44-1 2 Standby 2.4 5.5TMS4044-20 Operating 4.5 5.5TMS40L44-20 Standby 2.4 5.5Supply voltage, VCCVTMS4044-25Operating 4.5 5.5TMS40L44-25Standby 2.4 5.5TMS40L44-45TMS4044-45 Operating 4.5 5.5Supply voltage, VSS 0 VHigh-level input voltage, VIH 2 5.5 VLow-level input voltage, VIL (see Note 2) -1 0.8 VOperating free-air temperature, T A 0 70 °CNOTE 2: The algebraic convention, where the more negative lIess positive) limit is designated as minimum, is used in this data sheet for logic voltage levels only.TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752658-21

TMS4044, TMS40L444096·WORDBY '·BIT STATIC RAMSfJ),..Q),..n':xJl>3:Q)::Jc..electrical characteristics over recommended operating free-air temperature ranges (unless otherwise noted)VOHVOLII10ZICCCiCoPARAMETERHigh-level output voltageLow-level output voltageInput currentOff-state output currentSupply current from VceInput capacitanceOutput capacitancet All typical vaiues are at Vee = 5 V, TA = 25°C.TEST CONDITIONS10H= -1.0 mA Vee=4.5 VIOL=3.2 mAVee=4.5 VVI=O V to 5.5 VSat 2 V orWat 0.8 VVO=O V to 5.5VTMS40L44Vee=MAXVec=2.4 V10=0 mA TMS4044-12Vec=MAXTA = 0 °c (worst case)TMS4044-20TMS4044-25VCC=2.4 VTMS4044-45 VCC=MAXVI=O V,f= 1 MHzVO=O V,f= 1 MHzMIN Typt MAX UNIT2.4 V0.4 V10 p.A25 4015 2550 5525 3550 55±10 p.AmA8 pF8 pF3:(1)3 timing requirements over recommended supply voltage range, T A = 0 ac to 70 ac, 1 Series 74 TTL load,o CL=100 pF-

TMS4044, TMS40L444096·WORD BY l·BIT STATIC RAMSswitching characteristics over recommended voltage range, T A = 0 °C to 70 °C, 1 Series 74 TTL load, CL = 100 pFTMS4044-12 TMS4044-20 TMS4044-25 TMS4044-45PARAMETER TMS40L44-12 TMS40L44-20 TMS40L44-25 TMS40L44-45 UNITMIN MAX MIN MAX MIN MAX MIN MAXtalM Access time from address 120 200 , 250 450 nsta(S) Access time from chip select low 70 70 100 100 nsta(W) Access time from write enable high 70 70 100 100 nstv(A) Output data valid after address change 20 20 20 20 nstdis(S) Output disable time after chip select high 50 60 60 80 nstdis(W) Output disable time after write enable low 50 60 60 80 nsread cycle timing (see Note 3)ADDRESS, ACHIP SELECT,SOUTPUT DATA, QVVIIHL_______ ~' r~_··_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-___ t_C_(r_d_) _________________n...ADDRESS VALIDAll timing reference points are 0.8 V and 2.0 V on inputs and 0.6 V and 2.2 V on outputs (90% points). Input rise-and fall times = 10 ns.NOTE 3. Write enable is high for a read cycle.tdis(S)---t= ....VILI--t-ta(S)tv(A)VOHHI-ZVOL ~~----------------------~--~~~~_ta(A)-HI-Z-enQ)0'>Q)C....0c.c.::::sen>-...0EQ)~"CCnJ~«a:0'';;nJ....enTEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752658-23

TMS4044, TMS40L444096·WORD BY '·BIT STATIC RAMSearly write cycle timingADDRESS, AWRITE ENABLE, W...-----------tc(wr) ------------~VIH \70~~~ k~--------------------------------------------~VIL~~~Y ~~----~--------------------------------------~VIH --------.1......menCio;ul-3:m~c.3:CI)3o-

MILITARYCMOSLSISMJ55172048-WORD BY 8-BIT STATIC RAMDECEMBER 1983• 2K X 8 Organization, Common I/O• Single + 5-V Supply'• Fully Static Operation (No Clocks,No Refresh)• JEDEC Standard Pinout• 24-Pin 600-Mil (15,2 mm) PackageConfiguration• Pin Compatible with TMS2516, TMS4016,MB8416, HM6116, and TC5517• 8-Bit Output for Use in Microproce~sor-Based Systems• 3-State Outputs with E for OR-ties• All Inputs and Outputs Fully TTL Compatible• Fanout to One Series 54S/74S, Five Series54LS/74LS or Twenty Series 54ALS/74ALSTTL Loads• Complementary Silicon Gate MOSTechnology with a Six TransistorMemory Cell• Power Dissipation:Operating.- Standby- Data Retention• Performance Ranges:descriptionSMJ5517-15SMJ5517-20150 mW Typical5 mW Typical50 p.W TypicalACCESS TIME (MAX)150 ns200 nsThe SMJ5517 static random-access memory isorganized as 2048 words of 8-bits each. Fabricatedusing complementary silicon-gate MOS technology;the SMJ5517 operates at high speed and uses lesspower than conventional NMOS 2K x 8 static RAMs.It is fully compatible with Series 54174, Series54S/74S, or 54LS174LS TTL. Its static design meansthat no refresh clocking circuitry is needed and timingrequirements are simplified. Access time is equalto cycle time. A chip-enable control is provided forcontrolling the flow of data-in and data-out andanother output enable function is included to allowfaster access time.A6A5A4A3A2AlDOlAO-A 10DO 1-008EGVCCSMJ5517 ... JD PACKAGEt(TOP VIEW)VeeA7A6A8A5A9A4 WA3 GA2Al0Al EAOD08DOlD07D02D06D03D05VSS-.... __....r-D04SMJ5517 ..• FG PACKAGE(TOP VIEW)u"uuu uuuzz4 3 2 1 3231305 6 296 287 278 269 2510 2411 2312 2213 2114151617181920PIN NOMENCLATUREAddressData In/Data OutASA9NCWGA10ED08D07Chip Enable/Power DownOutput Enable+ 5-V Supply~S GroundWWrite EnableenCDCJ-:;CDc~oc.c.:::sen... >oECD~"CCco~«a:CJ-.;:...., coenThe SMJ5517 static RAM has the same standard pinout as Tl's compatible 16K SRAMs, and EPROMs. This makesthe SMJ5517 plug-in-compatible with the '4016 and the '2516. Few modifications, if any, are needed for other 16Kt Low cost J package available soon.4ADVANCE INFORMATIONThis document contains Information on a new product.Specifications are subject to change without notice.TEXASINSTRUMENlSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265Copyright © 1983 by Texas Instruments Incorporated8-25

SMJ55172048·WDRD BY 8·BIT STATIC RAM5-V SRAM or EPROM. This allows the microprocessor system designer complete flexibility in partitioning his memoryboard between read/write and nonvolatile storage. Of special importance is the data retention feature of the SMJ5517,as long as Vee ;;:= 2 V, the device retains data indefinitely.The SMJ5517 is offered in a 24-pin dual-in-line ceramic sidebraze package (JD suffix) and in a 32-pad leadless ceramicchip carrier (FG). The JD package is designed for insertion in mounting-hole rows on BOO-mil (15,2 mm) centers, whereasthe FG package is intended for surface mounting on solder pads on 0.050-inch (1 ,27 mm) centers. The FG packageoffers a three layer rectangular chip carrier with dimensions 0.450 x 0.550 x 0.1 00 (11,43 x 13,97 x 2,54)..... en....DICr:u»~DI::2C.~~3o-

SMJ5517204a·WORD BY a·BIT STATIC RAMfunctional block diagramA4 -----t~AS ----4~ ADDRESSA6BUFFERA7 -----t~88 8DQ1·0Q8 -4--t~f---I----4t--~"'"AO A2A1 A3OUTPUTDATACONTROLenCI)CJ'SCI)Ct:oCoCo~en.. >oECI):?!"CCCO:?!

SMJ55172048·WORD BY 8·BIT STATIC RAM,.. rn,.. I»n'::a~s:I»:lQ.s:CD3o- A 2047A6(1)A7A8 (23)A9 (22)(19)A1010 ...(18) _E[PWR OWN)La. G1G - (20) G2W (21) 1.2 EN [READ)L.. 1C3 [WRITE)(9) ~ rDQ14- A.3D A.Z4 ..\74(10).....DQ2(11) _.DQ3DQ4 (13).... .(14)_ ..DQ5(15) ... :DQ6(16) .....DQ7(17) '.DQ8-..FUNCTION TABLEW E G DQ1-DQ8 MODEL L X VALID DATA WRITEH L L DATA OUTPUT READX H X HI-Z POWER DOWNH L H HI-Z OUTPUT DISABLED

SMJ55172048·WORD BY 8·BIT STATIC RAMrecommended operating conditionsSupply voltage, VCCSupply voltage, VSSHigh-level input voltage, VIHLow-level input voltage, VIL (see Note 2)Operating case temperature, TCPARAMETERMIN NOM MAX UNIT4.5 5 5.5 V0 V2.2 VCC- 0 .2 VVSS-0.2 o.a V-55 125 °cNOTE 2:The algebraic convention, where the more negative (less positive I limit is designated as minimum, is used in this data sheet for logic voltage levels only.electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)PARAMETER TEST CONDITIONS MIN Typt MAXVOH High-level output voltage IOH = -2 mA 2.4VOL . Low-level output voltage 10L = 2 mA 0.4IIInput currentAll inputs exceptD01-DOa VI = 0 V to 5.5 V,D01-DOainputs onlyVCC = 5.5 V-1 1-5 5ICC1 Operating supply current from VCC VCC = 5.5 V, 30 90ICC2 Standby supply current from VCC 10 = 0, E = VIH MIN 5ICC3 Data retention supply current from VCC E = VCC -0.2 V 100VCC(DR) VCC required for data retention ~ = VCC(DR) -0.2 V 2 5.5t All typical values are at VCC = 5 V, TC = 25°C.timing requirements over recommended supply voltage range and operating case temperature range ttc(rd)tc(W)tw(W)tsu(A)tsu(E)tsu(D)th(A)th(D)tAVWHRead cycle timeWrite cycle timeWrite pulse durationAddress setup timeChip enable setup timeData setup timeAddress hold timeData hold timePARAMETERAddress valid to write enable highSMJ5517-15SMJ5517-20MIN MAX MIN MAX150 200150 20090 12010 1090 12050 7010 1010 10100 130UNITVVp.Ap.AmAmAp.AVUNITnsnsnsnsnsnsnsnsns(I)Q)CJ'$Q)C1::oc.c.~en...>oEQ)~"CCCO~«IX:CJ'';:CO....ent AC test conditions:Input pulse levels: 0.8 V and 2.2 VInput rise and fall times: tr = tf = 5 nsInput and output timing reference levels: 0.8 v and 2.2 VOutput load: 1 TIL gate, CL = 100 pF34TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 752658-29

SMJ55172048·WORD BY 8·BIT STATIC RAMswitching characteristics over recommended supply voltage range and operating case temperature range ttalA)talE)talGltv(A)tdis(E)tdis(G)tdis(W)ten(E)ten (G)tenlW)PARAMETERAccess time from addressAccess time from chip enable lowAccess time from output enable lowOutput data valid after address changeOutput disable time after chip enable highOutput disable time after output enable highOutput disable time after write enable lowOutput enable time after chip enable lowOutput enable time after output enable lowOutput enable time after write enable highSMJ5517-15 SMJ5517-20MIN MAX MIN MAXUNIT150 200 ns150 200 ns60 70 ns10 10 ns50 60 ns50 60 ns50 50 ns0 0 ns0 0 ns0 0 nst AC test conditions:Input pulse levels: 0.8 V and 2.2 VInput rise and fall times: tr = tf = 5 nsInput and output timing reference levels: 0.8 V and 2.2 VOutput load: 1 TIL gate, CL = 100 pFg capacitance over recommended supply voltage and operating case temperature ranges, fC.s:C1I3o-

SMJ55172048-WDRD BY 8-BIT STATIC RAMPARAMETER MEASUREMENT INFORMATIONvOUTPUTUNDER TEST ---_aT CLFIGURE 1 -timing waveform of read cycle (see note 3)ADDRESSDQloutl= 100pFEQUIVALENT LOAD CIRCUIT1 ...•....-------- tclrdl--------~·I~F----------------------------------~~~-------------1-..... -----ta,AI .1 1~ : t~~i-------------I ~taIGI------.J I ~tvIAI~E"tIi+-tenIGI---t I ii~J;;.----------:'---:----J I I I· II ifI 1oI1 •....-------taIEI----...... 1 I i.--tdiSIGI'-';11.1-----tenIEI----....... ...1 I I- tdislEI D·___________________________ ~~ , ... Not .. "111 __C/)Q)CJ-s:Q)c.......o0.0.:::len...>-oEQ)~"'CCca~

SMJ55172048·WDRD BY 8·BIT STATIC RAMtiming waveform of write cycle no. 1 (see note 4)I»...enn·::Ill>3:I»::::sc.3:CD3o-

SMJ5517204B·WORD BY B·BIT STATIC RAMschematics of inputs and outputsE-EQUIVALENT E INPUT CIRCUITOUTP~ ORWE~sl~:J-~VONIIIIVId5INTERNALJ ~CHIP SELECT ~d dINTERNALJCHIP SELECTEQUIVALENT INPUT CIRCUITd. INTERNAlJCHIP SELECTINPUT BUFFER DRIVERSenQ)(.)'S;Q)C...oCoCo::JCJ)..>oEQ)~"CC(U~

...D)...fA(i'::ul>3:D):::lC.3:CD3o-

Alphanumeric Index, Table of Contents, Selection GuideInterchangeability GuideGlossary/Timing Conventions/Data Sheet StructureDynamic RAM and Memory Support DevicesDynamic RAM ModulesEPROM Devices I~IROM Devices ~Static RAM and Memory Support DevicesApplications Information ..Logic SymbolsMechanical Data

Applications Brief64K DYNAMIC RAM REFRESH ANALYSISSYSTEM DESIGN CONSIDERATIONS64K SYSTEM HARDWARE64 KHZOSCILLATOR.REFRESHCONTROLLER64 KHzOSCILLATORREFRESHCONTROLL'ER128 CYCLE REFRES.H256 CYCLE REFRESH64K64K• 8 bit address mUltiplexing and8 bit address bus are needed foreither 256 or 128 cycle refreshon 64K.• 128 cycle 64K s require 1 lesscounter bit (7 vs. 8). This is, however,unlikely to be a practicalsaving since counters/multiplexerscome in 4 and 8 bit multiples.• 256 cycle/4 ms refresh approachaUows the same oscillator timing(64 kHz) to be used when upgradingfrom 16K s (128 cycle/2 ms period).• Systems designed for 256 cycle64K s can easily use 128 cycle64K s.Compatibility among all 64K Dynamic RAM vendors can be achieved by designing to TI's 416464K x 1 Dynamic RAM. The TMS 4164 requires all 256 rows to be refreshed within 4 ms. Competitive64K D RAMs which are not able to achieve the 256 cycle, 4 ms refresh rate require twicethe number of sense amplifiers as the TMS 4164 and half the number of refresh addresses. A 64KD RAM which requires the 128 cycle, 2 ms refresh treats the 256 cycle, 4 ms refresh as two refreshevents in 2 ms each.Simply:256 cycle in 4 ms = 2 (128 cycle in 2 ms)The extra address bit, A7, during refresh is treated by these vendors as a don't care situation.The TMS 4164 has the same refresh rate as the 4116, 16K x 1 Dynamic RAM, which requires128 rows to be refreshed in 2 ms. Most 4116 based systems already contain the extra refreshcounter bit required for upgrading to the 64K. Those implemented with the 74LS393; 8-bitcounter already do.co.~CO.. E....o.Eenco.~CO.5:aQ.c.

However, the TMS 4164 provides the user with the following advantages:Half the number of sense amplifiers, small chip size, low cost.Lower power yielding lower temperature and increased reliability.More chip area devoted to memory array allowing greater detectable cell charge andimproved performance. . .In summary, the TMS 4164 is compatible with 16K DRAMs and other 64K DRAMs since they areall refreshed at the same rate. An extra counter bit A 7, introduced to the TMS 4164 during refreshwill insure compatibility among all 64K DRAMs.MOS MemoryApplications Engineering•9-2

Applications Brief.256-CYCLE REFRESH CONVERSIONA7 ------____________________________________ ~1------__ ADDRESS 7 TO MULTIPLEXERzao SIGNALSSELECT1-0F-2DATA SELECTORSYSTEM SIGNALSRFSH -----...... .;.....-

EXPANSION OF 3242 FOR 256-CYCLE REFRESH3242RAO-RASoo-osMAo-MAsCAO-CAS A7-A 13CA7REFRESHENABLERFSHENRA7MA7ROWENABLECOuNTROWENCNf20RAO·RA7 • ROW ADDRESSCAO-CA7 • COLUMN ADDRESSESMA"0.M'A6. MEMORY ADDRESSES (INVERTED)MA7· MEMORY ADDRESS (NON-INVERTED)Adding the above circuit to those systems which utilize a 3242 allows the use of 256-cyclerefreshparts. The circuit on the following page may also be incorporated into designs using the3242A where the zero-detect output is not available.These designs are presented to demonstrate possible implementation, however, particular systemrequirements may suggest alternate circuits to optimize component layout.NOTE; The SN74LS153 may be replaced with an SN74LS352 to obtain inverted signal for allmemory addresses.-9-4

EXPANSION OF 3242A FOR 256-CYCLE REFRESH3242ARAG-RA7CAG-CA7REFRESHENABLEROWENABLEC'OuNT"-Ao-A6)r..)A7-A'300-0 6...CA7 0IRFSHENROWENWi¥ ¥ ¥ I¥ ¥ r I0A OB Oc 00 OA OB Oc 00't~Afr SN74LS393RA7 ,r 2~~33_B"""A.......VYr---- MA7RAG-RA7 - ROW ADDRESSCAO-CA7 - COLUMN ADDRESS*MAO-MAs -MEMORY ADDRESS (lNV~RTED)MA7 - MEMORY ADDRESS (NON-INVERTED)This output may be used to implement 256-cycle refresh for 3232 devices in conjunction with the other half ofthe SN74LS153.In summary, these circuits show how to convert a system to a design with maximum flexibilitythat can use either 128-cycle or 256-cycle 64K dynamic RAMs. Meeting this requ irement allowsthe use of any 64K RAM which will ultimately result in the lowest cost and most reliable system.MOS MemoryApplications Engineeringco'+:CO... Eo'too.5enco'+:CO,~Q.c.•

•9-6

Applications BriefTMS4164A AND TMS4416INPUT DIODE PROTECTIONThe 64K DRAM family from Texas Instruments has departed from conventional input schemes for DRAMs toprovide the user with improved ESD protection and input clamping diodes for negative undershoot. Bothenhancements of device capability are possible due to the use by TI of a grounded epitaxial substrate in themanufacture of its 64K DRAMs. While the input circuit technique has provided the user with additional protectionand ease of use, it may cause anomalous testing results for the unwary test engineer who tires to drive theinputs to large negative voltages.Shown below is an equivalent circuit for the input circuitry of the TMS4164A and the TMS4416.FIGURE 1 -IIII- I..: __ JEQUIVALENT INPUT CIRCUITRYThe diode and transistor clamping circuit is the essential element in protecting the device from electrostaticdischarge (ESDI damage. Figure 2 shows the physical layout of this circuit.c:o'';:COE-o"l-.Eenc:o'';:;CO,~C.•Q.cd:9-7

PAD OPENINGIN OVERCOATPADMETALPADMET AL-TO-DIFFUSIONCONTACT OPENINGSP- p-VSS-METALP+FIGURE 2A -DIODE AND TRANSISTOR CLAMPING CIRCUITFIGURE 28 -CROSS SECTION OF CLAMPING CIRCUITThe essential element of the circuit is the input diode (A). which is surrounded by a diffused guard ring (B) connected to VSS.This circuit can be viewed as a combination of a lateral NPN transistor, a bipolar diode, and a thick field transistor - all occupyingthe same area and connected to the input pad. The P - /P + substrate is both the base of the transistor and the anodeof the diode. Both are connected to VSS through the resistance of the substrate from the surface of the chip to the backside.During an ESD with positive voltage, the input diffused area goes into reverse-bias breakdown, which turns on the bipolartransistor, thus clamping the input voltage. The action of the transistor is identical to second breakdown observed in conventionalbipolar transistors. Once the transistor turns on, it can sink a large amount of transient current which is evenlydistributed over the area of the input diffusion (collector of the lateral transistor). This avoids localized heating from theenergy in the ESD. Localized heating could destroy the integrity of the input diode. For ESD with negative voltage, the diodeand the transistor act to clamp the input voltage. When the input voltage drops below - 0.7 V, the input diffusion appears asa cathode for a diode tied through the substrate resistance to ground. It also acts as an emitter for the lateral NPN transistor.Both elements turn on and tend to uniformly source the current in the input diffusion. .The polysilicon resistor included in the input circuit serves to limit the amount of voltage that reaches the thin oxideassociated with the address buffers and clock inputs. The dynamic impedance of the input clamping circuit is considerablylower than the resistance of the polysilicon resistor.•The input circuit also offers the advantage of clamping negative undershoots on the inputs during normal operation. Whilethis provides advantage to the board and system designer, it can cause confusion for the test engineer unless he fullyunderstands the limits of his tester. DRAMs have historically been specified with negative dc input voltages of -1 V. In addition,they are often tested/characterized to - 3 V. This testing has been done to ensure that the devices will operate correctlywith a negative input undershoot, which is transient. Such testing was required due to the inability of a MOSFET ofreasonable size on the chip to clamp the negative-going input and due to the susceptibility of address input buffers on someMOS RAMs to negative input undershoots. The input clamping mechanism, provided on the TMS4164A and the TMS441 6,can supply sufficient current to clamp the input transient.Difficulty in testing the device with negative dc input voltages can occur due to the tester's output driver devices going intosaturation when forward biasing the input diode. Also, most testers are unable to supply the large transient current requirementduring reversal of bias on the input diode and transistor. Both effects will result in distortion of the tester's waveforms.What may appear to be poor setup and hold time margins of the device may actually be a tester's inability to supply the correctwaveforms to the device at the proper time.The improvement in both ESD protection and signal undershoot on system boards offered by the input circuit may beoverlooked if erroneous conclusions are drawn from incoming testing with negative dc input voltages below - O. 7 V.9-8

TESTER LIMITATIONS WITH PROGRAMMED INPUT LOW LEVELS OF LESS THAN - 0.7 VDriver distortion occurs when input low levels are programmed for values below - 0.7 V. The input diodellateral NPN transistorshares a common PN junction which becomes forward biased at - 0.7 V and below. The transistor collector, which istied to VSS, carries most of the forward-bias current (see Figure 3).VssFIGURE 3 -FORWARD- TO REVERSE·BIAS CURRENT, The diode exhibits a classical forward- to reverse-bias recovery delay due to a momentarily large reverse current of amplitudelimited only by the programmed reverse voltage VIH and driver output impedance R, i.e., the input approximates a momentaryshort circuit. An initially large short-circuit current plateau (lR =VIH/R) subsequently relaxes to the normal dc reversebiascurrent IS (see Figure 4). The time from the positive transition edge, corresponding to t= 0 in Figure 4, to the pointwhere the reverse current surge relaxes to 10% of the plateau value is the diode recovery time (toft).VIHR..,.,------ toft -------iP4f10% IRISc:o'';:;CO..E.... o.5t/)c:o'';:;CO,~0.c.

Figure 5 shows how the driver output waveform is altered. During forward bias, the transistor clips the negative level at VFB(in the range - 0.7 V to - 1.4 V) with the VIL level programmed over the range of - O. 7 V to - 6 V. During the initial reversebias, the driver output voltage Yo is given by the programmed VIH level minus the iR drop across the driver output impedance,i.e.,Vo = VIH- iRDuring the current plateau, the Vo value is essentially 0 V. The driver output voltage then recovers to the programmed valueas the diode reverse current relaxes to the dc reverse-bias level IS. In effect, the toft value is a measure of the time that theoutput waveform is distorted if the unwary engineer programs VIL values significantly below - O. 7 V.VoV,H - - - - - - - - - -----.... ----»"0"2-c:;",.. mc·:::len......S'"o3m...2r:::lV,L Vo = VIL(lH) - iRVFO: Forward-bias diode dropV,L: Address input low-level (forward-bias)FIGURE 5 - ADDRESS DRIVER OUTPUT VOLTAGEThe following equation derived from diode switching theory serves to estimate the magnitude of the toft values for input'levels below -1 V.toft = 40 Ir - Ir/(r+ 1)) 2] nswhere r = - (VIL + 1 )/VIHand VIL < -1 VThe coefficient 40 ns is a characteristic of the diode structure and physical parameters of the material. For example,VIL = - 3 V and VIH = + 3 V give toft = 20 ns. This estimate is not accurate at very small forward-bias values, because itignores the rise time of the driver's positive transition edge. As long as the predicted value is greater than or equal to the edgetransition time, the estimate is good. It is assumed that driver output impedance has the same value R at both upper andlower levels, VIIi and VIL.The distortion in driver waveform, shown in Figure 5, increases as the driver input low level is progressively driven morenegative. Depending on driver output impedence, only slight distortion is observed in the positive transition for input levelsnear -0.7 V to -1 V. This irregularity corresponds to the onset of the recovery phenomenon short-circuiting the output ofthe driver .. Significant distortion occurs at large negative values of VIL, and the test engineer must be aware of thisphenomenon to prevent erroneous conclusions as to the performance of the device.The input transistor provides great advantage to device use in a system environment. In a system, the negative undershootof an address line is caused by transient transmission-line reflections (undershoot of negative-edge transitions). Here the inputtransistor clips much of the swing below - O. 7 Von the address line. Positive-edge transition from a settled negative addresslow level, which gives rise to the forward-to reverse-bias recovery delay, does not occur in the typical system environment.9-10MOS MemoryApplications Engineering

Applications BriefTMS4164 AND TMS4416INTERLOCK CLOCKThe TMS4164 (64K x 1) and TMS4416 (16K x 4) dynamic RAMs use a novel interlocked clock to yield enhancedimmunity to process variations, temperature, and voltage induced parametric changes. The basic conceptof an interlock clock structure is to provide a synchronous timing operation that eliminates race conditions.As an aid to understanding the interlock clock, an overview of the memory control structure and its functionswill be presented first.The TMS4164 (Figure 1) and TMS4416 (Figure 2) need a minimum of 16 address bits to address all of their64K memory locations (2 16 = 65,536). Instead of physically using 16 address pins, the DRAMS only use 8address pins and receive the addresses in two parts of 8 bits each (8 (row) and 6 (column) in the case of theTMS4416). The first 8 addresses are called the row addresses; once stable on the address pins, they are latchedby the low going edge of the row address strobe (RAS) input. The 8 column address bits are then set upon the 8 address pins and latched by the low going edge of the column address strobe iCASi input. The TMS4416only uses 6 of the column address lines, disregarding AO and A 7 (These will be utilized in next generation partsproviding an address for 64K x 4 memories). This sharing of address lines is known as multiplexing which keepsthe number of pins on a package to a m,inimum.The TMS4164 and TMS4416 use a square array of memory cells consisting of 256 rows and 256 columnswhich is divided into an upper and lower half. A word line (which corresponds to a row) is connected to thetransfer gates of 256 cells that comprise a row of memory. The transfer gates control access to the data storedon the memory cell capacitor. The bit line (which corresponds to a half of a column) has for each half of thearray 128 memory cells and 1 dummy cell connected to it via the transfer gates. Located physically.betweenthe two halves of the memory array are 256 sense amps whose inputs connect to the bit lines from each halfof the array. The dummy cell provides the reference (VREF) to a sense amp to determine the state of the memorycell.On an access cycle, the row decoders drive the selected word line high turning on all 256 transfer gates in theselected row and connect 1 memory cell to each bit line. Concurrently, dummy enable (DE) decodes and drivesthe transfer gates of one of the rows of dummy cells, and connects 1 dummy cell to each bit line on the oppositeside of the sense amps. The dummy selection uses RA 7 so that the row of dummy cells selected is on the oppositeside of the sense amp from the selected row of memory cells. Connecting the memory and dummy cellsto their respective bit lines causes a differential voltage to be established at the inputs of the sense amps. Thisdifferential voltage is then detected by the sense amps whose outputs will change to reflect the detected stateof the memory cells. After sensing is completed, the output of the sense amp is driven back onto the bit linesto refresh the memory cells. Signal restoration is necessary because an access results in a destructive read (thememory cells no longer contain valid data after the access). This is due to the large bit line capacitance(=600 fF) and the relatively small capacitance of the cell (50 fF). Connecting the cell to the bit line depletesthe cell charge, and makes refresh necessary to ensure valid data retention. This restoration is transparent tothe user but should not be confused with providing external refresh. After sensing is completed, the data onthe bit lines can now be selected by the column decoders. The column decoders select 4 of the 256 sense ampsusing AO-A5 (TMS4164) and A 1-A6 (TMS4416) for the selection. On the TMS4164, these 4 bits are furtherdecoded by a 1 of 4 decoder using A6 and A 7 (the 4 bit output of the TMS4416 eliminates the need for the1 of 4 decoder). This 1 of 4 selector acts as a bidirectional switch for data transfer to or from the sense amps.Now that the basic blocks and functions of a DRAM have been described, a detailed look at the interlock schemewill be presented.A simplified logic representation of the clock structure is shown in Figures 1 and 2. The clock interlock pointsare shown as inverting input NAND gates. The inputs represent timing events that must be complete beforethe output of the inverting input NAND gate can trigger a third event; this system provides interlocking. Approximately60-100 clock signals are generated in a DRAM to control the various functions (address latching, decodetiming, sensing, data transfers within the device, etc.); approximately 15 .of these have been represented. Thefollowing discussion briefly shows the operation of the TMS4164 and TMS4416 DRAMs.co'';:;ca'E..o'too.E(I)co'';:;ca,~C.•Q.

cpI UO,leWJOJUI suo'le:>!ldd"f\)W(3)CASRAS(15)(4)D(2)(9)A7(13)A6(10)A5A4A3A2(11 )(12)(6)(7)A1(5AO(Y» MEMORY ARRAYDUMMY CELLS256 SENSE-REFRESH AMPS Q(14)IY»DUMMYDECODEROWDECODECAO-CA74 of 256 COLUMN DECODEDUMMY CELLSInct(JIY» MEMORY ARRAY 6ct(J CA6CA7FIGURE 1 - TMS4164 BLOCK DIAGRAM

W(4)(1)GCASRAS(16)(5)(10)A7(6)A6(7)A5(8)A4(11)A3(12)A2(13)A1(14)AOROWROW(Yo) MEMORY ARRAYDECODEDUMMYDECODEDUMMY CELLS(Yo) 4 of 256 COLUMN DECODE256 SENSE-REFRESH AMPS4DATA1/0(Yo) 4 of 256 COLUMN DECODECOLUMNADDRESSBUFFERS(6)DUMMYDECODEROWDECODEDUMMY CELLS(%) MEMORY ARRAYCA1-CA6-~~~~- -----~---FIGURE 2 -TMS4416 BLOCK DIAGRAM~UlI ApplicationsInformation

The falling edge of RAS causes R 1 to latch the row addresses into the row address buffers and enables interlock pointR2. The row addresses are then amplified and drive the row decoders for row selection. When RAO-RA 7 are valid, therow address buffers output a signal to interlock point R2. A delay stage within R2 allows the row decoders time to completetheir decoding before the output of R2 goes low. R2 going iow enables the row decoders to drive the selected word linehigh. Interlock R2 ensures two things: the row addresses are valid, and decoding is complete before the selected wordline is activated. Address RA7 causes dummy enable (DE) to select the row of dummy cells on the opposite side of thearray from the selected row of memory cells. After row and dummy selection is completed, the decoders then drive theappropriate word lines high, connecting the memory and dummy cells to their corresponding bit lines. The differential vol~ageat the inputs of the sense amp is sensed, amplified, and driven back onto the bit lines; this refreshes the memory cellsin the selected row. The sense amp control then outputs a signal to interlock RC1 that indicates sensing is complete.A high logic level on CAs holds the reset on 01 active and forces the 0 output of the data out buffer into a high-impedancestate. A logic low level on CAS removes the reset to allow clocking.The falling edge of CAS causes interlock C1 to go low (assuming RAs low) driving C2 low to latch the column addressesinto the column address buffers. Interlock C1 ensures that/he CAS cycle is inactive untilMs is low. The column addressesare then amplified and drive the column decoders for column selection. With CAO-CA 7 valid, the column address buffersoutput a signal to interlock point C3. A delay stage within C3 allows the column decoders time to complete their decodingbefore the output of C3 goes low. C3 going low enables the column decoders to access the selected columns (4). InterlockC3 ensures two things: the column addresses are valid, and decoding is complete before the selected columns are accessed.After selection is completed, data can now either be input or output depending on the Iii signal timing. Interlocks RC1and RC2 ensure that the sense amps are active and the proper column is selected before a read or write can take place.In the case of a read or read-modify-write cycle, the high logic level on the write line (ijh prevents any transfer into thedata in register by keeping the output of W1 high. The presence of CAS low and the output of RC1 low allows RC2's outputto go low; this clocks the level of Winto register 01. Only in the case of an early write (iii low prior to CAS low), whenthe output of 01 is not clocked to a logic one, will the data out register be maintained in the high-impedance state. In anyread cycle, the output of 01 is a logic one and the data out regist~r is enabled although data will not be valid until RAsand CAS access times are both satisfied.In a write cycle, the low logic level on Wallows the output of W1 to go' low which latches the data present at D (thusthe latter of either CAs or Iii going low latches the data). The logic level at the output of the data out register will remainuntil CAS returns to a high leve!.( When CAS is high, the output will go to a high-impedance state.) Data out reflects thedata read from the cell rather than the new data that is written for read-modify-write cycles.The RAS low time following sensing complete, is used to restore data to the memory cells currently selected by the wordline (restoration after the desctuctive read). Any data that is changed by a write cycle causes alterations of the sense amplifierwhich then stores the new data in the memory cells. When RAS goes high, the word line is turned off and the cells nowhold the data restored from the sense amps. RAS going high initializes a precharge state used to equalize the bit lines bycharging them to full VDD potential. Precharge is necess~ry to ensure the charge on the bit lines is equal on both sidesof the sense amp. Another access cycle may begin once the precharge time has been met.•The representation used in Figures 1 and 2 is a simplified logic diagram which does not depict all points of signal interlocking.It does however demonstrate the principle of an interlocked clock scheme. The signal generation and timing becomesvery critical as device delays decrease. In many dynamic RAMs there are over 100 timing signals used to control internaloperations, and these timing signals are generated using delay chains without interlocking. The signal skew resulting fromnon-interlocked timing increases device sensitivity to operating conditions and process variations. Although the interlockclock is transparent to the user, its incorporation on the TMS4164 and TMS4416 offers greater component reliability andavoids timing race conditions inherent in previous generation DRAMs.MaS MemoryApplications EngineeringTexas Instruments reserves the right to make changes at any time in order to improve design and to supply the best product possible.Texas Instruments assumes no responsibility for infringement of patents or rights of others based on Texas Instruments applications assistance or productspecifications, since TI does not possess full access to data concerning the use or applications of customer's products. TI also assumes no responsibility .for customer product designs.9-14

INTRODUCTION TO SURFACE MOUNT TECHNOLOGYABSTRACTThe demand for high-density, cost-effective printed circuitboards has prompted the electronics industry to seek alternativemethods to traditional plated-through-hole technology.One such alternative is surface mounting, a technology traditionallyused in hybrid fabrication. The advantages· of surfacemounting are numerous but the bottom line is that itis cost effective and will begin to displace plated-throughholetechnology as the a~ailability of surface-moUlit componentsincreases.Texas Instruments is fully supporting the growth of thesurface-mount industry with its line of plastic leaded chipcarriers. An introduction to the surface-mount technologywill be given in this application report.INTRODUCTIONThe post molded leaded chip carrier (pLCC) wasdeveloped by Texas Instruments in 1980 to improve the packingdensity of ICs on printed circuit (PC) boards and overcomesome of the size constraints normally caused by dualin-line(DIP) packages. The PLCC was also designed to beused under the same environmental conditions as the DIPwithout any reliability degradation. The PLCC occupies approximately40% to 60% of the PC board area of anequivalent DIP, and requires no through holes (surfacemount), therefore, it lowers the cost on PC boards. Unlikesome surface-mounted packages, TI's PLCC requires nospecial PC board material considerations. The design of thelead provides compliance allowing the use of any commercialsubstrate. Digital, Linear, Gate Array, and MOS deviceswill be offered in 18-, 20-, 28-, 44-, 52-, 68-, and 84-pinpackages through TI.Package OutlineThe mechanical data for the PLCCs is given in Figures1 and 2; their thermal properties are listed in Table 1. Thefollowing general statements apply to the packages:1. Each of the chip carrier packages consists of a circuitmounted on a lead frame and encapsulated within anelectrically nonconductive plastic compound. The compoundwithstands soldering temperatures with no deformation,and circuit performance characteristics remainstable when the devices are operated in high humidityconditions.2. These packages are intended for surface mounting onsolder pads with 1,27-mm (0.050-inch) centers. Theleads require no additional cleaning or processing whenused in soldered assembly.3. All dimensions shown are metric units (millimeters),with English units (inches) shown parenthetically. Inchdimensions govern.4. Lead spacing shall be measured within the zonesspecified.5. Tolerances are noncumulative.6. Lead material CD-155. T60 (Copper Alloy).7. Dimple in top of package denotes pin 1.s::::o'+IaJ...E.....o.Etns::::o'+IaJCJ'=a•0.~9-15

~--------::~~:~:~~~:--------~~7,34(0.289)~I.-==..c::::l...- 7,14 (0.281) ~ I10 9 812rr:·-1111,86 (0.467)11,61 (0.457)13l 0,686 (0.027)0,660 (0.026)10,90 (0.429)"~['42'114~11_: ____________ 4-______ +--JSEATING PLANE17l>"C~n'Q)....0':::l(I)5'0'...3Q)....0':::l0,737 (0.029)0,635 (0.025)1,12 (0.044)MAXFigure 1. Plastic Chip Carrier Package (FP Suffix)9-16

NO.OFTERMINALS2028445268AMIN9,70(0.382)12,24(0.482)17,32(0.682)19,86(0.782)24,94(0.982)MAX MIN10,03 8,89(0.395) (0.350)12,57 11,43(0.495) (0.450)17,65 16,51(0.695) (0.650)20.19 19,05(0.795) (0.750)25,27 24.13(0.995) (0.950)BCMAX MIN9,04 8,08(0.356) (0.318)11,58 10,62(0.456) (0.418)16,66 15,70(0.656) (0.618)19,20 18,24(0.756) (0.718)24,28 23,32(0.956) (0.918)MAX8,38(0.330)10,92(0.430)16,00(0.630)18,54(0.730)23,62(0.930)18 17 16 15 14 13"mBA1,27 (0.050) X 45'NOM4,78 (0.188)4,06 (0.160)1,14 (0.045)0,63 (0.025)2,41 (0.095) MIN2526 27 28~'14(0'045)X45'oNOMB------~~------ A-----------~L 1,35 (0.053)1,19 (0.047)ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES.Figure 2. FN Plastic Chip Carrier PackLlgeTable I. Thermal Properties. of Plastic Chip Carriersco.~ca... Eo~..5enco.~.~Q.Co«'NO. OF PACKAGEOJA (0 C/N) OJC (0 C/W)LEADS DESIGNATION18 FP 85.4 13.820 FN 113.6 37,128 FN 76,8 32.244 FN 68,0 20.368 FN 45,7 11.49-17

J-Lead AdvantageTexas Instruments PLCC packages are constructed withthe I-lead structure due to its superior performance whenmounted on a wide spectrum of substrates ranging fromceramic to epoxy-glass. This is possible due to the compliancyof the I-lead which compensates for the possible thermalmismatch between plastic packages and mounting substrates.More care must be taken when using ceramic leadless chipcarriers mounted on nonceramic substrates in order to preventsolder joint fracturing under thermal cycling. The I-leadalso offers advantages over plastic surface-mount packagesusing different lead structures. Figure 3 gives a comparisonof the I-lead used on the PLCC to the "gull wing" commonlyused on small-outline integrated circuits (SOlCs)and "quad packs."GULL WINGDEVICE AREA (16 L-PIN SOIC) = 111.6 mm 2(0.173In 2 )ADVANTAGES- PROVEN PROCESS- POSITIVE SOLDER 'WITNESS"- EASY AUTO-POSITIONING- NESTED STACKING (PERIPHERAL)DISADVANTAGES- EXTENDS X-Y SIZE- LEADS SUBJECT TO DAMAGE- HIGH PIN COUNT PACKAGES IMPRACTICALJ-LEAD:t>"C"2-n'Q)..0':sen5".., d'3...m0'::l- PROVEN PROCESSADVANTAGES- LEADS ARE COMPLIANT. USEABLE WITHPC BOARD AND CERAMIC SUBSTRATES- MINIMUM X-Y SIZE. MAXIMUM BOARD DENSITY- EASY AUTO POSITIONING- LEADS WELL PROTECTED- EASY REPLACEMENT- SOCKETING EASYDEVICE AREA (18-PIN PLCC) = 98.6 mm2- JEDEC STANDARDS EXIST- STAND-OFF FROM THE BOARD ALLOWS EASY CLEANING- LARGEST LINE OF AVAILABLE PACKAGES:FROM 18 TO 68 LEADS. HIGHER PIN COUNTS UNDERDEVELOPMENT(0.1531n2)DISADVANTAGES- TOTAL PACKAGE-HEIGHT THICKER THAN SOIC- INFRARED URI REFLOW DIFFICULTFigure 3. Gull Wing Vs. J-Lead9-18

Area Savings with PLCCThe pe board area savings that can be realized with thePLee is best demonstrated by a comparison of two TexasInstruments one· megabyte memory boards (see Figure 4).The DIP board is eight layers, measuring 279,4 rom(11 inches) by 355,6 nim (14 inches) with 226 les. ThePLee board is four layers, measuring 165,1 rom (6.5 inches)by 243,84 mm (9.6 inches) also with 226 les. The savingsthat can be realized with the PLee board amounts to 60%less board area at an overall cost savings of approximately55 %. This illustrates the viability of surface mount as a lowcost means of improving circuit board density while reducingpe layout complexity.Figure 4. PLCC and DIP One Megabyte Menwry Expansion Boardsco'';:;mE ...o .....CtilCo'';:;m,2C.Co

Surface Mount Component AvailabilityMost IC manufacturers are presently producing surfacemountcomponents for a large part of their product line. Thedevices available range from the sophisticated VLSI to thediscrete transistor. Non-integrated circuit components rangingfrom chip resistors and capacitors to surface-mount connectorsare also being produced in volume by major manufacturers.As the demand for surface-mount components increases,most products now produced for standard throughholetechnology will also be available in surface mount. Asof the printing of this application report TI produces over700 ICs in surface mount packages.Surface mounting consists of five basic steps:1. PC board design2. Solder paste application3. Component mounting4. Oven drying (optional)5. Solder retlowA brief description of each step will be given; detaileddescriptions of the various steps can be obtained by componentand equipment suppliers and from numerous technicalarticles on surface mounting.PC Board DesignTo produce reliable surface-mount PC boards the designerhas to pay particular attention to IC solder pad (also termedfootprint) layout. Not providing adequate footprint area andproper orientation will generally yield poor solder joints andlack of self-centering during retlow. Figure 5 shows therecommended footprints for the I8-pin PLCC. When layingout the IC footprints, as a general rule the footprint shouldextend approximately 10-15 mils past the outer edge of thePLCC lead. This provides a good solder fillet that will extendup the outer edge of the PLCC lead to yield a reliablesolder joint that is easily inspected. The 70-80 mil lengthof the footprint should be a minimum, however a longer footprintcan be used. It is recommended that the dimensionsA and B never be less than the minimum width or lengthof the IC.l>"C'2.,.Cr... mci"~en:r .....0~3... ms·~A8.81 (0.347)8.05 (0;317)~r0.762 (0.030)00.635 (0.025)L ( )T ( )( )( )... J.... ""-12.03 (0.080)1.78 (0.070)00000 00 0 0( )( )( )( )~......12.4 (0.487)11.6 (0.457)BFigure 5. I8-Pin PLCC Footprint9-20

Solder Paste ApplicationSolder paste can be applied using several methods: screeningthrough a stencil or stainless steel mesh, pneumaticdispensing or by hand application with a syringe. TexasInstruments recommends screening through a stainless steelscreen. The screen mesh must be chosen in accordance withthe mesh of the solder paste to provide an adequate emulsionof the solder paste and to prevent screen clogging. Ingeneral an 80-100 mesh screen should be used with 200 meshor finer solder paste particle. There are a number of factorsthat need to be considered when selecting a solder paste, afew key factors are as follows:1. Particle size2. Particle shape3. Percentage of metal content4. Temperature rangeComponent PlacementThe components can be placed via several different modesinto the still moist solder paste. In a production environment,the components are most efficiently placed with an automaticpick-and-place machine to achieve both speed and accuracy.Presently, pick-and-place machines can place between 600and 600,000 components per hour and are priced accordingly.In a research and development environment, hand placementcan be adequate due to the forgiving nature of surfacemounting. When a component is placed off center it will tendto self-align during reflow due to the surface tension of themolten solder. Naturally there are limits to the amount ofmisalignment that can be corrected. Two important aspectsof self-alignment are provision of adequate solder pad area,and proper placement of the solder pads with respect to thecomponent.Oven DryingAs solder pastes have evolved over the past several years,the drying process following component placement is notalways necessary. In the past, drying was necessary to driveout the solvents in the solder paste. If the solvents were notdriven out, the formation of solder balls was frequent dueto the out gassing of the solvents prior to reflow. Todaymanufacturers of solder pastes report that drying is no longernecessary when using many of the new solder paste formulations.As a wide variety of solder pastes exists, it is necessaryto consult the manufacturer before determining if drying isnecessary in your process.Solder ReflowWhile several methods of solder reflow are available,vapor phase soldering has been the most successful and isbecoming the industry standard.Two types of vapor phase systems are the batch and thein-line. The batch system is a two-vapor system that uses afluoroinert liquid such as FC-70 for the primary vapor anda clorofluorocarbon such as trichlorotrifluoroethane (R113)as the secondary liquid (see Figure 6). The secondary liquidhas a lower boiling point (47.6°C) than the primary liquid(215°C) thus acting as a blanket to prevent loss of the expensiveprimary liquid. The in-line system (see Figure 7)is a single-vapor system using only a primary vapor (suchas FC-70). The batch system is the forerunner of the in-lineand is more suited to development and small productionwhere the in-line is tailored to a mass production atmosphererequiring good throughput and minimal operating expense.Although the two systems are targeted to different marketstheir basic operation is the same. Both are capable of singleand double sided surface mount.Batch System OperationThe PC board complete with components is plated on anelevator and lowered into the secondary vapor. The elevatorascent-descent rate and dwell in the two vapor zones can bepreset via the vapor phase machine front panel. The descentrate and hold time in the secondary zone should be set soas not to unnecessarily disrupt the secondary vapor blanketor cause defluxing of the solder paste. Lowering the boardinto the 215°C primary zone causes the solder to reflow.A dwell time of 10-30 seconds in the primary zone is generallysufficient for most PC boards. The dwell time in theprimary zone is a function of the PC board mass. Once thesolder is reflowed, the PC board is raised back into the secondaryzone where the molten solder is allowed to solidify.In the batch system it is necessary to pay particular attentionto the ascent-descent rate of the elevator as the disruptionof the two-vapor zones will cause unnecessary loss ofthe expensive primary liquid.In-Line System OperationThe operation of the in-line system is similar to that ofthe batch system except that there are no secondary vaporor dwell times with which to contend. The PC board is placedon a conveyor belt that transports it through the system ata constant speed. Passing through the vapor zone the solderbecomes molten and solidifies as it moves toward the systemsexit. Where the ascent-descent rate and dwell time are criticalto the batch system, the conveyor speed is critical to the inlinesystem. The speed at which the conveyor should be setis also a function of the PC board mass.r::o'';:CUE.......o.EC/)r::o'';:CU,~C.c.

fiSECONDARYVAPOR(VAPOR BLANKET)..Figure 6. Vapor Phase Reflow System with Secondary Vapor Blanket•IPRODUCTSYSTEM INLETJVAPOR ZONElJSYSTEM OUTLET. VAPOR CONDENSINGCOILVAPORCONVEYOR CONDENSING PRODUCTL:~~ Ji -L-~-~~~";~~:;~:~i.A~~~.~~' _~~~~~_C_E_~ _~(:~:OADVENTILATIONSATURATED VAPORVENTILATIONIMMERSION HEATING ELEMENTSBOILING FLUOROINERTELECTRONIC FLUIDFigure 7. In-line Single Vapor Heating System Schematic9-22

CleanupFollowing the soldering process, it is necessary to removethe flux residues. These residues can be removed by traditionalcleanup methods if the components have approximately5 mils clearance to the PC board. One benefit of the PLCCwith its J-leads is that it provides approximately 29 mils ofclearance. Special soaking, agitation, or other methods willbe necessary to provide adequate cleanup for componentswith less that 5 mils of clearance.CONCLUSIONA brief overview of surface-mount technology has beengiven showing its advantages over standard plated-throughholetechnology. Surface mounting is a cost-effective, sensiblesolution to the ever increasing demand for denser circuitboards. Detailed information about surface mounting isavailable from most major component and equipmentmanufacturers and through numerous technical articles onthe subject. As the electronics industry strives to implementmore functions in a given area, Texas Instruments believessurface mounting will become the predominant mountingtechnology of the future.MOS MemoryApplications Engineeringco"';:;«SE ...-E.5tnCo".;:i«S"~Q.c.~9-23

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Applications BriefTTL DRIVERS FOR THE TMS4416-15Some form of drive circuitry is needed when DRAMs are used with processors. such as the Z-80 or Z-8000. Onepossible solution involves the use of a precision delay line; however. a more cost-effective and efficient approachuses TTL devices as drivers. Two versions of TTL driver circuits are shown in Figures 1 and 2. The first figureshows the drive circuit for a memory array using TMS4416-1 5 DRAMs and the Z-80 processor; Figure 2 showsthe same array configured for use with the Z-8000 processor. Both circuits are designed to drive 256K bytes ofmemory arranged in either 8- or 1 6-bit words. They provide all DRAM control signals. address multiplexing. andrefresh address generation. The circuits shown for the Z-80 and the Z-8000 use the hidden refresh provided bythese devices so that refresh/access arbitration is not necessary. Time delays were selected to provide maximumperformance from the TMS4416-15 with off-the-shelf components. (Enhanced operation could be obtained byhand sel,ecting components for single applications.) A comparison of the two circuits will reve~1 the differencesbetween the two. The following description applies to both circuits.The memory array is arranged as 4 banks of 8 TMS4416s. Two TBP18S030 PROMs decode and generate thecontrol signals for the drive circuit. BAO and BA 1 are used to select which bank of memory will be accessed.MREQ and ACCESS are NORed and then delayed by 3 inverters to provide a CAS signal. The MUX Signal thatis used to switch the 74S153 multiplexers and propagate the column address to the memories is taken fromthe output of the first inverter in the CAS delay. CAS is connected to all the devices in the array. (Since RASacts as a chip enable. CAS will only activate the memories in the bank that has RAS active; this keeps the powerconsumption of the array lower than using CAS as select logic.) Two CAS drivers are used to reduce the effectsof the capacitive load of the DRAM CAS inputs. (This also improves drive characteristics and reduces noise.)Seri~s damping resistors have been added to reduce ringing on the address lines. These resistors should bebetween 15 and 68 ohms. depending on the circuit board layout. and can be determined by examining theaddress waveforms with an oscilloscope and selecting a value that produces the cleanest signal. The desired8- or 16-bit data word from the active bank is selected using RO. R 1. and the READ line. RO and Rl can beaddress lines from the Z-8001 or they can be generated from memory mapping logic. If the READ input is lowduring an access cycle. the output enable of the TMS4416 will be activated (RDA-RDD); a high input to READwill select a write output (WRA-WRD). Using this matrix. the memory can be divided into sixteen 16Kx8 oreight 16K x 16 blocks. The desired word width of the data output will be dependent on the microprocessorbeing used. For an 8-bit data bus the two data busses shown in the diagram would be connected in parallel.Since the Z-80 only directly accesses 64K of memory. bank select logic must be included in this memory systemto provide higher order address lines. The design of the bank select circuitry has been left up to the user. butmight include memory mapping or other logic.coo+:;COE ...o'+-.5encoo+:;COo~C.•Q.ct9-25

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An external refresh counter has been added to the drive circuit for the Z-80 since the Z-80 internal refresh counter doesnot support 256 cycle refresh. (Application Brief DR-7 shows a circuit to add the extra refresh address bits similar to theimplementation used here.) As the Z-8000 provides 9-refresh-address bits, its internal refresh counter was used.A description of the signals used in both circuits previously illustrated is given in Table'. Due to slight differences in thesignals available from the Z-80 and Z-8000 processors, a slight modification of the interface between the processor and theTTL drive circuits shown will be required. The differences in the interface are shown in Figure 3. The DS signal is generatedfrom the Z-80's RD and WR lines. The B/Vii input should be tied to a 5-' 0 kilohm pullup resistor. The RFSH signal can bedecoded from the status lines of the Z-8000 as shown with the 74S138; however, it could also be done with other typesof logic if desired. The address of the Z-8000A is only guaranteed valid for 35 ns so the address latches are necessarywhen using DRAMs with this microprocessor. MREQ is used to enable the 74LS373 transparent latches for both memoryaccesses and refresh cycles.TABLE 1 -SIGNAL DESCRIPTIONSIGNAL NAMEMREOBAO,BA'BSRFSHDSRO, R1READB/WAO-A15DESCRIPTIONFrom the Z-80 or Z-8000, indicates address validAddress for RAS selection, decoded from high order addresses.Board select to designate DRAM access, decoded from high order addresses.Z-80 output or decoded from the Z-8000 status outputs. Signals a refresh cycle.Z-8000 output indicating data valid on the multiplexed address/data lines.Address for read or write selection, decoded from high order addresses.If low, indicates a memory read and if high, indicates a memory write.Indicates if the Z-8000 is doing a 8-or , 6-bit memory access.Z-BO address outputsc;'D)...O·::Jen5'.......o3Q)...•o·::JADO-AD15Z-80»"C"2-ii5==Q-Wii74S08Z-BOOO multiplexed address/data linesosBANKSElO ------ ROBANKSEL1 ------ RlRo ------ READVee ----'I/II'Ir-- BtWSKUBANKSH2 ------ BAaBANKSEl3 ------ BAIZ-8000os------osAO------ROBANKSElO ------ RlBtW ------ BtWBANKSHI ------ BAaBANKSEl2 ------ BAI+5SKUGlG2AST3STOG2B74S138ASTlST2FIGURE 3 - INTERFACE CIRCUITRY DIFFERENCES9-28

Tables 2 and 3 list the data for the PROMs to provide the control signals. Both the binary and hexadecimal programming datahave been supplied.TABLE 2 - PROM A PROGRAMPINNAMEFIGURENAMEA3 A2 Al AO 07 06 05 04 03--BS RASl-- --RFSH BAl BAO RASO RAS2 RAS3 ACCESS0 X X X 0 0 0 0 1 OF1 0 0 0 0 1 1 1 0 711 0 0 1 1 0 1 0 B71 0 1 0 1 1 0 1 0 071 0 1 1 1 1 1 0 0 E71 1 0 0 1 1 1 1 1 FF1 1 0 1 1 1 1 1 1 FF1 1 1 0 1 1 1 1 1 FF1 1 1 1 1 1 1 1 1 FFHEXTABLE 3 - PROM B PROGRAMPINNAMEFIGURENAMEG A3 A2 Al AO 07 06 05 04 03 02 01 00Os B/W REAO Rl RO ROA ROB ROC ROO WRA WRB WRC WRO0 0 0 0 0 0 0 1 1 1 1 1 1 3F0 0 0 0 1 0 0 1 1 1 1 1 1 3F0 0 0 1 0 1 1 0 0 1 1 1 1 CF0 0 0 1 1 1 1 0 0 1 1 1 1 CF0 0 1 0 0 1 1 1 1 0 0 1 1 F30 0 1 0 1 1 1 1 1 0 0 1 1 F30 0 1 1 0 1 1 1 1 1 1 0 0 FC0 0 1 1 1 1 1 1 1 1 1 0 0 FC0 1 0 0 0 0 1 1 1 1 1 1 1 7F0 1 0 0 1 1 0 1 1 1 1 1 1 BF0 1 0 1 0 1 1 0 1 1 1 1 1 OF0 1 0 1 1 1 1 1 0 1 1 1 1 EF0 1 1 0 0 1 1 1 1 0 1 1 1 F70 1 1 0 1 1 1 1 1 1 0 1 1 FB0 1 1 1 0 1 1 1 1 1 1 0 1 FD0 1 1 1 1 1 1 1 1 1 1 1 0 FE1 X X X X 1 1 1 1 1 1 1 1 FFHEXco"';:CO... E.... o.E,enco"';:CO"~Q.Co~The TTL drive circuits previously described allow the TMS4416-1 5 to operate at maximum speed. Although there are manyways to provide the necessary control signals for DRAMs, the drive circuits described will provide insight into the controllogic that is necessary to use dynamic RAMs. TTL circuitry was selected in order to avoid the cost of a precision delay line.MaS MemoryApplications Engineering9-29

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TMS4416/7220 GRAPIDCSAs the increased activity in computer graphics grows, theneed for dedicated graphics peripherals and video memorybecomes apparent. The NEC 7220 is currently a good answerfor a high resolution single chip graphics controller. The 7220provides all of the necessary graphics primatives for line,arc, and rectangle drawing, as well as area fill routines.Signal timings are easily adapted with extemallogic to providethe proper memory and video timings, with programmablefeatures allowing the user to do in software what hastypically been implemented in hardware. To take advantageof the 7220' s wide spectrum of operation requires a memorythat is also well adapted to graphics applications. TheTMS4416 16K x 4 dynamic RAM provides such a memory,with modularity and bandwidth advantages over 64K x 1memories. The architecture of the TMS4416 provides an outputenable function (relieving the need for databus buffers),faster access times and a 4X bandwidth improvement overXl devices of the same speed. Although 64K x 1 nibble modeparts out perform standard 64K x Is, they can not match thebandwidth of the TMS4416 and they require more memorycontrol circuitry to perform the same function. The modularityof the TMS4416 offers efficient memory usage in manyapplications and is well suited for both single and multi planememory systems.This application report describes a design coupling the7220 and the TMS4416 in a single plane, bit mapped graphicssystem. The main objective is to provide a detailed exampleof the necessary memory interface. While the design doesnot use all of the capabilities of the 7220 (DMA, Zoom, LightPen, etc.) .it does provide an easily adaptable example thatcan be tailored to many applications. This particular systemcan be switched between a 512 x 240 noninterlaced and512 x480 interlaced display by changing a single 7220parameter byte. To simplify the host interface an existingZ80A based computer was used to communicate to the 7220in a Multibus* system, with all the programming done inBASIC.To evaluate the design, calculations of the memory andvideo requirements will be given with a brief discussion ofkey points of interest. Measured drawing times for an arcand area fill are included to provide some feel for the drawingspeed of the 7220.Referring to the schematic (Figure 1), the graphics boardcan be divided into five functional blocks: Multibus* interface,7220, memory control, display memory, and video outputcircuitry. Four of the blocks will be discussed while adetailed understanding of the 7220 is left to the reader (NECprovides a 7220 Design Manual which is essential to understand7220 operation).A simple Multibus interface has been implemented forcontrol of the graphics system. The low order eight bits ofthe data bus are buffered with a 74LS640 transceiver. Thistransceiver is controlled by 10RC and output YO of the*Trademark of Intel Corporation.74LS138 (board select logic). The lU) and WR signals arederived from 10RC and rowc in conjunction with the boardselect. The XACK signal, required to terminate all liD operationsis generated by using the board select to enable a74LS241 whose input is tied to ground. The Multibus signaltimings were sufficient to meet the 7220 specificationswithout the use of complicated logic.The memory array is made up of four TMS4416s providing262,144 pixels. With the CAS circuitry shown, thememory space can be upgraded to sixteen TMS4416s for1,048,576 pixels which allows the maximum display resolution(1024 x 1024) of the 7220 to be implemented. TheTMS4416 offers improved modularity over the 64K xl(which relates to less wasted memory space) and is welladapted for multiplane memory systems. A four plane colorsystem of 512 x 512 display resolution requires sixteen 64KDRAMs. For the TMS4416 application, the memory breaksinto four physically separate planes which are simultaneouslyaccessed once per display cycle. With 64K x Is, the fourmemory planes reside in the same physical memory, and requirefour separate accesses to memory per display cycle.This significantly reduces the obtainable bandwidth and alsorequires the addition of complex control circuitry. The outputenable function and common liD of the TMS4416alleviate the need for databus buffering further reducing thecircuit component count.The memory control timing is generated by dividing thedot clock with a 74S163 and using the appropriate outputsto clock several 74LS74s for proper placement of the memorycontrol signals. This approach may seem complicated,however it allows maximum flexibility in generating the controlsignals by the choice of the clock connections. The fallingedge of ALE takes RAS low, latches the memory addressesand enables the 74LS74s in the memory control circuitry(see Figure 2). On the next rising edge of2 xWCLK(edge A), MUX goes low switching the memory addressesfrom row to column via two 74S157s. The row addressescorrespond to 7220 addresses AD-O through AD-7 and thecolumn addresses correspond to AD-8 through AD-13. Thenext rising edge of clock A (edge B) takes CASffi low.CASSTB is then used in conjunction with AD-14 and AD-15to derive four CAS signals through a 74LS139 for easymemory expansion. It is necessary to select the memory withCAS instead of RAS, because the 7220 does not provide astatus indicating the type of memory operation to be performed(display, refresh, or RMW). (Normally RAS is used formemory selection to reduce system power consumption andnoise induced by RAS switching currents.) The rising edgeof clock C (edge C) after CAS, takes the memory outputenable (G) signal low. The G signal is controlled such thatit is only active on display and RMW cycles; for refreshcycles, IT is held high by the 7220 DBIN and BLANKsignals. Generating four CAS signals and a single G signalt:o.~COE ...o-.5ent:o.~CO.~Q.c.«9-31

uo!~ew"oJul suo!~ea!ldd"CD .,.., w745299ADDRESS LATCH ADDRESS MUX VIDEO DATA7 V5YNC11.34 MHzt--------4:> HSYNCFigure 1. TMS441617220 Interface

allows the use of multiple rows of memory since both CASand G have to be low for the TMS4416 outputs to be active(see TMS4416 operation, 1982 MOS Memory Data Book).The cycle is terminated by the rising edge of ALE (edge G).On RMW cycles, the 7220 uses the DBIN signal to gatedata from the memory onto the bus signifying the read operation.The rising edge of DBIN is then used to disable theG signal terminating the read portion of the cycle (seeFigure 3). The 7220 does not provide a separate write signalso the memory control circuit must use the presence of DB INto generate the write signal. This is accomplished by shiftingDBIN two clock C cycles (edge E) with two 74LS74s.Again the rising edge of ALE terminates the memory cycle(edge G).The 7220 runs at a relatively slow clock speed (1.4 MHz)in this design allowing the use of Low Power Schottky componentsfor most of the memory control circuitry. Thenecessary memory calculations given below show the actualmargins and also provide an easy means for determining themaximum speed of the design with Schottky components.The critical memory timings to be covered are: RASprecharge, row address setup and hold, CAS access, datavalid to write enable time and refresh interval.RAS Precharge TimetRP = tRW - tS(74LS08)where: tRW = ALE width (MIN, 7220 Spec.)ts = Skew between tpHL and tpLH, 74LS08thus: tRP = [113(705) -10) ns= 225 nsRow Address Setup TimetASR = 1I2(tCLK) - tAD - tpLH(74LS373)- tPLH(74S157) + tRF- tPHL(74LS08)where: tCLK = 2 x WCLK cycle timetAD = Address/data delay from 2 x CCLK(MAX, 7220 Spec.)tRF = ALE delay from 2 x CCLK (MIN, 7220Spec.)thus: tASR = [1/2(705) - 130 - 18 - 7.5 + 20+ 4) ns= 221 nsRow Address Hold TimetRAH = 1I2(tCLK) - tPHL(74LS08)+ tPLH(74LS74) + tPHL(74S157)thus: tRAH = [1/2(705) - 20 + 6 + 6) ns= 344.5 nsCAS Access TimeA. DisplaytCAC = 7(tDCLK) - tPLH(74S163)- tPHL(74LS74) - tPHL(74LS139)- tsu(74S299)where: tDCLK = Dot clock cycle timethus: tCAC = [7(88) - 15 - 40 - 33 - 7) ns= 521 nsB. RMW cyclestCAC = 5.5(tCLKA) - tPHL(74S04)- tPHL(74LS74) - tPHL(74LS139)- tOIswhere: tCLKA = Clock A cycletOIs = Input data setup to 2 x CCLK (MIN,7220 Spec)thus: tCAC = [5.5(176) - 5 - 40 - 33 - 40) ns= 850 nsData Valid to Write EnabletDS = 112 (tcLK) - tAD - tPLH(74S04)+ tPLH(74LS74)thus: tDS = [112(705) - 5 - 130 + 6) ns= 223.5 nsRefresh IntervalFor this circuit the least significant address lines correspondto the DRAM row addresses which are incrementedevery display cycle. This provides a refresh rate given by:Refresh Interval = (256/number of display words)x line time= (256/32) x 63.5 p.s= .5 msTherefore the memory is refreshed by normal displayaccesses and the 7220 refresh feature is not needed for thisdesign.A comparison of the previous calculations to the DRAMspecification indicates there are no memory speed restrictionsfor the design. To attain the maximum speed of thisparticuI'ar design, Schottky components may be substitutedand the appropriate parameters placed into the above equationsto determine the maximum dot clock frequency. By usinghigh performance logic, a dot clock rate of approximately22 MHz can be used.co.~~...E..... o.5enco.~~.~Q.c.«9-33

DOTCLOCKCLOCK ACLOCK C2 xWCLKRAS (ALE)MUXCASGLOAD--------------------------------------~--~Figure 2. Display And Refresh Cycle Timing»"C"2-(;'Q)...0'~en...~-t\o3Q)...•0'~2xWClKMUXA C o E GI I I I IFigure 3. RMW Cycle Timing9-34

The video output circuitry closely resembles that providedin the 7220 Design Manual. The major difference beingthe manner in which the 74S299 load pulse is generated.It was decided to use the ripple carry out of a 74S163 insteadof gating the clock outputs together. The CAS signalenables the 74S163 and six dot clocks later (edge F) the ripplecarry out will go high (see Figure 2) providing a videoload pulse at the end of the display cycle (edge G). Thisreduces hardware and provides an easy means for varyingthe position of the load pulse within the memory cycle ifnecessary. Some applications may require the video loadpulse to occur earlier in the display cycle which is accomplishedby changing the input strapping of the 74S163.A video load pulse will occur on every memory access;however, on refresh and RMW cycles, the display is blankedpreventing any disturbance of the display. Since the firstword of video information on each horizontal scan is not validuntil the end of the first display cycle, video unblanking mustbe delayed for one display cycle. This is accomplished byclocking the 7220 BLANK signal with the NAND result ofthe inverted dot clock and ripple carry out through a 74S74.The video is then synchronized with the dot clock and outputto the monitor. A 74LS123 is used to provide the properhorizontal and vertical drive signals to the monitor. Althoughthe 7220 can be programmed for the horizontal sync widthand the vertical sync width, some monitors require long drivetimes that can only be implemented with external logic.Providing the correct video information to the monitorrequires several calculations to determine the necessaryparameters that must be supplied to the 7220 upon initialization.The 7220 Design Manual goes through detailed calculationsfor determining these parameters when the designer isin the specification stage of a design. For this design themonitor specifications and dot clock rate were assumed andthe other parameters derived accordingly. The necessaryspecifications and calculations are given below.Horizontal frequency = 15.75 kHzVertical frequency = 60 HzHorizontal blanking = 11 p.s nominalVertical blanking = 900 p.s nominalDot clock = 11.34 MHz2 x WCLK = 1.42 MHz (Dot clocle/8)Word time = 1.41 p.s [2(1/2 xWCLK)1Line time = 63.5 p.s (lIHorizontal frequency)Pixel time = 88.18 ns (lIDot clock)From the line time and pixel time, the total number ofpixels per horizontal scan can be calculated.Pixels= tLINE/tPIXEL= 63.5 Its/88.18 ns= 720The total number of words per horizontal scan is givenby:WT = Pixels/16= 720116= 45(Since the 7220 uses a 16-bit word)The total word count is then divided between displayedwords and blanked words. For the monitor used, the onlyrestriction on the horizontal parameters is that the sum ofhorizontal front porch, back porch and sync be approximatelyequal to the nominal horizontal blanking time (11 its). Thehorizontal drive to the monitor is set by the 74LS123. Ahorizontal resolution of 512 pixels would require 32 displaywords and leave 13 words for horizontal blanking. SettingHorizontal Back Porch (HBP) = 5, Horizontal Front Porch(HFP) = 5, and Horizontal Sync (HS) = 3 meets all 7220constraints except for light pen use (requires HFP > 6words), and also satisfies the monitor horizontal blankingtime.Horizontal blank13 x 1.41 itS18.33 itSCalculations to determine the vertical blanking parametermust also be made.Total number of lines = (l/vertical frequency)/line time= (1160)/63.5 its= 262.3 (use 263)The total number of lines is also broken into active andblanked lines. In this application it was desired to neglectaspect ratios and display as much on the screen as possibleand stay within the monitor specifications. For this reason,it was decided to display 240 lines and blank 23 lines for512 x 240 noninterlaced and 512 x 480 interlaced displayresolution. Again the vertical drive is set by a 74LS123 andthere are no restrictions placed on the breakdown of the verticalblank parameters by the monitor or the 7220, allowingrandom division of the 23 blanked lines. The followingparameters were chosen: Vertical Back Porch (VBP) = 3lines, Vertical Front Porch (VFP) = 2 lines, and VerticalSync (VS) = 18 lines.Vertical blank = Blanked lines x one line time= 23 x63.5 itS= 1.46 msSeveral points of interest relating to the choice of thehorizontal and vertical parameters are given in the followingparagraphs.A. Dynamic RAM refresh, if necessary, is only done duringhorizontal and vertical sync which needs to be longenough to allow sufficient memory refresh.co'.;ICO... E.... o.Eenco'.;ICO,~Q.c.«9-35

B. If dynamic RAM refresh is enabled, then drawing can. only be done during front and back porch times. Thiscan degrade drawing time significantly if these times areshort.C. To maximize the drawing time and reduce wasted cycles,the horizontal parameters should be chosen in accordancewith memory refresh requirements. Whenmemory refresh is needed, the horizontal front and backporch parameters should be selected as multiples of 2word times (one RMW cycle equals 2 word times) ifpossible.Example: For HBP = 5, two RMW cycles (4 word times)would be performed and one cycle (1 word time)would be wasted. Choosing HBP'equal to fouror six eliminates the one wasted state. Of course,minimum 7220 requirements must be met also.These parameters can then be translated into a formatneeded to program'the 7220 (see Table II). Writing thesecommands and parameters to the correct 7220 address location(AO = 0, Parameter into FIFO; AO = 1, Commandinto FIFO) results in setting the video control commands,ends idle mode and unblanks the display. Upon initialization,the 7220 can then be programmed for drawing usingthe various graphics prhnatives. The 7220 Design Manualcontains numerous examples illustrating the necessary stepsfor drawing. To switch to 512 x480 interlaced modeparameter PI of the Reset command needs to be changedto IB hex (see Table II) and the Cursor and CharacterCharacteristics (CCHAR) command needs to be set appropriately(Blink Rate parameter greater than zero).The parameters for this design were choosen for norefresh operation and to support as many 7220 operatingmodes as possible. Table I gives a quick summary of thevideo parameters.Table I. Video ParametersParameter Value Parameter ValueActive Words 32 Active Lines 240Blanked Words 13 Blanked Lines 23HS 3 VS 18HBP 5 VBP 3HFP 5 VFP 2Table II. 7220 Initialization DataCommandsAnd Address AO Data (Hex) FunctionParametersReset ,1 00 Reset to idle stateP1 0 12*P2 0 1E Active words-2P3 0 42 HS-1, VS low bitsP4 0 12 VS high bits, HFP-1P5 0 04 H8P-1P6 0 02 VFPP7 0 FO Active display linesP8 0 OC V8PVSYNC 1 6F Master video syncSTART 1 68 End idle mode·Set for graphics mode, noninterlaced, no refresh, drawing during retrace only; for interlaced operation Pl =, IB (hex),9-36

To illustrate the drawing speed of the 7220, drawing timesfor arc and area fill routines with and without memory refreshwere measured. The 7220 also provides Flash Mode drawingwhere drawing is done during display and retrace. Whilethis yields extremely fast drawing times there is considerabledisturbance to the display when drawing is in progress. Thedrawing time results are shown in Table III.This Application Report has demonstrated how adesigner might incorporate the TMS4416 into a graphicssystem with the 7220. No attempt has been made to detailthe interface or communication between the host processorand the 7220 as so many variants exist (see 7220 DesignManual). The TMS4416 requires minimal circuitry togenerate a dense, low cost, high performance memory arrayfor the 7220.MOS MemoryApplications EngineeringTable III. Drawing TimesRoutine Pixels Drawn Refresh No Refresh Flash ModeArcRadius = 96 69 1,079 p,s 704 p,s 191.8 p,SArea Fillx = 400Y= 200 80,000 926:9 ms 686 ms 227.4 msc.;:;ocaE ..o""" .5enc.;:; oca.!:aQ.•Q.~9-37

•9-38

Applications BriefTMS4416/TMS4500A EVALUATION BOARDThis application note illustrates memory system implementation using the TMS4416/TMS4500A evaluationboard (Photo shown in Figure 1). The board measures 3" X 5.5" and is populated with a TMS4500A DRAMcontroller imd 16 TMS4416s (16K X 4 Dynamic RAMs); this system provides for 128K bytes of static appearingmemory and requires a single 5-volt supply. The interconnection bus at the board edge and the flexibility ofthe TMS4500A makes the board adaptive to almost any system. This board was developed by TexasInstruments to allow construction of several processor systems without redesign of the memory section for eachsystem. It is beyond the scope of this article to cover every microprocessor interface, although several popularmicroprocessor interfaces are covered in the TMS4500A User's Manual.co.~ca.. E.... o.5U)co.~ca.~C.c.•«FIGURE 1-TMS4416/TMS4500A EVALUATION BOARD9-39

The TMS4416/TMS4500A board is arranged as two rows of 8 devices (see Figure 2). Row 0 and Row 1 are selected bythe RASO and RAS1 sign,als, respectively. The board is then subdivided into four blocks of 32K bytes that are controlledby the WR1-WR4 and RD1-RD4 signals. The strapping of WR1-WR4 and RD1-RD4 allows the board to be configured as32K X 32 bits, 64K X 16 bits, or 128K X 8 bits. Table 1 shows the typical strapping needed for the various word widths.Several examples of how the WR and RD signals can be used will show the versatility of the TMS4416/TMS4500A board.BLOCK 0 BLOCK 1 BLOCK 2BLOCK 3TMS4500AUlTMS4416I I-' IRASO- I II I III IIU2 U3 U4 U5 U6 U7I I I--RASl-I I II I II I I- Ul0 Ull U12 U13 U14 U151 I' , I I 1 IWR2WR3U8U16IIIII •iIIIIU9U171 IWR4 RD4ROW 0ROW 1FIGURE 2 -TMS4416/TMS4500A BOARD lAYOUTTABLE 1 - READ AND WRITE SIGNAL STRAPPING CONFIGURATIONCONFIGURATION128K X 864K X 16SIGNAL STRAPPINGSWR1 = WR1, 'S"WR2 = WR2, 'S"WR3 = WR3. SWR4 = WR4SRD1 = RD1, SRD2 = RD2, SRi5'3 = RD3, SRD4 = RD4SWRl = WR1 = WR2. SWR2 = WR3 = WR4SRD1 = RD1 = RD2. SRD2 = RD3 = RD4TYPE OF CONTROLSeparate ControlCombined Pairs•NOTES:32K X 321. WRX = Write signal for any block.2. RDX = Read signal for any block.3, SWRX = User supplied system write signal.4. SRDX = User supplied system read signal."SWR1 = WR1 = WR2 =wib = WR4SRi5'1 = Ro1 = RD2 = RD3 = Ro4All CombinedThe REN1 input on the TMS4500A selects which row of devices is selected by controlling the RAS (Row Address Strobe)signals (REN1 low selects RASO, REN1 high selects RAS1). When a row of memory is accessed (RASO low or RAS1 lowl. allthe devices in that row are active which allows the user to manipulate each half-block within a row separately or collectively.As an example, strapping WR1-WR4 and RD1-RD4 for 64K X 16 operation as shown in Table 1 combines the 32-bit databus to form two 16-bit data busses that can be used in 16-bit systems as shown in Figure 3. The I/O function is controlled bythe combination of WR1-WR2, RD1-RD2 (Blocks 1 and 2) and WR3-WR4, RD3-RD4 (Blocks 3 and 4). It is then possible toread and/or write to each block by appropriate control of the WR and RD signals.9-40

TMS4500A BLOCKS 1 AND 2 BLOCKS 3 AND 4FIGURE 3 -64K X 16 CONFIGURATIONAnother example takes advantage of having a 32-bit word available but only an 8-bit data bus. To take advantage of this, a74LS139 selects the WR and RD signals and 00-07 of each block are tied together to form an 8-bit bus (See Figure 4). Awrite cycle enables 1 G allowing the 1 A and 1 B signals to select the block to be written to. A read cycle enables 2G allowingthe 2A and 2B signals to select which block will be read. On a read cycle, the 2A and 2B signals can be sequenced, causingsuccessive activation of the RD lines to rapidly access all 32 bits over the 8-bit bus (See Figure 5). This configuration makesfull use of the output enable (

RAS ~CAS \ I2AI \ I '-2BI '-iiD1Ro2Ro3Ro4DQ'----I'----I'----I'----II»"C'E..n'0)...0':::Ien5'~o...30)...0':::IBLOCK 1 BLOCK 2 BLOCK 3 BLOCK 4FIGURE 5 - FAST ACCESS READ TIMINGThe upgrade to next generation parts and expanded memory requirements are also taken into account on theTMS441 6/TMS4500A board. When 64K X 4 parts become available, they will be pin-compatible with the 16K X 4, allowingthe user to upgrade his board to 512K bytes of memory with no added interfacing. The TMS4416 disregards two of thecolumn addresses supplied to it from the TMS4500A (CAO, CA7) which are not needed to address its 16K of memory .These two extra address lines will be used to complete the addressing needed for the 64K X 4 making upgrade a matter of installingthe new devices .The TMS4416/TMS4500A memory board demonstrates the use of a versatile, and expandable memory suitable for mostany system.MOS MemoryApplications Engineering9-42

+5 VVCC16RAI1720RA22333RA326MA7 32RA4 MA6 2729RA5 MA5 2430RA6MA435214RA7MA3121923CAOMA21514CAlMAl1813CA2MAO22CA3 CAS 1025 TMS _~6CA428 4500ARASa14 CAS8 CA67 __RAslCA7csALEffi19 ECw111CLK39REFREOTWST,SO362~ ~~~_~~MAIMA2MA3MA4MAS1...----oMA6MAlilllIii.MAOMA2MA7"!:AsRAS1tB=f goo Cl la I"77 Cl-C15areO.l/4F 000 a a:: 3:+5 V78 47 .,111111111111111 146(Jewu..g g g gMAlMA2MA6MA7as-=0MA2MA3MA6MA7CAsilllc0'';:CO... E0.....Ernc0'';:CO,~C.C.«FIGURE 6 -TMS4416/TMS4500A BOARD SCHEMATIC9-43

9-44

TMS4500AALE AND ACX TIMINGThis application brief describes the timing diagrams for several configurations that can be achieved with theTMS4500A by controlling ALE and ACX. (ACX refers to either ACR or ACW.) Example timing diagrams are giventhat illustrate the pertinent edge timings of ALE and ACX and their impact on system timing requirements.The timing diagram given in Figure 1 shows ALE leading ACX. The falling edge of ALE latches the CS, REN1,RAO-RA7, and CAO-CA7 inputs (not shown in the diagram); if CS is valid, RAS will go low tAEL-REL after ALElow. ACX going low has two functions: the MAO-MA7 outputs are switched from the row addresses to thecolumn addresses, and CAS will go low when these addresses become valid. The access time of the TMS4500A(ALE low to CAS low) is specified as tAEL-CEL providing ACX goes low less than tAEL-CEL - tACL-CEL afterALE. If this condition is not met then the access time increases and CAS low is measured from the low-goingedge of ACX instead of ALE (tACL-CELl. The rising edge of ALE brings RAS high and causes the inputs at RAO-RA7to be output as addresses on MAO-MA 7. (Input latches for RAO-RA 7 are transparent latches.) The rising edgeof ACX brings CAS high and terminates the memory access cycle. The edge placements of ALE and ACX canvary from this example giving rise to RAS and CAS timings not explicitly shown in the MOS Memory Data Bookas explained below.Figure 2 illustrates the case where ALE overlaps ACX. In this case, the falling edges of ALE and ACX have thesame function as explained in the first example although the rising edges take on a little different function. Referringto. Figure 2, it can be seen that the rising edge of RAS, CAS, and the switching of MAO-MA 7 are controlledby the rising edge of ACX. The rising edge of ALE has no control in this example. Because ACX brings RAShigh, the precharge time (tRP) required by DRAMs is initiated from the rising edge of ACX and terminated bythe subsequent falling edge of ALE. This timing can be helpful in a system that cannot meet RAS prechargetime initiated from ALE.co'';:;COE ..o-.5U)co'';:;CO,~Q.c.

ALEACXRASMAO-MA7CASFIGURE 1 -ALE LEADING ACXALEACXRASMAO-MA7CASFIGURE 2- ALE OVERLAPPING ACXThe next example shows ACX prior to or coincident with ALE (see Figure 3). When ACX falls prior to or coincident withALE, the falling edges of RAS, CAS, and the switching of MAO-MA 7 are controlled by the falling edge of ALE. In this case,the TMS4500A provides several of the memory timing signals. First, the row address hold time (RAS low to MAO-MA7switching) is guaranteed to be a minimum of 30 ns (tREL-MAX); this value satisfies the row address hold times (tRAH)of TMS4164/TMS4416 (-15 and -20) DRAMs. Secondly, ALE low to CAS low (tAEL-CELI is within a guaranteed maximum.The rising edges of ALE and ACX have the same functions as described in the second example. In many applications, ALEand ACX can be tied together to take advantage of this "automatic timing feature" of the TMS4500A.Figure 4 illustrates the case where ACX overlaps ALE. In this case, the falling edges of ALE and ACX have the same functionas described in the third example: that is, ALE controlling RAS, CAS, and the switching of MAO-MA 7. The rising edgesof ALE and ACX have the same function as described in the first example: that is, ALE controlling RAS and the switchingof MAO-MA 7 while ACX controls CAS.9-46

ALEACXRASMAO-MA7CASFIGURE 3 -ACX PRIOR TO OR COINCIDENT WITH ALEALEACXRASMAO-MA7CASFIGURE 4 -ACX OVERLAPPING ALE.co'';:;m..E.... o.5tnCo'';:;m,saQ.c.

The ALE high to ClK low time is given by:tAEH-Cl = tRP - tw(Cl) - tCH-RRl + tAEH-REH + tt(REH)wheretAEH-Cl = ALE high to ClK lowtRP = memory precharge time (from DRAM spec.)tw(Cl) = ClK low timetCH-RRl = ClK high to refresh RAS starting low *tAEH-REH = ALE high to RAS starting hightt(REH) = RAS rise time*Multiply by a skew factor (0.9) because the maximum skew between starting high and starting low edgesare required.Given this equation, the timing of ALE call be obtained to meet the memory precharge times when operating the TMS4500Ain this mode.ClKALEACXl>"0'2..CrQ)r+O·::sen:r ....... o3Q)r+o·•::sREFREQRASMAXCASFIGURE 5 -REFRESH AFTER ACCESS (HIDDEN REFRESH)9-48

Figures 6 and 7 show how the edge timings of ALE and ACX described in the previous examples affect the RAS and CAStimings on access grant cycles. An access grant cycle occurs when ALE goes low during a refresh cycle. In this case thetiming of ALE low to ACX low determines the timing of RAS and CAS low with respect to ClK. If ACX falls more than20 ns after ALE during a refresh cycle, the TMS4500A will follow the timing shown in Figure 6. If ACX falls prior to orless than 2 ns after ALE during a refresh cycle, the TMS4500A will follow the timing shown in Figure 7. The differencebetween the two timing diagrams is the CAS timing with respect to ClK. On access grant cycles, the falling edge of ALEcauses the ROY signal to go low; ROY low is generally used to hold off the processor until the refresh cycle is complete.The refresh timings of RAS, CAS, and MAO-MA 7 are identical to the fifth example with respect to ClK edges A, B, C,and O. ClK edge E in Figures 6 and 7 terminates the refresh cycle and initiates the access grant cycle by bringing the ROYsignal high and the RAS signallow. 1 In Figure 6 (ACX falling more than 20 ns after ALE), the CAS signal is timed fromthe subsequent falling edge of ClK after the access grant cycle is initiated (ClK F) and will go low tCl-CEl later. In Figure 7(ACX falling prior to or less than 2 ns after ALE), the CAS signal is timed from the rising edge of ClK that initiated theaccess grant cycle (ClK E) and will go low tCH-CEl later. This diagram shows that CAS will fall approximately one-halfClK cycle earlier in Figure 7 than CAS in Figure 6; this timing arrangement decreases the access time after refresh. In bothof these access grant examples, the cycle is terminated by the low-to-high transition of ALE and ACx as described above.ClKALEACXRASMAO-MA7CASREFREQROYc00';:'CO.. E0'I-.5enc00';:'CO09C.~

ClKALEACXRASMAO-MA7CASREFREQROY• Timing of RDY for TWST = 1 is shown by dashed lines.FIGURE 7 -ACCESS GRANT (ACX PRIOR TO. COINCIDENT. OR OVERLAPPING ALE)~ The examples given have shown how the edge timings of ALE and ACX of the TMS4500A effect the Ms. CAS. and MAO-MA 7"E.. outputs. Table 1 provides a quick reference and summary showing which input controls which output(s) for the example(i" timing diagrams given in Figures 1 through 4.III....c" TABLE 1 - ALE AND AcX FUNCTIONS:::len.......5"c3III....0':lTIMING DIAGRAM RAS! RASI CASIFigure 1ALE leading ACXFigure 2ALE Overlapping ACXFigure 3ALEI ALEI ACXIALE! ACXI ACXIACX Prior To Or ALEI ACXI AlEICoincident With ALEFigure 4ACX Overlapping ALEALEI ALEI AlEISIGNAL TRANSITIONSCASIMAO-MA7ROW TO COL.ACTUATING SIGNALSACXIACXI-- ACXIACXIACXIACXIALE!ALEIMAO-MA7COL. TO ROWALEIACXI-- ACXIALEICASIACCESS GRANTSClKI (Fig. 6)ClKI (Fig. 6)ClK I (Fig. 7)ClKI (Fig. 7)Mos MemoryApplications EngineeringTexas Instruments assumes no responsibility for infringement of patents or rights of others based on Texas Instruments applications assistanceor product specifications, since TI does not possess full access to data concerning the use or applications of customer's products. TI also assumesno responsibility for customer product designs.9-50

Applications BriefTMS4500A DRAM CONTROLLER CONFIGURED FOR THETMS99000 SERIES 16-BIT MICROPROCESSORSThe TMS4500A dynamic RAM controller can be used in various configurations with TMS99000 series 16-bitmicroprocessors.' A medium-speed version and its timing diagram are shown in Figures 1 and 2, respectively.A high-speed version and its timing diagram are shown in Figures 3 and 4, respectively. Two memory configurationsare also shown: a bulk memory configuration and a modular array. The bulk memory configuration uses32 TMS4164 dynamic RAMs arranged as 128K of 16-bit words (see Figure 5). The modular memory array iscomprised of 16 TMS4416 16K X 4 dynamic RAMs arranged as 64K of 16-bit words (see Figure 6). The modulararray can be reduced in 16K word increments to a system that is 16K words deep for less memory-intensiveapplications. In addition, signals have also been provided to increase the memory depth to 128K words. In theparagraphs that follow, a description of both speed versions will precede a six-point analysis of the design criteriapresented in the "TMS4500A Dynamic RAM Controller Users Manual." Both versions will be analyzed to ensurea proper match of timing signals between processor and memory.The 15 address lines (AO-A 14) and Pm are latched by two 74S373 8-bit data la'tches as shown in Figure 1.2Latched addresses A 1-A4 are used to address three 16 X 4 bipolar RAMs in order to generate eight higher-ordermemory address lines. These RAMs are used as a memory mapping function to increase the memory space ofthe TMS99000. Four of the higher order address lines are decoded into chip selects for all memory-mappeddevices. On powerup and reset, the TMS99000 fetches the reset trap vector located at memory address OOOOH.Since PSEL is forced high for this fetch, the three memory-map RAMs are deselected, allowing their outputsto be pulled high by the 10k pullup resistors. This deselects the memory decoder and enables EPROM. Part ofthe reset service routine residing in EPROM should include instructions to load the memory mapper. The memorymapper is addressed using the 1/0 interface of the TMS99000 that has both serial and parallel bit manipulationcapabilities.Address lines A 1-A4 are used to address the memory-map RAMs. AO is set to a one for parallel 1/0 transfers(see TMS99000 Data Book). Additional 1/0 ports could be addressed by using the Y6 output (1/0 transfer) ofthe bus status decoder to enable an 110 decoder connected to the address latch outputs. Because of the largememory address space provided by the memory mapper, however, it was felt that all additional 1/0 ports couldbe memory-mapped.co.~COE...... o.5U)co.~CO.~Q.Q.~1 All references to the TMS99000 apply to both the TMS99105A and TMS99110A microprocessors.2 It should be noted that the TMS99000 uses the convention that AO to A 14 represent the most to least significant address bits. respectively.9-51

CDinN~1~12 MHzClKINClKOUTWE/iOclKRDREADY -AlATCHBSTlBST2IUO!leWJoj.ulABsuo!le:>!ldd'dY6I/O..-CLOCKWRiTEREADROYALE,:107TMS99105A/TMS99110ABST3P5El/0 15/0UT 16AO/OO/IN16C74lS138E G2AG2iiGl- f- El 10-80,mf?-8 15~ r--' DE P5El.Al~+ 5 V745373 10-808A7-AO10-80 ~ WPSIT. Al-A4 ... AO-A3 01A14-745373Q2A8Q38A7-AO ': 10-8004015-012 ;t:P 01-04745189011-08 __ 01-04f74518901Q2030410 kllAO--15.A14-AO....-..M5AM5BM5CM50M5EM5FM5GM5HM51EPiiOM"Cs745189Q1Q207-04 --c.- 01-04 OJ B04 CG2AAȲm-Yn ~ AOOl C57451387~~MEMR/W4 4 416 16+5V--Gl,...... G2BVx ~LIDRAM C5R/W015-00* See TextFIGURE 1 -TMS99105A/TMS99110A AND MEMORY MAPPING CIRCUITRY (3 MHz VERSION)

CLOCKACCESS REFRESH I ACCESS GRANT ACCESSALATCH,ALE ~~ ___....... n\-___________ ---Jn rROY, READY U \~ ________ ---J/ ~READ,WRITE =.J \\--..~.! \~---------'! \\..-_--....J!REFREQ\\--.._-~/A14-AO~~:~~~~:~~ ____________ -JX~ ______________________________________ ~X~ ____________ _DRAMCSBST1-3,'MEM,R/W --V VALID X VALID X VALID V-~~. ------~~------------------------~~---------~RAS\\..-...---J/ \~----.J/ \\--..----J{\ ICAS\~/ \~/ LfREAD DATAREAD DATADO-D15~--W-DA-R.!.;-f""'(-1"'

UO!leWJOJUI SUOlle:ludd"com~'~,i'74720 MHzCLKINCLKOUTWEIIOCLKiiDTMS99105A/TMS99110AREADY .:ALATCHB5T1B5T2B5T3PSEL/015/0UTAO/OO/INMEMR/W!:=74502+AY6BC 74L5138G2A/[o 0I/O745L04~G2B 0 0G1EL10-80PSEL.A 14-A8 16~05~ 74574t> (if-L...-..--~74L574A74502

~. ______________________ACCESS REFRESH ACCESS GRANTCLOCKALATCHALERDYREADY----READ.WRITEREFREQM~1~~~ ------~r_-----------------.r_------------------------------------------------,~-----.J~_T~________________________________________________ ,~ ____ _DRAMCSBST1-3.M:/~ ~~ _____________ ~X\' _________________________________________ X ...____CLOCKWRITEREADRAS\~ __ ~/ \~ __ ~r-\~ _____ ~LJ \ IDO-D1S--------~~;~---------{ ~!~~RDYALEA14-A5MSA-MSDMSE-MSGD15-DOFIGURE 4 --103TIMING DIAGRAM FOR TMS99105A OR TMS99110A AND TMS4500A INTERFACE 15 MHz VERSION)rTMS4S00AClKTMS4164_lx16)1 ...ACW RASO RAS -~- -~ACR CAS CAs-0-tt-tl .....RDY W Q ~~I>0Ior--_ALE ~C. 1:.10- REFREQ r--- AO-A7 i>oI.r--_RAO-RA7~~-'" r--FIGURE 5 -~See Text16~-TMS4500A AND 128K WORD DYNAMIC MEMORY USING TMS4164s--c::;:_ ~~-t:;:"C~ 16co.~COE~o8 A14-A7 i>oI.2 A6-AS~~,•CAO-CAl8 I>0Io -~4 -':.6 U- ~ __CA2-CAS2 MSE-MSFCA6-CA7 RASlRAs'lx16) 'M~'''_-_ ~ ~~MSG~~m Df-l~I----r RENl W Of- ~~ I-I-f-CS 8MAO-MA7".M ~ t-" ;~~~I-""'I-I->-_FSO FSl TWST16~~~~~~- ~~~~~"'=.-'to-..5f/)co.~CO.~Q.Q.«9-55

coen(J)CLOCKWRITEREADROYALEA14-A5MSA-MSOMSE,MSFMSGDRAMCS'R/W015-00- --8~10 T2 ...r2~,4,A14-A7• See Table 1 for Strap Configuration.I" UO!JewAoJul SUO!Je3!!ddy-..-- --_--A6-A5-..-..MSE-..~- -1.;~...TMS4500ATMS4416(x4) .... f--ClK RASo RAS ~ACW CAS CAs"ACRCAO N_C.ROYGCA7 N.C.ALE.. AO-A7REFREQ N.C. -8 If •RAO-RA7CA1-CA2CA3-CA6V;OQ1-0Q4 - :::: ~TMS4416(x4)---f--f-oRAS1 RAS ~CASREN1 W OQ1-0Q4.-I- ~CS MAO-MA7 ~118 GFSO FS1 TWST AO-A7-L, I I I ,L•*74lS155MSF 2YO ~.. A2Y1B2Y2FIGURE 6 -2Y31G1YO2G1Y11ClY22C1Y3'l ~} FOR EXPANS'ON Of_ .: ADD'l 64K WORDS16 ~-8r~L TMS4418,x4I-- ~RAS ~CAS- - WOQ1-0Q4 10- ~ ~P""- G.. AO-A7,.8 •I- I18TMS4500A AND 64K WORD OF MODULAR DYNAMIC MEMORY USING TMS4416sI- TMS4416(x4) f--f--RASf--~10- CASW OQ1-DQ4 ~ ~~ G~....- AO-A7--J~~

1. Refresh TimeTABLE 1 -STRAP CONFIGURATIONWAITSTRAP INPUT MODESSTATESCLOCKFOR MINIMUM CYCLESMEMORY REFRESH CLK FREQ. REFRESH FOR EACHTWST FS1 FSO ACCESS RATE IMHz) FREQ.lkHz) REFRES~l l Lt 0 EXTERNAL - REFREQ 4l l H 0 elK + 31 1,984 64 - 95t 3l H l 0 elK + 46 2,944 64 - 85t 3l H H 0 elK + 61 3,904 64 - 82§ 4H l l 1 elK + 46 2,944 64 - 85t 3H l H 1 elK + 61 3,904 64 - 80* 4H H l 1 elK + 76 4,864 64 -7H 4H H H 1 elK + 91 5,824 64 ~ 88+."4This strap configuration resets the Refresh TImer circui.try.Upper figure in refresh frequency is the frequency that is prodllced if the minimum elK frequency of the next select state is Ilsed.Refresh frequency if ClK frequency is 5 MHz.+ Refresh frequency if ClK frequency is 8 MHz.From Table 1 of the TMS4500A data sheet, there are two strap selections that would be appropriate for a 3 MHz clockfrequency. One selection inserts a wait state on every memory access while the other does not. Assuming that no waitstates will be necessary, select the strap input: FSO = TWST = 0 and FS1 = 1. This will yield a refresh rate of (3 MHz)/46or approximately 65 kHz. Each refresh will take 3 clock cycles.2. Memory Precharge Time (RAS precharge)The memory precharge time must be calculated for access, refresh, and access grant memory cycles to ensure the minimumRAS precharge time is satisfied.a. Access CyclesThe precharge time on access cycles is given by:wheretRPtRPtc2td1tc2/4+td1 +tAEL-REL* - td7 - tACH-REH - tt(REH)RAS precharge timeCLKOUT periodDelay from ALATCH low from reference line (ry1AX,99000 Spec.)tc2/4 + 10co"';::mE~~.5enco"~CJ=&c.~thustAEL-RELtd7tACH-REHtt(REH)tRPTime delay, ALE low to RAS starting low (MAX, 4500A-20 Spec. *)WE, AD control release delay (MAX, 99000 Spec.)Time delay, ACX high to RAS starting high (MAX, 4500A-20 Spec.)RAS rise time (MAX, 4500A-20 Spec.)(333/4 + 333/4 + 10 + 36 - 30 - 40 - 20) ns123 ns RAs precharge time.This value should otherwise be a minimum value; however as all propagation delays on a given chip will tend to track each other, the maximumvalue is multiplied by a skew factor to reflect variations in same-chip propagation delays. The skew factor used here is 0.9. AU values (followedby an asterisk) are obtained by multiplying the specified maximum value by 0.9.9-57

. Access Grant CyclesThe precharge time for access grant cycles is given by:wherethustRPtCH-REltCH-RRHtRPtc2 + tCH-REl * - tCH-RRH - tt(REH)Time delay, ClK high to access RAS starting low (MAX, 4500A-20 Spec. *)Time delay, ClK high to refresh RAS starting high (MAX, 4500A-20 Spec.)(333 + 63 - 45 - 20) ns = 331 ns RAS precharge timec. Refresh CyclesThe precharge time for refresh cycles is given by:wherethustRPtCH-RRltRP1.5 (tc2) + tCH-RRl * - td7 - tACH-REH - tt(REH)Time delay, ClK high to refresh RAS starting low (MAX, 4500A-20 Spec. *)[1.5(333) + 54 - 30 - 40 - 20] ns = 464 ns RAS precharge time3. ALE to elK RelationshipALE low transition must not occur within 10 ns of the ClK low transition. Since the TMS99000 strobes ALATCH Iowanthe rising CLKOUT edge, this criterion is satisfied.4. Row Address Setup and Hold Timesl>'C"2-C;"Q)r+o·:;:,en;--h0~3o·Q)r+•:;:,The row address, column address, REN 1 and CS inputs must all be set up and stable no later than 10 ns prior to the fallingedge of ALE. The latest of these signals will be CS which must propagate through all of the memory decode logic. Therow address setup time for the 4500A then is given by:wherethustAV-AEltAV-AEltd2t w H3td3t p('S373)t p('S189)t p('S138)tAV-AELtd2 * + twH3 - td3 - t p('S373) - t p('S189) - t p('S138)Setup time, row, column, REN1, CS valid to ALE starting low (MIN, 4500A-20Spec.)Delay to ALATCH high from reference line (MAX, 99000 Spec. *)ALATCH pulse width high (MIN, 99000 Spec.)Delay to address valid from reference line (MAX, 99000 Spec.)Propagation delay, data input to output (MAX, 74S373 Spec.)Propagation delay, address input to output (MAX, 74S189 Spec.)Propagation delay, select input to output (MAX, 74S138 Spec.)[13.5 + (333/4 - 15) - 15 - 13 - 35 - 12] ns6.8 ns setup time from CS to ALE starting low.The setup time from row address valid (at the DRAMs) to RAS starting low must also be considered. This is given by:wheretsu(AR)t§u(AR)td1tAEL-REltd3td1 + tAEl-REl * - td3 - t p('S373) - t p('S189) - tRAV-MAVSetup time, row address valid to RAS starting lowDelay to AlATCH low from reference line (MIN, 99000 Spec.)Time delay, ALE low to RAS starting low (MAX, 4500A-20 Spec. *)Delay to address valid from reference line (MAX, 99000 Spec.)• Multiply the specified maximum value by 0.9.9-58

thust p('S373)tp('S189)tRAV-MAVtsu(AR)Propagation delay, data input to output (MAX, 74S373 Spec.)Propagation delay, address input to output (MAX, 74S189 Spec.)Time delay, row address valid to memory address valid (MAX, 4500A-20 Spec.)[(333/4 + 10) + 36 - 15 - 13 - 35 - 55) ns16 ns row address setup time for the DRAMs.The row address hold time is guaranteed by the TMS4500A for -12, -15, and - 20 speed range devices.5. Data Valid to Write EnableSince CAS is initiated by the write enable signal, all write cycles are necessarily early write cycles. Therefore, we will calculatethe setup time for data valid to CAS starting low which is given by:wherethustsu(D)tsu(D)tAEL-CELtd9td1td8tsu(D)tAEL-CEL + td9 - td1 - td8Setup time, write data valid to CAS starting lowTime delay, ALE low to CAS starting low (MIN, 4500A-20 Spec.)Delay to WE from reference line (MAX, 99000 Spec. *)Delay to ALATCH low from reference line (MAX, 99000 Spec.)Delay from ALATCH low to valid write data (MAX, 99000 Spec.)[75 + (333/4 + -18) - (333/4 + 20) - 35) ns38 ns setup time from data valid to CAS starting low.6. Read Access TimeThe maximum access time allowable from CAS to data valid on memory read cycles is given by:talC)tc2 - tc2/4 - td1 - tAEL-CEL - tsu2where talC)tc2tc2/4td1tAEL-CELtt(CEL)tsu2Access time from CAS to data validCLKOUT periodDelay from CLKOUT falling to reference line (99000 Spec.)Delay from reference line to ALATCH low (MAX, 99000 Spec.)Time delay, ALE low to CAS starting low (MAX, 4500A-20 Spec.)CAS fall time (MAX, 4500A-20 Spec.)Data setup time (to CLKOUT falling) (MIN, 99000 Spec.)thus talC) [333 - 333/4 - (333/4 + 20) + 20) - 200 - 25 - 25) nsco.~COE....-o.5tJ)co.~CO.~Q.c.~'. ... = . -1~3 ~s. . . d b d •Now that the SIX specifications on the deSign criteria checklist have been examined, the values obtalne can e compareto those required for the TMS4164. This comparison shows that three criteria constrain design and memory selection. Thesecriteria are RAS precharge, CS valid to ALE starting low, and read access from CAS. The RAS precharge time of 123 nsmeans that only -20, -15, or -12 speed range devices may be used. Next, 3.2 ns of delay must be added to the ALEsignal to ensure that CS is valid 10 ns before ALE starts low. This delay is achieved by inserting a buffer between ALATCHand ALE. Finally, a negative access time from CAS requires that a wait state must be inserted on each memory accesscycle. By adding one CLKOUT period (set TWST = 1, FSO = FS 1 = 0) to the calculated memory access requirement,the read access cycle time (from CAS) with one wait state inserted is given by:• Multiply the specified maximum value by 0.9.9-59

whereta(C)tp(BFR)(-103 + tc2 - tp(BFR)) nsBuffer propagation delay, input to output of the ALE buffer. (MAX, Spec.)Using the worst case CAs access time for TMS4164-15 DRAMs (ta(c) = 100 ns), the maximum allowable propagationdelay for the buffer can be determined:tp(BFR)(-103 + tc2 + talc)) ns(-103 + 333 -100) ns130 nsThis value must be greater than the maximum propagation delay for the ALE buffer.The specifications for the high-speed version will be evaluated next. In this version, ALE is extended to meet the RAS prechargerequirement for -15 devices. This also gives sufficient address setup time to use the 74LS61 0 memory mapper. The memorymapper performs essentially the same function as the bipolar RAM array in the previous example, but incorporates the controlsignals that are necessary on-chip. For more information regarding the 74LS610, refer to TI Application Brief entitled"Memory Mapping Using the SN54/74LS610 Thru SN54/74LS613 Memory Mapper." For the following example, assumethat the TMS99000 has an input CLKIN frequency of 20 MHz (CLKOUT = 5 MHz).1. Refresh TimeFrom Table 1 of the TMS4500A data sheet, the strap selection should be FSO = 0, FS1 = TWST = 1. This will yielda refresh rate of 66 MHz and each refresh cycle will take 4 clock cycles. Also, the TMS4500A will insert one wait stateon each access cycle. As was mentioned earlier, the external logic will insert two wait states on each access cycle withthe assistance of the RDY signal from the TMS4500A.2. Memory Precharge Time (RAS precharge)l>~"2-c;'Dl...O·::len:;-......03Dl...•o·:;,a. Access CyclesThe precharge time on access cycles is given by:b.c.wherethustc2~p('LS04)t p('S74)tRPAccess Grant CyclesthusRefresh Cyclesthustc2 + tp('LS04) + t p('S74) + tAEL-REL * - td7 - tACH-REH - tt(REH)200 nsPropagation delay, input to output (MIN, 74LS04 Spec.)Propagation delay, clock to Q output (MIN, 74S74 Spec.)(200 + 6 + 4 + 36 - 30 - 40 - 20)ns156 ns RAS precharge time .tc2 = tCH-REL * - tCH-RRH - tt(REH)(200 + 63 - 45 - 20) ns198 ns RAS precharge time.1 .5[tc2) + tCH-RRL * - td7 - tACH-REH - tt(REH)[1.5(200) + 54 - 30 - 40 - 20) ns264 ns RAS precharge time.3. ALE to eLK RelationshipAs mentioned previously, a schottky flip-flop and low-power schottky inverter are used to clock ALE so that a minimumof 10 ns delay is guaranteed from CLK low to ALE low.• Multiply the specified maximum value by 0.9.9-60

4. Row Address Setup and Hold TimesthustAV-AELtAV-AELtc2 + t p('LS04) + t p('S74) - tc2/4 - td3 - tAVQV1(200 + 6 + 4 - 50 - 15 - 70) ns75 ns setup time from CS to ALE starting low.Also,thustsu(AR)tsu(AR)tc2 + t p('LS04) + t p('S74) + tAEL-REL * - tc2/4 - td3 - tAVQV1 -tRAV-MAV(200 + 6 + 4 + 36 - 50 - 15 - 70 - 50) ns61 ns row address setup time for the DRAMs.5. Data Valid to Write EnableSince data is valid before ALE falls, the data setup time is guaranteed.6. Read Access TimeAssuming two wait states are generated for each access cycle:thusta(C)ta(C)2[tc2] - t p('LS04)t - t p('S74)t - tAEL-CEL - tt(CEL) - tsu2t Maximum values are used for propagation delays t p('LS04) and tp ('S74) tosatisfy worst-case design requirements.[2(200) - 15 - 9 - 200 - 20 - 25] ns131 ns read access time from CAS.The previous calculations indicate that RAS precharge and read access requirements will constrain memory selection.TMS4164-25 devices will not be able to meet either the RAS precharge time (tw(RH) = 150 ns) or the read access time(ta(C) = 165 ns). TMS4164-20 devices cannot meet the read access time (ta(C) = 135 ns); however, TMS4164-15 devicesmeet all timing requirements.Now that the 128K word memory using TMS4164s has been analyzed, a brief description of a 64K word memory usingTMS4416s will be given. The major difference between the two memory configurations lies in the addition of a 7 4LS 155used as a one-of-four selector (see Figure 6). The R/W line from the TMS99000 is used to select whether the upcomingaccess is to be a read or write cycle. MSF selects either the left or right bank of memory while MSE selects either the upperor lower bank. Thus, only one of the four banks of 16K word memories will be accessed on any given mefTlory cycle. Becauseall of the inputs to the 74LS155 are set up before the start of each DRAM access (ALE starting lowl. there are no timingconstraints when using TMS4416-20 or TMS4416-15 devices.Two memory system configurations have been presented showing how the TMS4500A can be configured to work withthe TMS99000 16-bit microprocessor. A memory mapping scheme has been provided that is flexible enough to work withmany microcomputer applications using the TMS99000 without modification. Although both expandability and modularityhave been considered in this design, other memory mapping schemes and processor speeds are possible .Mos MemoryApplications Engineeringco";:;CO...E.... o.5enco";:;CO"~Q.c.•

•9-62

Applications BriefTMS4500A/8088 INTERFACEThis application brief presents a circuit configuration which interfaces the 8088 microprocessor to dynamic RAMmemory via the TMS4500A-15 dynamic RAM controller. The memory array is 32K bytes deep and featuresthe TMS4416 16K X 4 dynamic RAM. The TMS4416 was used for its modularity advantage over X 1 DRAMs.Figure 1 shows the schematic diagram of the circuit while Figure 2 depicts the timing diagram of a write accessfollowed by a refresh followed by a read access grant memory cycle. The 8088 and TMS4500A both operateat 5 MHz requiring no wait states on normal memory accesses. The TMS4500A clock is shifted by one 15 MHzclock cycle via a 74S74 to ensure the proper ALE low to ClK low relationship to the TMS4500A. In order tocover the important TMS4500A interface requirements, the six-point design criteria will be used as presentedin the "TMS4500A Dynamic RAM Controller Users Manual."1 . Refresh TimeThe TMS4500A is configured for maximum division of the clock without inserting wait states by strapping TWST,FS1, and FSO as follows: TWST = 0, FS1 = 1 and FSO = 1.This strap configuration divides the clock by 61 to yield a refresh rate of 3.123 ms (see TMS4500A Spec.).2. Memory Pre charge timeThe memory precharge time must be calculated for consecutive access, refresh, and access grant cycles toensure that the minimum RAS precharge time is satisfied.a. Access CyclesThe precharge time for access cycles is given by:wheretRPTClClTClCl + TClCH - TClRH - tACH-REH - tt(REH) + TCHll+ tAEl-REl *RAS precharge timeClK cycle periodc:o'';::COE...o'too..5(I)c:o'';::CO,~Q.c.•

tt(REH)TCHLLtAEL-RELRAS rise time (MAX TMS4500A-15 Spec.)ALE inactive delay (MAX 8088 Spec.)Time delay, ALE low to RAS starting low (MAX TMS4500A-15Spec. *)thus,(200 + 118 - 150 - 30 - 15 + 85 + 27) ns235 ns*This value should otherwise be a minimum value; however, as all propagation delays on a given chip will tendto track each other, the maximum value is multiplied by a skew factor to reflect variations in same chip propagationdelays. The skew factor for the TMS4500A is 0.9. All values follow by an asterisk are obtained bymultiplying the specified maximum value by 0.9.5100IROY -,..---LMN/MX ADO·AD7ALE ALE CAs enDQ4A8·A1386~RAO·RA7 MAO· AO·A7CA1-CA6 MA7 cr TMS4416A17TMS4416CS101MIA16RENIFA -4,AD RASlRAS DQ1·WR ACW-- en DQ48088TMS4500A '-- AO·A7OQ4GW TM~16TMS441615MHZ5 Xl ~D Qr-8284A ~ 74S74T X2 OSC I--- ~CREADY ClK5100I 1 lS04----T+5V READY ClK ClK ROY RASO RAS DQ1·':'"81-WL4,DQ1.~DQ4DQ1'~•FIGURE 1 - TMS4500A/8088 INTERFACE SCHEMATIC9-64

WRITE 1::3 REFRESH t ACCESS GRANT READ---c::JClK (SOSS)ALE' r--\. rACW \ ,ACR \ ,RAS , ,-- --\ r \ ICAS \ ,- -, IROY~ d• •READY ~ ~--ADDRESS!DATA BUS AD7·ADO A DATA FROM CPU A AD7·ADOREFREO\ Icoa,01IApplicationsInformationFIGURE 2 - TIMING.DlAGRAM

. Refresh CyclesOn refresh cycles the minimum precharge time occurs when ACR or ACW go high 20 ns before TMS4500AClK low. If this occurs, refresh RAS will go Iowan the subsequent rising edge of the TMS4500A ClK.The minimum precharge time for refresh cycles is. given by:wherethus,tRPtACH-CltACH-REHtCH-RRlTClCH + tACH-Cl - tACH-REH - tt(REH) + tCH-RRl *Time delay ACX high to ClK low (MIN TMS4500A-15 Spec.)Time delay, ACX to RAS starting high (MAX TMS4500A-15Spec.)Time delay, ClK high till refresh RAS starting low (MAXTMS4500A-15 Spec. *)(118 + 20 - 30 - 15 + 45) ns138 nsc. Access Grant CyclesThe pre charge time for access grant cycles is given by:wheretRPtCH-RRHtCH-RElTClCl - tCH-RRH - tt(REH) :t tCH-REl *Time delay, ClK high to refresh RAs starting high (MAXTMS4500A-15 Spec.)Time delay, ClK high to access RAS starting low (MAXTMS4500A-15 Spec. *)l>'C"2.c;'Ell...S':::Ien5'....... o3OJ...•ci':::sthus,3. ALE to elK Relationship(200 - 35 - 15 + 54) ns204 nsThe ALE low transition must not occur within 10 ns of the TMS4500A ClK low transition. This is guaranteedby the phase shift between the 8088 and TMS4500A clocks.ALE low to ClK low time is given by:wherethustAEl-CltosctOlCHtp04tp74tAEl-Cl2(toSC) - !OlCH - TCHll + tp04 + tp74OSC cycle period (8284A Spec.)'OSC low to ClK high (MAX 8284A Spec.)Propagation delay, MSI gate (MIN 74lS04 Spec.)Propagation delay, MSI gate (MIN 74S74 Spec.)[2(66) - 22 - 85 + 5 + 41 ns34 ns4. Row Address Setup and Hold TimeThe setup time to the TMS4500A is given by:wheretAV-AEltAV-AElTAVAl - tp32Time delay, address, REN1, CS valid to ALE low (MINTMS4500A-15 Spec.)9-66

TAVAlAddress valid t~ ALE low (TClCH -60, MIN 8088 Spec.)thus,tp32tAV-AElPropagation delay, SSI gate, allowing for delay to CS(MAX 74lS32 Spec.)(118 - 60 - 22)ns36 nsThe row address setup time to the DRAMs is given by:wherethus,tASRtRAV-MAVtASRTAVAl - tRAV-MAV + tAEl-REl *Time delay, row address valid to memory address valid (MAXTMS4500A-15 Spec.)(118 - 60 - 40 + 27) ns45 ns5. Data Valid to Write EnableAll writes to memory are early writes, which allows data to be set up to CAS instead of W. The 8088 specifiesthat the data is valid a minimum of 0 ns to WR low. This gives a data setup time equal to tACL-CEl (50 nsMIN) for this circuit.6. Read Access time from CASThe required access tittle for both access and access grant memory cycles must be calculated.The read access time from CAS on normal access cycles is given by:wherethustCACtCACTClRltACl-CEltt(CEl)TDVCltCAC2(TClCl) - TClRl - tACl-CEl - tt(CEl) - TDVClAccess time from CASRD active delay (MAX 8088 Spec.)Time delay, ACX low to CAS starting low (MAX TMS4500A-15Spec.)CAS fall time (MAX TMS4500A-15 Spec.)Data valid delay (MIN 8088 Spec.)[2(200) - 165 - 90 - 15 - 30] ns100 nsThe'read access time on access grant cycles is given by:wheretCACTCHCltCH-CEl2(TClCl) + TCHCl - tCH-CEl - tt(CEl) - TDVClClK high time (113 TClCl + 2, MIN 8284A Spec.lTime delay, ClK high to access CAS starting low (MAXTMS4500A-15 Spec.)co"+::COE ....... o.5enco-.+:;CO"~Q.•Co

wherethus,fCLKfCLKtCACfCLK[1/2 (tCAC + TCLRL + tACL-CEL + tt(CEL) + TDVCU]-l X109Maximum 8088 clock frequencyCAS access time (MIN TMS4416-20 Spec.)[1/2 (120 + 165 + 90 + 15 + 30)] ns4.762 MHzA circuit configuration to interface dynamic memories to the 8088 microprocessor utilizing the TMS4500Adynamic RAM controller has been presented. The circuit design featured a 5 MHz 8088 interfaced to aTMS4500A-15 operating with no wait states. The memory array was implemented with TMS4416 dynamicRAMs for increased modularity.MOS MemoryApplications Engineering•Texas Instruments reserves the right to make changes at any time in order to improve design and to supply the best product possible.Texas Instruments assumes no responsibility for infringement of patents or rights of others based on Texas Instruments applications assistance or productspecifications, since TI does not possess full access to data concerning the use or applications of customer's products. TI also assumes no responsibilityfor customer product designs.9-68

Applications BriefTMS4500A/MC68000 INTERFACEThis application note provides several circuit configurations interfacing three speed rangesof the MC68000 microprocessor to dynamic RAM memory via the TMS4500A-15 dynamicRAM controller. The MC68000L6 operates with no wait states while the MC68000L8 andMC68000L 10 operate with one wait on normal memory access cycles. The memory arrayis organized as 32K words featuring the TMS4416 16K x 4 dynamic RAM arranged as tworows of 16K x 16 bits with each. row partitioned into 16K bytes of upper and 16K byteslower memory. The TMS4416 was used for its modularity advantage over X 1 DRAMs andupgradability to future 64K x 4 devices.Two approaches for controlling access to the upper and lower bytes of memory are given.The first approach (Figure 1 A) controls access to upper and lower memory by gating CASwith UDS and LDS providing an early write condition. Early write occurs when the W signalto the DRAM goes low prior to CAS low. Under this condition the data input to the DRAMis req'uired to be set up prior to CAS instead of prior to W, and the output buffers are disabledallowing the use of common I/O. This can be achieved on the TMS4164 by tying Dand Q together; the TMS4416 is a common I/O device. The second approach (Figure 2A)controls access to upper and lower memory by gating R/W with UDS and LDS providinga late write condition (CAS low prior to W low). There are definite advantages and disadvantagesto each of the implementations. From a system standpoint the gated CAS requiresa smaller number of gates than the gated R/W version but would degrade CAS access timewith the extra SSI gate (74LS32) delay. Another system criteria would be the choice ofmemory used with each implementation. For the gated CAS approach both TMS4416s andTMS4164s could be used with common I/O reducing layout signal routing complexity. Thegated R/W implementation restricts the use of common I/O when using TMS4164s due tolate write operation. In the late write cycle the Q outputs will go to an active state causingcontention between the processor and the memory for the data bus. To use TMS4164s withinthe gated R/W system requires that the Q outputs be externally buffered to allow a bidirectionaldata bus which adds extra circuitry for the buffers. The timing diagrams for Figures1 A and 2A are given in Figure 1 Band 2B, respectively.co0';:;m... Eo~.EU)co0';:;mo~C.c.«Both methods of upper and lower byte control allow the use of read-modify-write (TAS instruction)cycles but the operational response of the DRAMs is ~lightly different. A readmodify-writeis performed by first reading the data from a memory I~cation then writing databack to that location in the same memory cycle. The TAS instrJction (Test and Set anOperand) tests a byte bperand and sets the negative and zero flag~aCCOrdingIY; the highorder bit of the operand is set. This provides a means of sync ronization in multipleprocessor environments. Figure 3 shows the read-modify-write timi ~s for the gated CASand gated R/W implementations. The two methods for controlling memory access have theadvantages and disadvantages mentioned above plus another difference on read-modifywritecycles. The gated CAS approach actually does a page mode read then a page modewrite (two CAS cycles for a single RAS cycle) to the same memory location while the gated9-69

R/W approach does a normal read-modify-write to the DRAM. The choice of these methods wouldprobably be determined by other factors in the system design; particularly the size of the memoryarray since the TMS4416 example would require less logic to implement but lends itself better tosmaller memory designs.The DTACK signal is derived by ANDing UDS, LOS, and R/W together, clocking ROY with a flip-flopand then DRing the two results. On normal accesses the ROY signal is high allowing either the UDS,LOS, o~' R/W signal to force DT ACK low. On access grant cycles the low ROY signal holds DT ACKhigh one clock period after the refresh cycle is complete. UDS, LOS and R/W are ANDed togetherso that on read cycles UDS and/or LOS force DT ACK low and on write cycles R/W forces DT ACKlow. This gating is necessary because UDS and LOS go low too late in the write cycle to provide sufficientDTACK setup time. It also provides the two DTACK pulses for read-modify-write cycles. Forthe MC68000L8/L 10 design DTACK is delayed with a flip-flop to provide one wait state.6 MHzCLK T ICLK+5V- _CLK_ RAS001- 4ACW RASO004AS ALE AO-A7~MC68000L6 L ill :---W48001-A1-A8 RAO-RA7 - CAS D046A9-A14CA1-CA6 ~ -G ~TMS4416A15CAO*001- 4MAO-004A16CA7*I~ASMA7 ~-A17 REN1 IG TMS4416 -001- 400400-015A18 csT I~ODS TMS4500A GLOS - ROY 19M54416CASR/W CAS RAS1,0DTA'Ci

ClKAlE,ACR,--UDS,lDSt-WRITEIREFRESH __.......1. __ ACCESS GRANT ....,,- (READ) -I~ ____________ ~r--R/WRASCAS (4500A).CAs (DRAM)REFREQRDYDTACK\\,I'---__---oJ II '~_-.JI ~FIGURE 1B - TIMING DIAGRAM (GATED CAS)co"';:;o~.5enco"';:;CO"~Q.Co«9-71

II(0~""6 MHzI UO!leWJO,ulSUo!le:l!lddvCLK T LCLK__ CLKRASOQ1- 4+5V- ACW RASO- .- OQ4ASALECASf---MC68000L6 1- ACR AO-A7 OQ1-8 ~A1-A8L RAO-RA7 - G OQ46A9-A14, CA1-CA6W TMS4416 ŌQ1-A15REN1IGA16CSMAO-OQ4MA7 H~A17 CAO* W TMS4416 OQ1-A18CA7*OQ4CAS I~UOSf--~TMS4500AL W TMS4416LOS r-- ROYIt)IGRAS1CR/W I-e I W TMS4416OTACKc6 ~~410-}OQ1- 4 ....- '-- RASOQ4CAS)AO-A7 --- OQ1-~ G ·OQ4LV'\.~~ ,~W TMS4416 OQ1-GOQ4-~ w ~TMS4416 OQ1-74LS32 IG OQ4+5V-f--'-->CKo CLR I-IG74LS74 li ~ 1-I WI WTMS4416TMS4416~'\.,16" I'See text.FIGURE 2A - TMS4500A/MC68000L6 INTERFACE SCHEMATIC (GATED R/Wi

ClKWRITE REFRESH _I_ ACCESS GRANT .,,- (READ)AlE,ACR\ / \ rUDS,LoSR/WRASCASGWREFREQ\ /c0RDY\ /DTACK\ / \ (FIGURE 2B - TIMING DIAGRAM (GATED R/Wi C.C.

ClKAlE.ACR\ ,----\,\ ,----R/W\ ,----DTACK\ I \ ,--CAS\ I L.F\ I L.F\ ,----}GATEDffiCASW\~------------------~,--,-----,FIGURE 3 -READ-MODIFY-WRITE CYCLE TIMINGTo cover the important aspects of the MC68000/TMS4500A interface, detailed calculations of thedesign criteria for the MC68000L6 and MC68000L 10 will be given with only a short summary ofthe MC68000L8 design criteria. The results will then be compared with the TMS4416 and TMS4164DRAM timing requirements to provide proper memory speed selections. Finally the designs will beweighed against each other to point out the strengths and weaknesses as related to systemperformance.The six-point criteria will be used as presented in the "TMS4500A Dynamic RAM Controller UsersManual" in the following calculations.MC68000L6 Design Calculations1. Refresh intervalThe TMS4500A is configured for maximum division of the clock without inserting wait states by strappingTWST, FS1, and FSO as follows_TWST = 0, FS1 = 1, FSO = 1This strap configuration divides the clock by 61 to yeild a refresh interval of 2.60 ms (see 4500A Spec.).9-74

2. Memory precharge timeThe memory precharge time must be calculated for consecutive access, refresh, and access grantcycles to ensure that the minimum RAS precharge time is satisfied.a. Access cyclesThe precharge time for access cycles is given by:tRP tSH - tAEH-REH - tt(REH) + tAEl-REl *where tRP RAS precharge timetSH = AS,OS width high (MIN MC68000l6 Spec.)tAEH-REH = Time delay, ALE high to RAS starting high (MAX 4500A-15 Spec.)tAEl-REl * = Time delay, ALE low to RAS starting low (MAX 4500A-15 Spec.)thus,tRP (180 - 25 - 15 + 27) ns= 167 nsb. Refresh cyclesThe minimum precharge time for refresh cycles is given by:tRP = 1.5(T) - tClSH - tAEH-REH - tt(REH) + tCH-RRl *whereT = Clock cycle timetClSH = Clock low to AS, OS high (MAX MC68000l6 Spec.)tCH-RRl * = Time delay, ClK high to refresh RAS starting low (MAX 4500A-15 Spec. *)thus, tRP = [1.5(166) - 75 - 25 - 15 + 45] ns= 179 nsc. Access grant cyclesThe precharge time for access grant cycles is given by:tRP = T - tCH-RRH - tt(REH) + tCH-REl *where tCH-RRH = Time delay, ClK high to refresh RAS starting high (MAX 4500A-15 Spec.)tCH-REl * = Time delay, ClK high to access RAS starting low (MAX 4500A-15 Spec. *)thus, tRP (166 - 35 - 15 + 54) ns170 ns3. ALE to ClK relationshipc:o'';::;coE ....... o.5(I)c:o'';::;co,~C.c.~The ALE low transition must not occur within 10 ns of the ClK low transition.ALE low to ClK low time is given by:tAEl-Cl = .5(T) -tCHSlxwheretCHSlx = Clock high to AS, OS low (MAX, MC68000l6 Spec.)thus tAEl-Cl [.5(166) - 65] ns18 ns• This value should otherwise be a minimum; however as all propagation delays on a given chip will tend to track each other, the maximum value is multipliedby a skew factor to reflect variations in same chip propagation delays. The skew factor for the TMS4500A is 0.9. All values followed by an asterisk areobtained by multiplying the specified maximum value by 0.9.9-75

4. Row address setup and hold timeThe row address setup time to the TMS4500A is guaranteed by the MC68000L6 address valid toAS low timing (tAVSU.tAV-AEL = tAVSL = 35 ns (MIN, MC68000L6 Spec.)The row address setup time to the DRAMs is given by:tASR == tAVSL - tRAV-MAV + tAEL-REL *where tRAV-MAV = Time delay, row address valid to memory address valid (MAX 4500A-15Spec.)thus,tASR = (35 ..:. 40 + 27) ns= 22 nsThe row address hold time to the DRAMs is guaranteed by the TMS4500A to meet - 20 or fasterspeed devices.5. Data valid to write enableIn both circuit configurations, data valid to write low is guaranteed by the MC68000L6. For the circuitin Figure 1 A this is accomplished by gating CAS with UDS and LDS to give an early write condition.For the circuit in Figure 2A R/W is gated with UDS and LDS to give a late write condition. Datavalid to write enable for both circuits is given by:tDS = tDOSL + tp32where tDS = Data setup timetDOSL = Data out valid to DS low (MIN, MC68000L6 Spec.)tP32 = Propagation delay (MIN, 74LS32 Spec.)ThustDS = (35 + 8) ns= 43 ns6. Read access time from CASThe required access time for both access and access grant memory cycles must be calculated.The read access time from CAS on normal access cycles for the gated R/W configuration (Figure 2A)is given by:wherethus,tCAC = 2.5(T) - tCHSLx - tAEL-CEL - tt(CEL) - tDICLtCAC = Access time from CAStAEL-CEL = Time delay, ALE low to CAS st~rting low (MAX 4500A-15 Spec.)tt(CEL) = CAS fall time (MAX 4500A-15 SpeG')tDICL = Data, in to clock low (MIN, MC68000~6 Spec.)tCAC = [2.5(166) - 65 - 150 - 15 - 25] n~= 1.60 nsThe read access time on access grant cycles for the gated R/W configuration (Figure 2A) is given by:tCAC = 2.5(T) - tCH-CEL - tt(CEL) - tDICLwhere tCH-CEL = Time delay, CLK high to access CAS starting low (MAX 4500A-15 Spec.)9-76

thus tCAC = [2.5(166) - 140 - 15 - 25] ns= 235 nsFor the gated CAS configuration one SSI gate (74lS32) delay must be subtracted from the above values.MC68000l10 Design CalculationsThe MC68000l8/l1 0 design requires extra hardware to meet the TMS4500A ALE to ClK lowtimings (tCl-AEl, tAEl-cLl and DRAM CAS access time (tcAC). This is accomplished by providingtwo clocks (ClK,

CLKrWRITE -------I.~ ..~---REFRESH---....... I.~ACCESS GRANT-..II (READ) -I¢AsALERAsCASREFREQROYJ>DTACK't:S"5!. FIGURE 4B - TMS4500A/MC68000L8-MC68000L 10 TIMING DIAGRAM(:;'Q)r+0':::JThe following calculations reflect gated R/W operation.t/)5' 1. Refresh time....~ Refresh interval = 1.56 msi TWST = 0, FS1 = 1, FSOr+0':::J2, Memory precharge timea. Access cyclestRP = 2(T) + to - tClSH - tp832 - tAEH-REH - ttREH + tp74 + tAEl-REl *Where to = Oelay between ClK and (j>tp832 = Propagation delay (MAX 74S832 Spec_)tP74 = Propagation delay (MIN 74S74 Spec.)andto = 1/2(tC) + tp04 -tc = 20 MHz clock cycle timetp04 = Propagation delay (MIN 74S04 Spec.)ts = Skew between ClK and (j>ts9-78

thus, to = [1/2(50) + 2 - 1] ns= 26 nstRP = [2(100) + 26 - 50 - 5 - 25 - 15 + 4 + 27] ns= 162 nsb. Refresh cyclestRP = 1.5(T) - tCLSH - tp832 - tAEH-REH - ttREH + tCH-RRL *tRP = [1.5(100) - 50 - 5 - 25 - 15 + 45] ns= 100 nsc. Access grant cyclestRP = T - tCH-RRH - ttREH + tCH-REL *tRP = (100 - 35 - 15 + 54) ns= 104 ns3. ALE to CLK relationshipALE low is triggered by the rising edge cP after AS goes low, which exceeds the minimum 10 nsspecification.4. Row address setup and hold timeThe row address setup time to the TMS4500A is given bytAV-AEL = T -tCLAV + to + tP74 + tpmin832where tCLAV = Clock low to address valid (MAX MC68000L10 Spec.)tPmin832 = Propagation delay (MIN 74AS832 Spec.)thus tAV-AEL = (100 - 55 + 26 + 4 + 1) ns= 76 nsThe row address setup time to the ORAM is given by:tASR = T - tCLAV + to + tp74 + tPmin832 - tRAV-MAV + tAEL-REL *thus tASR = (100 - 55 + 26 + 4 + 1 - 40 + 27) ns= 63 ns5. Oata valid to write enableThe data valid to write enable is dependent upon the tOOSL timing of the MC68000 when CAS.orW to the ORAMs is controlled as shown in Figure 1 A or Figure 1 B.co0,t:;C'CSE..o'too.5fI)Co0,t:;C'CSogQ.c.

The read access time on access grant cycles for the gated R/W configuration is given by:tCAC 2.5(T) - tCH-CEL - tt(CEL) - tDICLtCAC 2.5(100) - 140 - 15 - 15) ns= 80 nsMC68000L8 Design Calculations ResultsThe results for'the calculations of the design criteria for the MC68000LS are given in Table 1.TABLE 1 -MC68000LS DESIGN CRITERIA SUMMARYDESIGN CRITERIAMC68000L81. Refresh interval 1.95 ms2. Memory precharge timea. Access cycles (tRP) 203 nsb. Refresh cycles (tRP) 122 nsc. Access grant cycles (tRP) 129 ns3. ALE to ClK relationship Guaranteed by clocking AS Iowan the rising edge ot'cp4. Row address setup and hold timesa. To the TMS4500A (tAV-AEl) 93 nsb. To the DRAMs (tASR) 79 ns5. Data valid to write enable (tDS) 38 ns6. Read access time from CASa. Access cycles (tCAC) 149 nsb. Access grant cycles (tCAC) 142 nsThe proper choice of memory can be selected from Table 2 for each design. For the MC68000L6and MC68000L8 designs there are no memory speed restrictions. However, the MC68000L 10 designis restricted to only TMS4416-15 and TMS4164-12 devices; the limiting parameters being RASprecharge (tRP) and CAS access time (tCAC). To meet slower memory requirements the MC6800L 10clock frequency would have to be reduced. The maximum clock frequency for a desired memory speedcan be determined by substituting in the necessary DRAM timing parameters and solving for the inputclock period (T) in the design criteria for memory precharge time and read access time.TABLE 2 -MEMORY SELECTIONMICROPROCESSORMEMORY DEVICESCLOCKTMS4416 TMS4164FREQUENCY-15 -20 -12 -15 -20MC68000l6 6 MHz ~ ~ ~ ~ ~MC68000l8 8 MHz ~ ~ ~ ~ ~MC68000l8 (Hybrid) 7.46 MHz ~ ~ ~ ~MC68000l10 10 MHz ~ ~Meeting DRAM timing requirements is only a small part of microprocessor system design. The ultimategoal is to achieve maximum performance with minimum hardware. Of the three designs the MC68000L6interface requires the least amount of hardware while the MC68000L 10 interface has the fastest processor/memorycycle time. To capitalize on the best of both designs a compromise can be made bysubstituting a MC68000L8 into the MC68000L6 design and operating at less than' 8MHz withoutwait states. Operating under these conditions it can be shown that the processor/memory cycle timeapproaches that of the MC68000L 10 design with a minimum hardware interface (see Table 3).9-80

TABLE 3 -MICROPROCESSOR TO MEMORY CYCLE TIME*MICROPROCESSORCLOCKNUMBER OF WAITCYCLE TIME he)FREQUENCY PERIOD STATES INSERTED (N)MC68000L6 6 MHz 166 ns 664 ns 0MC68000L8 8 MHz 125 ns 625 ns 1MC68000L8 (Hybrid) 7.46 MHz 134 ns 536 ns 0MC68000L 10 10 MHz 100 ns 500 ns 1'tc = 4 (T) + NIT)where T = microprocessor clock periodN = number of wait states inserted.To determine the maximum speed that the MC68000l8 can operate without wait states it is necessaryto recalculate the design criteria using the MC68000l6 equations with MC68000l8 timing parameters(results in Table 4). From these values the restricting parameter will be the ALE to ClK low timing(minimum 10 ns) requirement necessary for proper TMS4500A operation. Setting tCl-AEL equal to12 ns (12 ns allows for 20% margin) and solving for T, yields a clock period of 134 ns (7.46 MHz)The design criteria for 7.46 MHz operation is also shown in Table 4. This "Hybrid" circuit meetsTMS4416-15,-20 and TMS4164-12,-15 timing requirements and has a processor/memory cycle timeapproaching that of the MC68000l1 0 design. This illustration shows the advantage of operatingwithout wait states when accessing DRAM, but does not directly reflect system throughputenhancement.System throughput calculations require a much more detailed analysis taking into consideration thesystems application, use of other types of memory (EPROM, PROM, ROM, and Statics), memory sizeand configuration, software, etc. It is beyond the scope of this application note to cover all of thesevariables in detail, although a brief overview can be given.TABLE 4 -MC68000L8 (HYBRID) DESIGN CRITERIA SUMMARY*DESIGN CRITERIAMICROPROCESSORMC68000L8 @ 6 MHz MC68000L8 @ 7.46 MHz1. Refresh interval 1.95 ms 2.09 ms2. Memory precharge timea. Access cycles (tRP) 167 ns 146 nsb. Refresh cycles (tRP) 189 ns 141 nsc. Access grant cycles (tRP) 170 ns 138 ns3. ALE to CLK relationship 28 ns 12 ns4. Row address setup and hold timesa. To the TMS4500A (tAV-AELl Guaranteed by tAVSL Guaranteed by tA VSLb. To the DRAM (tASR) 17 ns 17 ns5. Data valid to write enable (tDS) 38 ns 38 ns6. Read access time from CASa. Access cycles (tCAC) 180 ns 100 nsb. Access grant cycles (tCAC) 245 ns 165 nss::o'';:;co... E....os::tns::o'';:;co,2Q.c.«'Results reflect gated R/iN operation.All of the interface examples given in this application note used a tightly coupled processor/memoryinterface to maximize DRAM performance. The calculations and comparisons for the "Hybrid" circuitonly reflect that the processor is executing strictly out of DRAM which is not always the casein many sys,tems. As microprocessor speeds and memory size increase, the benefits Of the tightlycoupled memory array give way to asynchronous main memory configurations and cache memory9-81

implementations in order to relieve the processor of wait states when accessing memory. ApplicationsNotes SR-1 , "An Introduction To Cache Memory Systems And The TMS2150", and DRC-1,"The TMS4500A In An Asynchronous Bus System", address the concepts of cache and asynchronousmemory architecture in more detail than given here.The percentage of time a microprocessor uses for internal operations as opposed to memory accessesis also a factor in determining system throughput when wait states_ are used. The greater the percentageof time that a microprocessor spends accessing memory with wait states, the greater thethroughput degradation. Thus, for systems whose software requires extensive internal processor operationsand few memory operations it may be more desirable to operate with wait states as opposedto the "Hybrid" approach. Tabl.e 5 gives an example of a few MC68000 instructions and their effecton throughput. The actual average instruction time will be dependent upon the instruction streambeing executed, but this example will indicate how wait states affect the processor performance. Themultiply and divide instructions which require a large percentage of internal operations make apparentthe advantage of higher speed processors when doing extensive numeric processing; however if thememory intensive instructions predominate, the system running without wait states will execute fastereven at slower clock frequencies. Systems which execute program mainly out of EPROM, PROM,ROM and Static memory and only use. DRAM for data storage may also benefit from the use of thehigh speed processors. Each of the four designs has its own niche which is based on the necessarysystem application. Designs that require maximum memory performance and minimum componentcount may find the Hybrid interface more suitable, while systems requiring maximum processor performancewould utilize the MC68000L8/L 10 design.TABLE 5 -AVERAGE INSTRUCTION CYCLE TIMEA. CLOCK CYCLES AND MEMORY CYCLES PER INSTRUCTIONINSTRUCTIONCLOCK CYCLESMEMORY CYCLESPER INSTRUCTION TOTAL PER INSTRUCTION TOTALMOV AN@+ 8 2MOV AN@- 10 2ADD AN@+ 12 2ADD AN@- 14 2CMPI AN@+ 12 3CMPI AN@- 14 3BRA 10 2JMPAN@ 8 2JMP AN@(d) 10 98 2 20MULS 70 168 1 21B. AVERAGE CLOCK CYCLES/INSTRUCTION AND AVERAGE MEMORY CYCLES/INSTRUCTIONNUMBER OF INSTRUCTIONSAVERAGE CLOCK CYCLES/ AVERAGE MEMORY CYCLES/INSTRUCTIONINSTRUCTIONFirst nine instructions 10.8 2.2(excluding MULS)Ten instructions 16.8 2.19-82

C. AVERAGE INSTRUCTION CYCLE TIME*MICROPROCESSORAVERAGE INSTRUCTION CYCLE TIMEFIRST NINE INSTRUCTIONS TEN INSTRUCTIONSMC6S000L6 (@ 6 MHz, 0 WS T) 1.S00 p,s 2.S p,sMC6S000L8 (@ S MHz, 1 WS) 1.625 p,s 2.362 p,sMC6S000L8 (Hybrid)(@ 7.46 MHz, 0 WS)1.340 p,s 2.252 p,sMC6S000L 10 (@ 10 MHz, 1 WS) 1.300 p,S 1.S90 p,S• Average instruction time = processor clock cycle time X [average clock cycleslinstruction + (average memory cycleslinstruction X N wait states)]tws ~ wait state.D. RELATIVE PERFORMANCEMICROPROCESSORRELATIVE PERFORMANCEFIRST NINE INSTRUCTIONSTEN INSTRUCTIONSMC6S000L6 (@ 6 MHz, 0 WS) 1.0 1.0MC6S000LS (@ S MHz, 1 WS) 1.1 1.15MC6S000LS (Hybrid)(@ 7.46 MHz, 0 WS)1.25 1.19MC6S000L 10 (@ 10 MHz, 1 WS) 1.27 1.32As was mentioned earlier in the text, the designs have taken future memory upgradability into account.When 64K x 4 devices become available they will be pin compatible with the 16K x 4 allowingeasy memory expansion. The TMS4416 only requires 14 address lines to address its entire memoryarray (8 rows, 6 columns) thus leaving two unused address inputs to the TMS4500A (CAO, CA7).The TMS4416 uses inputs A 1-A6 for its 6 column addre~ses, disregarding AO, A 7 (see TMS4416spec.). These two unused inputs to the TMS4500A will be needed to complete the address spacefor the 64K x 4 devices (8 row, 8 column). In Figures 1 A and 2A, 14 consecutive address lines areused to address the TMS4416s which provides a linear address space. For 64K x 4 expansion, A 15and A 16 of the MC68000 will be connected to CAO and CA7 of the TMS4500A respectively. Thisconfiguration does not provide a linear address range for the 64K x 4 upgrade but, this would betransparent to the microprocessor and not effect system performance.For the circuits presented the memory upgrade would expand the memory size from 64K bytes to256K bytes by simply changing devices. If the memory array of TMS4416s was expanded to takefull advantage of the TMS4500As drive capability (32 devices), it would provide 256K bytes of memory.This could then be upgraded to a megabyte of memory by substituting the 64K x 4 devices. ApplicationsNote SMAAOO 1 "TMS4416/TMS4500A Evaluation Board" provides in detail the techniquesand advantages of designing for future memory upgradability.This completes the TMS4500A/MC68000 design requirements. Four MC68000 interfaces were givenwith two configurations for controlling accesses to upper and lower memory. Two of the designsoperate without wait states and two with wait states to illustrate a wide spectrum of operation. Thememory was implemented with TMS4416s for their modularity advantage over the X 1 DRAMs, andupgradaqility to future 64K x 4 DRAMs. A brief discussion of the strengths and weaknesses for thefour designs was given to provide some insight into the necessary system requirements that needto be considered to achieve maximum system performance for a given application.co.~COE~....o.5U)co.~CO.saQ.c.

"C'2..c:rm...o·j(I)....5'o3...mo·::s9-84

AN INTRODUCTION TO CACHE MEMORY SYSTEMSAND THE TMS21 50As the typical operating speeds of processors have increased to provide for the ever increasing need for computingpower, the necessity of developing a memory hierarchy (the incorporation of two or more memorytechnologies in the same system) has become apparent. One of these memory technologies is selected on thebasis of fast access time (with associated high cost per bit) to allow minimum system cycle time. The othertechnologies are chosen with the lowest possible cost per bit relative to speed in order to achieve the maximumsystem memory capacity. In a system with a multiple level hierarchy, the speed/cost relationship depends uponthe frequency of access and the total memory requirement at that leveL By proper use of this hierarchy throughcoordination of hardware, system software, and in some cases user software, the overall memory system willreflect the characteristics that approximate the fast access time of the fast memory technology and the low costper bit of the low cost memory technology. Large computer systems have made use of this memory optimizationtechnique to maintain very large data bases and high throughput (see Figure 1). Many smaller processor systemsuse this technique to allow mass storage of data, where a tape or disk is the low cost memory and RAM (RandomAccess Memory) is the fast memory technology.Memory hierarchy is now extending to the RAM memory used in microcomputer systems because of the increasein processor speeds. Typically, Dynamic RAM (DRAM) is used as the bulk or main memory and HighSpeed Static RAM (HSS) serves as the fast access memory. This HSS RAM is usually 1 K to 8K words deep andserves as a fast buffer memory between the processor and the main memory. This small, fast buffer memory iscalled "cache" memory as it is the storage location for a carefully selected portion of the data from the mainmemory. The addresses for that portion of memory currently in the buffer memory is saved in the cache tag RAM(a small memory that is used to store the addresses of the data that has been mapped to cache) .co"';::;COE~....o.5enCo"';::;CO"~Q.c.•

RELATIVE MEMORY SIZEARCHIVAL STORAGE(MAGNETIC TAPEI1BULK STORAGE(DISKIINCREASINGCOST PER BITINCREASINGACCESS TIMEFIGURE 1 -MEMORY SIZE VS. ACCESS TIME AND COST PER BITWhen the processor accesses main memory, the processor address is compared to the addresses currently present in thecache tag RAM. In the case where a match occurs, the required data is resident in the cache and the access is called a "hit,"and is completed in the cycle time of the fast memory. If there is no match (a "miss"), the main memory is accessed, and theprocessor must be delayed to allow for the slower access cycle of the main memory. The determination of whether a hit hasoccured is the responsibility of the cache tag RAM. Figure 2 shows the relative placement of the processor, main memory,cache, and cache tag RAM within a system.Since there must be comparisons made between the current processor address and the addresses in the cache, the cachetag RAM must have a very fast accesS time to prevent the degradation of processor accesses even when a match occurs.Previously, the memory used for the cache tag RAM was the same as that used for the cache; which, due to added delaysthrough comparision logic. meant that the full benefits of the cache were not realized.PROCESSOR:/'~DATA BUS"DCACHE BUFFERE4-RAMAr ....,/"ADDRESS BUS ){1. VzDACACHE TAGRAMMI...MAINMEMORYFIGURE 2 -TYPICAL MEMORY SYSTEM WITH CACHE9-86

I~ _________________________________The TMS2150 Cache Tag RAM has been designed to reduce this cache access degradation to a minimum by incorporatingthe matching logic on-chip thus providing match recognition times compatible to the access time of the cache buffermemory.The TMS21 50 implements the "set-associative" type of cache address matching. This algorithm may be more clearlyunderstood by considering main memory as an (m) by (n) array of blocks and the cache is an (n) by (k) array (see Figure 3).Each block is composed of (x) words and transfers between main memory and cache memory always move all (x) words inthat block. Corresponding to every block in the buffer RAM is a tag address specifying which block of main memory is currentlyresident in the buffer RAM at that location. The set-associative algorithm maps each modulo (n) group of (m) blocks intothe corresponding (n) row of the cache. The low order address lines of the processor covering the sets (n) select a row ofthe cache buffer and the corresponding row in the tag RAM. The data is stored in the cache buffer and the high order addressspecifying the block (m) is saved in the tag RAM. The high order address then becomes the tag.LOW ORDERADDRESSnn·121oMAIN MEMORYXXXX012 m·1\-------~V~--------Im(HIGH ORDER ADDRESS)~ABUFFER RAM.,xCACHE,-----i-t-i-i-i-1..JJ.t-K~DATAK = Number of BUFFER/TAG groups for multiple cache systemsX = Blocks moved to cacheo = Valid data from main memory7 = Areas of cache that have not been loaded from main memoryNV = Code to indicate non-valid labelO. 1.2. m-l = Labels from high order address specifing the block moved from main memory.FIGURE 3 -SET-ASSOCIATIVE CACHE ADDRESS MATCHING~\TAG RAM....NV-tm·1~NV--iNV2~-I0-I0-I1....Il4----K----.~..LABELThere are several algorithms used to determine which areas of main memory should be resident in cache and which should bereplaced (first-in, first-out; least recently used; or random). Since programs typically have the property of locality (over shortperiods of time. most accesses are to a small group of memory addresses), these replacement algorithms can make thecache have the majority of processor accesses resulting in hits. The hit ratio (number of hits x 1 OO%/number of memory accesses)runs 90% and higher in systems with well coordinated memory to cache mapping routines. Note that as the blocksize (x) increases. the replacement mapping algorithm options have greater impact on the cache performance.c:o';::CO.. Eo'+-.5enc:o'';:;CO,2Q.Co«Many microprocessors are operating with memory access times of 130 ns or less when running at maximum frequency.After allowing for address buffering, decoding. and propogation delays through data buffers, the maximum access time thatcan be tolerated is 75 ns or less before processor throughput is affected. For large memory systems, DRAM can be used toachieve a cost effective memory; however these can not meet a 75 ns access requirement. If the actual system throughputsfor a system with cache and one without cache are compared. the advantages of cache become obvious.For comparison of the two architectures, assume that a processor is implemented in which 30% of the active cycles involvemain memory (the other 70% used for instruction decoding and internal operations). Also assume that the processor cyclesat 250 ns with a required memory access time of 75 ns, but if the memory is not ready the cycle time is extended by 100 ns9-87

increments till satisfied. This processor using 150 ns DRAMs would require one delay increment on main memory accessesand 200 ns DRAMS would require two delay increments. The average cycle time can be calculated for each memory speedas follows:Average .CY'cle Time = [(INT) x (CYC)] + [(MEM) x (CYC + DEL))where INT = percent of time doing internal operationsCYC = processor cycle timeMEM = percent of time doing memory accessesDEL = number of delay increments x 100 nsFor a processor using 150 ns DRAMs:Average Cycle Time = [(70%) x (250 ns)) + [(30%) x (250 + 100))= 280 nsFor a processor using 200 ns DRAMs:Average Cycle Time = [(70%) x(250 ns))+[(30%) x(250+200))= 310 nsFor the same system with cache memory assume a 90% hit ratio with 75 ns cache and 200 ns DRAM:Average Cycle Time = [INT x CYC) + [MEM x [(HIT x CAC) + (MIS x (CYC + DEL))))where INT = percent of time doing internal operationsCYC processor cycle timeMEM = percent of time doing memory accessesDEL = number of delay increments x 100 nsHIT = percent of memory accesses hit cacheMIS = percent of memory accesses miss cacheCAC = cache memory access cycle timeAverage Cycle Time = [70% x 250) +[30% x [(90% x 250) + (1 0% x (250 +200))))= 253 nsThis value represents a 10% improvement with 200 ns devices over the non-cache implementation with 150 ns parts and18% using 200 ns parts. This performance improvement can be further demonstrated for those systems using custom orbit-slice processors where the memory cycle time as well as access time is of concern. For this example, consider a processorwith a cycle time of 50 ns and main memory cycle time of 250 ns (use the same access ratios as in the previousexample):ACT (Without Cache) = [(70%) x (50)) + [(30%) x (250)L= 110 nsACT (With Cache) [70% x 50) + [30% x [(90% x 50) + (1 0% x 250))= 56 nsThis represents a 49% decrease in average cycle time for the processor using 50 ns cache memory. If the main memory wasrated at a cycle time of 500 ns, either using very slow main memory, error detection/correction, or due to allocation of alternatecycles for some other activity (multi-processors, direct memory access, display refresh, etc.); the cache would still givean average cycle time of 63.5 ns, which is an improvement of 65% over the 185 ns average cycle time for a non-cachesystem.The following figures show several applications for TMS2150 in cache memory systems. Figure 4 shows a cache memoryconfiguration that has a 32-megaword main memory (represented as 32-megabytes since only an eight-bit data bus is used)with a block size of 2. In this particular example, a cache containing 512-two word blocks was chosen thus defining themain (n)x(m) array as being 512 sets of 32,768-two word blocks. The 32-megaword memory requires an address bus of25 lines. The least significant address (AO) is used as a word select for one of the two words in each block. The next leastsignifiCant address lines (A 1 - A9) are used as the set select inputs to the cache buffer RAM and the cache tag RAM.The remaining high order address lines (A 10 - A24) form the label or tag which is stored and compared by the tag RAM.9-88

Since the label in this example is composed of 1 5 address lines, two TMS21 50s are used as an expanded tag. The 1 5 addresslines are the data inputs to the tag RAM and the 16th data input is tied to + 5 V so that after RESET invalid data cannotforce a match. The match output of the two TMS2150s are ANDed together to form the enable for the cache data buffer. Inthis manner, if the contents of either TMS21 50 does not contain a match, the cache is not enabled. This ANDed MATCHsignal is also used by the control circuitry to notify the system that the address is not present in the cache so that mainmemory might be accessed. The control circuit is also responsible for the reseting of the cache upon power-up, which is accomplishedwith a low pulse on the RESET input of the TMS21 50. After reset, no matches will occur at any locations untilthat location has been written ..A00-07PROCESSOR4OQ1-DQ4 •1K)(4RAMBUFFER•E..., .4OQ1-0Q41K)(4RAMMAINMEMORYUPTO32M BYTESAO-A910~'1AO-A9AO-A24AO-A9'lOt1 AO-A99{1-A9 7 +S V 9't' -A9 B~ A17-A24,A10-A1eCDO - De 07 "'--""':0:"!0~-1.:0~7~--"AO - AB AO - AB --;:::0-~~i _____ T_M_·~T2~1_60_____ M.. ~ ~~i _____ T_M_:'~2~1_601CONTROL(RESET. W. PElBLOCK SIZE = Z_____FIGURE 4 - CACHE MEMORY CONFIGURATIONM~ I _......co'';::CO.. Eo~.Eenco'';::CO,~Q.c.

In the example shown in Figure 5, the expansion of the cache RAM is carried out in both depth (more sets) and width (widertag). The block size has been chosen as one such that the 1 K cache now represents 1024 blocks of one word each. Thehigh order addresses are still used as the label to the tag RAM but now A9 is used to select between two TMS2150 pairseach containing labels for 512 of the cache memory blocks. Addresses lines AO - A8 are thus used as the set addressinputs. If the chip select (S) is at logic one (deselected), the TMS2150 match output (M) is high, so an AND gate can beused to enable the cache data buffers and also to notify the control circuit if access needs to be made into the main memory.The logic for this system is shown so that the upper pair is compared for the first 512 blocks within cache and the lowerpair is compared for the second depending on the state of address A9.ADDRESSES TOCACHE BUFFER RAMMATCH OUTPUT TOBUFFER ENABLEPROCESSORA9 AO-AB Al0-A16MAINMEMORYUP TO32M BYTES............ +------+--------iM STMS2150.-~~---------+---------------~sl>"'C"En·0)...o·::Jen:;-....o30)...o·::JFIGURE 5 -BLOCK SIZE = 1CACHE MEMORY CONFIGURATION9-90

A dual cache structure (K = 2) is shown in Figure 6. The 1 megaword main memory is divided into 1024 sets of 256 fourwordblocks. In this example, AO and A 1 are used to select which one of the four words within a block are accessed, andA2 - A 10 select which of the 51 2 block labels are to be compared. Addresses A 1 2 - A 1 9 form the eight-bit label for theblock. Address A 11 is used by the cache control logic in conjunction with the possible processor status lines as chip selectinputs. The match outputs from the two TMS21 50s A 1 and A2 are NANDed to form an active low enable to the cache databuffers and to serve as request to the control logic. The match outputs from B 1 and B2 also are NANDed to perform a similarfunction for cache RAM B. If no match is found in cache RAM A or B, the control logic will initiate an access from mainmemory. The purpose of the dual cache architecture is to allow for rapid switching between multiple tasks or programs sincethe processor can have access to one cache while the controller moves data between main memory and the other cache. Thedual or mUltiple cache approach also yields more replacement options than the single cache architecture. When an access'results in a miss in the single cache system, the data in cache is replaced by the current data even though the old data maystill be useful. By using "independent" caches, the control can determine which data is most expendible and replace thatblock while the other caches keep their potentially useful data.Cache memory architecture can enhance the throughput of many micr~processor systems, allowing large, low-cost memoryto perform like high speed RAM. The TMS21 50 reduces the tag memory implementation cost and complexity and provideslabel comparison times comparible to the access times of high-speed memories. These additional benefits make highperformancemicroprocessor designs that can utilize the same techniques of optimizing cost/memory size/throughput thathad previously been found only in larger computer applications.MOS MemoryApplications EngineeringPROCESSORCACHECONTROLLOGIC~ lsIle, 00-016. r I CACHE00-016RAM BCACHE RAM AA12-A1900- 01BA1-A19CACHE RAM ARRANGED INDUAL 4K WORD CACHE9,A2-A10S ±A12-A19DO 074 AO-ASCACHE RAMB1 TAG M~_CACHE TAG M M'ATCii1iI-J __ ~ ________ ~ ____________________ ~ ________ ~~- RAMB2______-1..1-00-07AD-ASCACHE TAGS RAM A1 ~ l-Jl-TISM hh..1 _ C~~~ ;:G M1 SMAINMEMORYUPTO1M WORDS-: s MEMORYMEMORY DIVISION1024 SETS256 BLOCKS/SET4 WORDS/BLOCKCONTROL-L..Er-co'';:CO.. E..- o.EtnCo'';:CO,~Q.c,;

»'C"E..crQ)r+0':::Jtil:;-....o...3Q)r+0':::J9-92

HIGH DENSITY ROMSIN CONSUMER GAME SYSTEMSThis application report will introduce the reader to the optionsavailable with the TI high density ROM family. Twochip select options have been implemented for these devices:a standard addressing scheme and a bank select option thatdivides the device into 8K banks. The bank select versionswill allow the higher density ROMs to work with most ofthe game systems now on the market even though the systemswill not directly address 16K of memory.Most of the game systems on the market use a 74138 oneof-eightdecoder to provide the chip select signals. The exceptionsto this use a similar method for generating chipselects and this discussion is applicable to them. Since mostof the systems used for games do their chip select decodingin 8K byte blocks, the 8K bank select architecture is idealfor systems that have restricted address space.The bank select ROM (TMS47128) is put into the systemwith the bank select lines connected to the appropriate systemchip select outputs (see Figure 1). These systems will onlyhave one chip select active at a time. If the bank select inputsof the ROM are programmed active low, the device outputswill be tri-stated unless one of the system chip selectsis active. This allows the chip selects of the ROM to be tiedactive and let the bank select inputs control the accessed bankand output impedence. Most of the memory accesses in agame system will be to ROM so having the device activeall the time will not significantly increase system current consumption.In fact the system may operate more reliably dueto the lack of current spikes caused by powering the ROMon and off.The limiting factor in most game systems on the marketis the lack of ROM address space. By providing a familyof high density ROMs with the bank select feature TI hasgiven these games extended capabilities and the software offersthe opportunity to write more colorful and complicatedprograms.MOS MemoryApplications EngineeringAO-A12~--------------~ 581~ ______________ ~SB2Q1-Q8r---------1TMS47128+5 Vco'';::;CO.. Eo\f-.5(I)co'';::;CO.~Q.c.•«Figure 1. Game SystemlTMS47128 Interface9-93

•9-94

Alphanumeric Index, Table of Contents, Selection GuideInterchangeability Guide ..Glossary /Timing Conventions/Data Sheet StructureDynamic RAM and Memory Support DevicesDynamic·· RAM Modules ..EPROM Devices .., ROM DevicesStatic RAM and Memory Support DevicesApplications ·'nformation ..Logic SymbolsMechanical Data

184LOGIC SYMBOLS1. INTRODUCTIONEXPl.ANATION OF NEW LOGIC SYMBOLSFOR MEMORIESThe International Electrotechnical Commission (lEC) has been developing a very powerful symbolic language that canshow the relationship of each input of a digital logic circuit to each output without showing explicitly the internallogic. At the heart of the system is dependency notation, which will be partially explained below.The system was introduced in the USA in a rudimentary form in IEEE/ANSI Standard Y32.14-1973. Lacking at thattime a complete development of dependency notation, it offered little more than a substitution of rectangular shapesfor the familiar distinctive shapes for representing the basic functions of AND, OR, negation, etc. This is no longerthe case.Internationally, IEC Technical Committee TC-3 has prepared a new document (Publication 617-12) that will consolidatethe original work started in the mid 1960's and published in 1972 (Publication 117-15) and the amendments and supplflmentsthat have followed. Similarly for the USA, I EEE Committee SCC 11.9 has revised the publication IEEEStd 91/ANSI Y32.14. Texas Instruments participated in the work of both organizations and this 1984 Edition of theMOS Memory Data Book introduces new logic symbols in anticipation of the new st~ndards. When changes are made asthe standards develop, future editions of this book will take those changes into account.The following explanation of the new symbolic language is necessarily brief and greatly condensed from what thestandards publiGCItions will finally contain. This is not intended to be sufficient for those people who will be developingsymbols for new devices. It is primarily intended to make possible the understanding of the symbols used in this book.2. EXPLANATION OF A TYPICAL SYMBOL FOR A STATIC MEMORYThe TMS 2114 symbol will be explained in detail. This symbol includes almost all the features found in the others.Section 4, oiagramatic Summary, should be referred to while reading this explanation.TMS2114RAM102Ax4By convention all input lines are located on the left and output lines arelocated on the right. When an exception is made, an arrowhead shows reversesignal flow. The input/output lines (001 through 004) illustrate this.The polarity indicator ~ indicates that the external low level causes theinternal 1 state (the active state) at an input or that the internal 1 state causesthe exte[nal low level at an output. The effect is similar to specifying positivelogic and using the negation symbol 0 •The rest of this discussion concerns features inside the symbol outline. Theaddress inputs are arranged in the order of their assigned binary weights andthe range of the addresses are shown as A r:; where m is the decimal equivalentof the lowest address and n is the highest. The inputs and outputs affected bythese addresses are designated by the letter A.en'0.QE>en'e»The letter Z followed by a number is used to transfer a signal from one point (,)in a symbol to another. Here the signal at output A,Z3 transfers to the 3 atthe left side of the symbol in order to form an inpot/output port. The A .9means the output comes from the storage location selected by the addressinputs. _.The 'V symbol designates a three·state Ol,ltput. Three-state outputs will always .be controlled by an EN function. When EN stands at its internal 1 state, theoutputs are enabled. When EN stands at its internal 0 state, the three-stateoutputs stand at their high·impedance states.TEXAS INSTRUMENTS 10-1INCORPORATEDPOST OFFICE BOX 225012 • OALLAS, TEXAS 75265

LOGIC SYMBOLSSince the boxes associated with 002, 003, and 004 have no .internal qualifying symbols, it is to be understood thatthese boxes are identical to the box associated with 001.Any 0 input is associated with storage. Whatever internal state is taken on by the 0 input is stored. The letter A (inA,Z3) indicates that the state of the 0 input will be stored in a cell selected by the A inputs. If the 0 input is disabled,the storage element retains its content.Various types of relationships between ports can be indicated by what is called dependency notation. A letter indicatingthe type of dependency (e.g., C, G, Z) is placed at the affecting input (or output) and this is followed by a number.Each affected input (or output) is labeled with that same number. The Z symbol explained above is one form ofdependency notation. Several other types of dependency have been' defined but their use has not been anticipated inthis book.The numeral 2 at the 0 input indicates that the 0 input is affected by another input, in this case a C input (i.e., 1 C2).When a C input stands at its internal 1 state, it enables the affected 0 input(s). When the C input stands at its internalo state, it disables the 0 input(s) so that it (they) can no longer alter the contents of the storage element(s).The C input is itself affected by another input. The numeral 1 in front of the C shows that a dependency relationshipexists with a G input. The letter G indicates an AND relationship. When a G input stands at its internal 1 state (low inthis case), the affected inputs (EN and C2 here) are enabled. When the G input stands at its internal 0 state, it imposesthe 0 state on the affected inputs.Pin 10 'has two functions. Its function as a C input has just been explained. Note that for the C input function to standat its 1 state, pin 10 must be low and pin 8 must also be low. The other function of pin lOis as an EN input. Thiscontrols the 3·state outputs. This EN input is also affected by the AND relationship with pin 8 so for the EN functionto stand at its internal 1 state (enabling the outputs), pin 10 must be high and pin 8 must be low.Labels within square brackets are merely supplementary and shOUld be self·explanatory.3. CACHE ADDRESS COMPARATORThe block diagram for the TMS 2150 uses the RAM symbol (explained in Section 2) and also the following:Buffer without special amplification. If special amplification is included, thenumeral 1 is replaced by t>.roCOC:;"(I)'

LOGIC SYMBOLS4.DIAGRAMATIC SUMMARYINPUTSG (AND) DEPENDENCYActive H (high)Active L (low)Active on L-to-H transitionActive on H-to-L transitiona G5b 5- -c 5d 5abacad-r--r--INPUT/OUTPUT---r-a 4-l__ a --L __C(CONTROL) DEPENDENCYa--fc;--b---t:D b--.... -~S [Set]R [Reset]OUTPUTSActive highActive low*3-StateOpen-Circuit (L-type)tOpen-Circuit (H-type):fai---z1-5 z1Z (INTERCONNECTION) DEPENDENCYaabCOMMON CONTROL BLOCKab• The active-low indicator may be used in combination with the 3-state and open-circuit indicators.t L-tYpes include N-channel open-drain and P-channel open-sourceoutputs.of H-tYpes include P-channel open-drain and N-channel open-sourceoutputs.en'0.cE>CI)'enCJo..Jccdd84TEXAS INSTRUMENTS 10-3INCORPORATEDPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265

LOGIC SYMBOLS5. EXPLANATION OF A TYPICAL SYMBOL FOR A DYNAMIC MEMORY5.1 THE TMS 4116 SYMBOL....;(5"";) __ -1 20D7/2100AO (7)~! (6)A3 (12)A4 (11)A5 (10)A6 (13)TMS 4116RAM 16K X 1oA16383The TMS 4116 symbol will be explained in detail for eachoperating function. The assumption is made that Sections2 and 4 have been read and understood. While this symbolis complex, so is the device it represents and the symbolshows how the part will perform depending on the sequencein which signals are applied.RAS _(....;4) .... --1CAS_(1_5~)~~------~23C22TN (3)D (2)A,22DA\l(14) Qr-0CCIc:;'til'

lOGIC SYMBOLSWhen RAS goes low, it momentarily enables (through C20, I> indicates a dynamic input) the D inputs of the sevenaddress registers 7 through 13. When CAS goes low, it momentarily enables (through C21) the D inputs of the sevenaddress registers 0 through 6. The outputs of the address registers are the 14 internal address lines that select 1 of16,384 cells.5.3 REFRESHRAS4lREFRESH RowlWhen RAs goes low,row refresh starts. It ends when RAS goes high. Theother input signals required to carry out refreshing are not indicated bythe symbol.5.4 POWER DOWNRAS ~ 24 [PWR DWNlCAS ----1 G24 .CAS is AND'ed with RAs (through G24) so when RAS and CAS are bothhigh, the device is powered down.5.5WRITERASCASiND23C22By virtue of the AND relationship between CAS and iN (explicitly shown),when either one of these inputs goes low with the other one and RAs alreadylow (RAS is AND'ed by G23), the D input is momentarily enabled(through C22). In an "early-write" cycle it is W that goes low first; thiscauses the output to remain off as explained below.5.6READCAS--e.......,&.;~C21G24RAS --....... ~ G23iN ----I 23,21 D '24EN1----..... A\lIf you have questions on this Explanationof New Logic Symbols, please contact:F.A. Mann MS 49Texas Instruments IncorporatedP.O. Box 225012Dallas, Texas 75265Telephone (214) 995-2867QThe AND'ed result of RAS and iN (produced by G23) isclocked into a latch (through C21) at the instant CAS goeslow. This result will be a "1" if RAS is low and iN is high.The complement of CAS is shown to be AND'ed with theoutput of the latch (by G24 and 24). Therefore, as long asCAS stays low, the output is enabled. In the "early-write"cycle referred to above, a "0" was stored in the latch by Wbeing low when CAS went low, so the output remaineddisabled.IEEE Standards may be purchased from:Institute of Electrical and Electronics Engineers, Inc.345 East 47th StreetNew York, N.Y. 10017International Electrotechnical Commission (lEC)publications may be purchased from:American National Standards Institute,lnc.1430 BroadwayNew York, N.Y. 10018tn'0.cE>en(.)'0,o...I184TEXAS INSTRUMENTS 10-5INCORPORATEDPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265

oCQ(;'rn-

Alphanumeric Index, Table of Contents, Selection GuideInterchangeability GuideGlossary/Timing Conventions/Data Sheet StructureDynamic RAM and Memory Support DevicesDynamic RAM ModulesEPROM DevicesROM Devices ..Static RAM and Memory Support DevicesApplications Information ..Logic· SymbolsMechanical Data

•

MECHANICAL DATAgeneralElectrical characteristics presented in this catalog, unless otherwise noted, apply to device type(s) listed in the pageheading, regardless of package. Factory orders for devices described should include the complete part-type numberslisted on each page.MOS NUMBERING SYSTEMEXAMPLE:TMS2114L-45 N(J.g. )LMax AccessTMS Commercial MOSSMJ Military MOS4 45 ns - 20 200 ns FP Plastic Chip Carrier- 5 55 ns - 25 250 ns J Cerpak/Cerdip- 7 70 ns - 30 300 ns JD Side Braze-10100 ns -35350 ns MC Chip-on-Board-12 120 ns -45 450 ns N Plastic DIP-15 150 ns-40°C to BO°CL OOC to 70°CM -55°C to 125°CS -55°Cto 100°Ct Inclusion of an "L" in the product identification indicates the device operates at low power.manufacturing informationDie-attach is by standard gold silicon eutectic or by conductive polymer.Thermal compression gold wire bonding is used on plastic packaged circuits. Typical bond strength is 5 grams. Bondstrength is monitored on a lot-to-Iot basis. Any pre seal bond strength of less than 2 grams causes rejection of theentire lot of devices. On hermetic devices either thermal compression or ultrasonic wire bonding is used. All hermeticMaS LSI devices produced by TI are capable of withstanding 5 X 10 - 7 atm cc/sec inspection any may be screenedto 5 X 10 - B atm cc/sec fine leak, if desired by the customer, for special applications.All packages are capable of withstanding a shock of 3000 g. All packages are capable of passing a 20,000 g acceleration(centrifuge) test in the V-axis. Pin strength is measured by a pin-shearing test. All pins are able to withstand theapplication of a force of 6 pounds at 45 0 in the peel-off direction.dual-in-line packagesA pin-to-pin spacing of 2.54 mm (100 mils) has been selected for standard dual-in-line packages (both plastic andceramic).TI uses three types of hermetically sealed ceramic dual-in-line packages: cerdip-, cerpak, and sidebrazed. The cerdipand cerpak packages have tin-plated leads. The sidebraze package has gold-plated leads. The plastic package mayhave tin-plated leads, 60/40 solder-plated leads, or 60/40 hot-solder-dipped-finished-Ieads.chip-on-board34TI will bond some MaS memory circuits (particularly ROMs) directly to a printed circuit board specified by the customer.This custom packaging technique for consumer applications utilizes a plastic sealant molded over the silicon directlymounted and ultrasonic wire bonded to a printed circuit board. Board material as well as dimensions are specified...... b.y .. th.e .. c.u.st.o.m .. e.r.............................................................................. ~TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 7526511-1

MECHANICAL DATAAll measurements are given using both metric and English systems. Under the metric system, the measurements aregiven in millimeters; under the English system, the measurements are given in inches. The English system measurementsare indicated in parentheses next to the metric.ceramic packages -side braze (JD suffix)~ ~r- A±0.025_(±0.010)~~~105 00,279 ± 0,076 ... I~(0.011 ± 0.003)0,508(OM~~OI~Lm5,08 (0.200) MAXSEATING- PLANE T 3,175 (0.125) MINPIN SPACINGJ L ~~2,54 (0.100) NOM 0,457 ± 0,076(0.018 ± 0.003)~DIM.A ± 0,025(±0.010)B(MAX)C(NOM)16 18 20 22 24 24 287,62 7,62 7,62 10,16 7,62 15,24 15,24(0.300) (0.300) (0.300) (0.400) (0.300) (0.600) (0.600)20,57 23,11 25,65 27,94 30,86 32,77 35,94(0.810) (0.910) (1.010) (1.100) (1.215) (1.290) (1.415)7,493 7,493 7,493 10,03 7,493 15,11 15,11(0.295) (0.295) (0.295) (0.395) (0.295) (0.595) (0.595)4015,24(0.600)51,31(2.020)15,11(0.595).. ------------------11-2 TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS, TEXAS 75265184

MECHANICAL DATAceramic packages -cerdip/300 mil cerpak (J suffix)

MECHANICAL DATAceramic packages --------600 mil cerpa k (J suffix)3:CDn::rIII::l(i'!!.oIII------------------------------IN--ST~TJ~~:U:~:;E~N::y.s:TE-XA-S-75--265...aI.11-4POST OFF! CEBOX225012. DALLA,184

MECHANICAL DATAplastic packages (N suffix)~'\(~I' N-'----------BMAX 'I, o~I~~~:{J:::::: lj] MAX~M~X INDEX MARKS I0,508 (0.020) MIN.L~~=~~=~=~~::=:.:.::=:=~:=~= J5.0810.2001 MAX-SEATING PLANE---r-- ~ J I D MIN .0.279 ± 0,076 -II-- 0,457 ± 0,076 -II- ~ I-0,838 (0.033) NOM(0.011 ± 0.003) (0.018 ± 0.003) PIN SPACING 1,778 (0:070) MAX2,54 (0.100) NOM84~DIM.A (MAX)8 (MAX)C (MAX)D (MIN)16 18 .20 22 24 28 408,255 8,255 8,255 10,80 15,88 15,88 15.49(0.325) (0.325) (0.325) (0.425) (0.625) (0.625) (0.61)22,1 23,37 27,18 28.45 32,26 36,58 53,1(0.870) (0.920) (1.070) (1.120) (1.270) (1.440) (2.090)6,858 6,858 6,858 9.017 13,97 13,97 13,97(0.270) (0.270) (0.270) (0.355) (0.550) (0.550) (0.550)3,175 3,175 3,175 .3,175 2,921 2,921 3,175(0.125) (0.125) (0.125) (0.125) (0.115) (0.115) (0.125)'2co..c:Co)Q)~----------------_BITEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265...cococ11-516Co)

MECHANICAL DATAceramic chip carrier package (FE suffix)17 1612119A286541.40 (0.055)1.1410.045)l ~NUMBERA1A2B1 B2 C2OFTERMINALS MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX8.76 9.02 13.84 14.10 7.80 7.95 12.88 13.03 1.65 2.0128(0.345) (0.355) (0.545) (0.555) (0.307) (0.313) (0.507) (0.513) (0.065) (0.079)11.30 11.56 13.84 14.10 10.34 13.03 12.88 13.03 1.65 2.0132(0.445) (0.455) (0.545) (0.555) (0.407) (0.513) (0.507) (0.513) (0.065) (0.079)11 ___________________________11-6TEXAS /INSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 75265184

MECHANICAL DATAceramic chip carrier package (FG suffix)121314151617 18 2(1,40) 0.055 j.--(0,99) 0.039 I0,76 (0.030)0,56 (0.022)t+.84TEXASINSTRUMENTS~.POST OFFICE BOX 225012 • DALLAS. TEXAS 75265I 1,85 (0.073)~1,55 (0.061)•11-7

MECHANICAL DATAplastic chip carrier package (FP suffix)~----::~~ :~:~~~:------.!~ 7,34 (0.289)----1l-==:..c::::l- 7,14 (0.281)-..C::l.-1rT:-lllO 9 8I I 1211,86 (0.467)11,61 (0.457)131l 0,686 (0.027)0,660 (0.026)10,90 (0.429)14,.~[.42" ~:-:---IN-D-E-X-D-O-T--~------t_~SEATING PLANE17 180,737 (0.029)0,635 (0.025)1,12 (0.044)MAX.. --------------------------11-8 TEXASINSTRUMENTSPOST OFFICE BOX 225012 • DALLAS. TEXAS 7526518

Texas InstrumentsSemiconductor Technical LiteratureOverview of IEEE Std. 91-1984, High-sp~ed CMOS Logic Data Book. TMS7000 FSlmily Data Manual,1984, 32 pages. 1984, 800 pages. 1983, 350 pages.A brief condensed overview of the Detailed specifkations and applica- Detailed specifications and applicasymboliclanguage for digital logic tion information on the TI family of tion information on TI"s family ofcircuits by the IEEE and the IEC High-speed CMOS logic devices. microprogrammablc H-bit micro-Technical Committee TC-3 incorpo- Includes product selection guide. computers. Includes architecturerated in IEEE Std. 91-19H4. glossary. and alphanumeric index. description. device operation.instruction set. electrical characteristics.and mechanical data.TTL Data ~ook, Vol. I, 1984, Linear Circuits Data Book, 1984,336 pages. 820 pages.TMS7000 microcomputers includeProduct guide for all TI TTL Detailed specifications on opera- versions in CMOS and SMOS anddevices. functional indexes. alpha- tiona I amplifiers. voltage with on-board UART.numeric index, and generalcomparators. voltage regulators.information.data-acquisition devices. aid converters.timers. switches. amplifiers. ManualsTMSxxxxx Microcomputer DataTTL Data Book, Vol. 2, 1984,and special functions. Includes These manuals contain detailed1392 pages.LinCMOS '" functions. Contains specifications and application infor-Detailed specifications and applica- product guide. interchangeability mation on specific TMSxxxxxtion information on the TI family of guide. glossary. and alphanumeric microcomputers and peripherals.Low-power Schottky (LS). Schottky index. Include architecture description.(S), and standard TTL logic devices.device operation, instruction set,Interface Circuits Data Book, 1981,TTL Data Bo()k, Vol. 3, 1984,electrical characteristics, and700 pages.792 pages.mechanical data.Includes specifications and applica-Detailed specifications and applications information on TTL logic Assembly Languagetion information on the TI family interface circuits. as well as product Programmer's Guides.of Advanced Low-power Schottky profiles on the line drivers/receivers TMS3201O. 19H3, 160 pages.(ALS) and Advanced Schottky (AS) and peripheral drivers. TMS99000, 19H3, 322 pages.logic devices.TMS7000. 19H3. 160 pages.Optoelectronics Data Book, 1983,TTL Data Book, Vol. 3 Supplement,Include general programming480 pages.1984, 255 pages.information, assembly instructions,Contains more than 300 device assembler directives. assembler out-Adds to the detailed specifications types representing traditional put. and application notes.of AS and ALS logic devices with optoelectronics (IREDs. LEOs,data on 51 new' functions, applica- detectors. couplers. and displays). TMS32010 User's Guide, 1984,tions information, system design special components (avalanche, 400 pages.guidelines, errata data and a func- photodiodes. and transimpedance Detailed application information ontional index of all TI bipolar digital amplifiers). fiber optic components the TMS32010 Digital Signal Prodevices.. (sources, detectors. and intercon- cessor. Detailed reference manualTTL Data Book, Vol. 4, 1984,necting cables). and new image on use of the TMS320 instruction416 pages.sensors (linear and arrays).set. Data sheets included.Detailed specifications and applica- MOS Memory Data Book, 1984, Fundamentals of Microcomputertion information on the TI family of 456 pages. Design, 1982, 584 pages.bipolar field· programmable logic Detailed specifications on dynamic University textbook. Subjects(FPL), progr.lmmable read-only RAMs, static RAMs. EPROl\ls. include microprocessors, software,memories (PROM), random-access ROMs. cache address comparators. instruction sets. microcomputer pro- .memories (RAM), microprocessors. and memory controllers. Contains gramming, high-level languages,and support circuits. product guide. interchangeability hardware features. microcomputerTTL Data Book, Vol. 5, 1984,guide. glossary. and alphanumeric memory. and I/O design. A design430 pages.index. Also. chapters on testing and example is included.reliability.Detailed specifications and applica-Sec Next Page for Additionaltion information on additional LSIInformationspecial functions that add to AS.ALS, and LS families. Includes H-bit bit-slice devices. FIFOs. EDAC,memory mapping units. and H. 9.and lO-bit registers.

Texas InstrumentsSemiconductor Technical LiteratureUnderstanding Series'" BooksThe Understanding Series books form a library written for anyone who wants to learn quickly and easily abouttoday's technology, its impact on our world, and its application in our lives. Each book is written in bright, clear,down-to-earth language and focuses on one aspect of what's new in today's electronics. Engineering concepts andtheory are explained using simple arithmetic. Technical terms are explained in layman's language. Ideal for self-paced,individualized instruction. Currently 14 different titles in the series.Understanding Series TitlesStock No.Understanding Automation Systems, Second Edition ................................................ LCB8472Understanding Automotive Electronics, Second Edition ............................................. LCB8475Understanding Calculator Math ......... , .......... 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LCB845IUnderstanding Optronics ........................................................................ LCB5472Understanding Solid-State Electronics. Fourth Edition .............................................. , LCB8453Understanding Telephone Electronics. Second Edition. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .. LCB8482Solid State Electronics Technology BooksA wide variety of textbooks spanning the field of solid state electronics - from fundamentals through advancedsemiconductor technologies. Each publication has been written by one or more authorities on the subject to bring anobjective viewpoint to the material. Texts have been carefully prepared and edited. and numerous diagrams andillustrations help achieve maximum clarity and understanding. In an industry as dynamic as electronics. it is importantfor engineers and technicians to keep abreast of the latest solid state technologies.Electronics Technology TitlesDesigning With TTL Integrated Circuits .......................................................... .Digital Integrated Circuit, Operational Ampliller. and Optoelectronic Circuit Design ................... .Electronic Displays ............................................................................. .Electronic Power Control and Digital Techniques .................................................. .Fundamentals of Microcomputer Design ........................................... ' .......... , .... .Handbook of Semiconductor and Bubble Memories ............................. : .................. .Integrated Circuits: A Basic Course .............................................................. .Integrated Digital Electronics ................... ' ............................... , ................. .Microprocessors and Microcomputers and Switching Mode Power Supplies .......... , ................. .Microprocessors/Microcomputers/System Design (H B-l)l)()OFSD B) ................................... .MOS and Special-Purpose Bi-Polar Integrated Circuits andR-F Power Transistor Circuit Design ............................................................ .MOS/LSI Design and Application .............................................. , ................. .Optoelectronics: Theory and Practice ............................................................. .Power Transistor and TTL Integrated Circuit Applications .......................................... .PCM and Digital Transmission Systems ........................................................... .R-F Power Transistor Circuit Design ............................................ , ................. .Semiconductor Measurements and Instrumentation ................................................ .16-Bit Microprocessor Systems (HB-MPB30A) .................................................... .Software Design for Microprocessors ............................................................. .Solid-State Communications ..................................................................... .Transistor Circuit Design ....................................................... , ................. .Write for current availability and prices to:Texas Instruments Information Publishing CenterP.o. Box 225012. MS-54Dallas. TX 75265Stock No.LCBI151LCB2401LCB448ILCB24 I IMPB30ALCB8034LCBlO61LCB8035LCB4021LCB5351LCB23l)ILCB1161LCB4360LCB2841LCB684ILCB23l)ILCBI851LCB776 ILCBI8l)1LCB 1Ol) ILCBIl21

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Wayne (219) 424·5174;Indianapolis (317) 248·8555IOWA: Cedar Rapids (319) 395·9550.MARYLAND: Baltimore (301) 944·8600MASSACHUSETTS: Waltham (617) 895·9100MICHIGAN: Farmington Hills (313) 553·1500.MINNESOTA: Eden Prairie (612) 828·9300.MISSOURI: Kansas City (816) 523·2500;St. Louis (314) 569·7600NEW JERSEY: Iselin (201) 750·1050.NEW MEXICO: Albuquerque (505) 345·2555.NEW YORK: East Syracuse (315) 463·9291;Endicott (607) 754·3900; Melville (516) 454·6600;Pittsford (716) 385·6770;Poughkeepsie (914) 473·2900.NORTH CAROLINA: Charlotte (704) 527·0930;Raleigh (919) 876·2725.OHIO: Beachwood (216) 464·6100;Dayton (513) 258·3877.OKLAHOMA: Tulsa (918) 250·0633.OREGON: Beaverton (503) 643·6758PENNSYLVANIA: Ft. Washington (215) 643·6450;Coraopolis (412) 771·8550.PUERTO RICO: Hayo Rey (809) 753·8700TEXAS: Austin (512) 250·7655;Houston (713) 778·6592; Richardson (214) 680·5082;San Antonio (512) 496·1779UTAH: Murray (801) 266·8972.VIRGINIA: Fairfax (703) 849·1400.WASHINGTON: Redmond (206) 881·3080.WISCONSIN: Brookfield (414) 785·7140CANADA: Nepean, Ontario (613) 726·1970;Richmond Hill, Ontario (416) 884·9181;St. Laurent, Ouebec (514) 334·3635.TI RegionalTechnology CentersCALIFORNIA: Irvine (714) 660·8140,Hotline: (714) 660·8164; Santa Clara (408) 748·2220,Hotline: (408) 980·0305.GEORGIA: Atlanta (404) 452·4682,Hotline: (404) 452·4686~~il~n~I:~~~~:i~~~06"o~8eights (312) 640·2909,MASSACHUSETTS: Waltham (617) 890·6671.Hotline: (617) 890·4271TEXAS: Richardson (214) 680·5066,Hotline: (214) 680·5096TI AUTHORIZED DISTRIBUTORS INUSAArrow ElectronicsDiplomat ElectronicsESCO ElectronicsGeneral Radio Supply CompanyGraham ElectronicsHarrison Equipment Co.International ElectronicsJACO ElectronicsKierulff ElectronicsLCOMP, IncorporatedMarshall IndustriesMilgray ElectronicsNewark ElectronicsRochester Radio SupplyTime ElectronicsR.V. Weatherford Co.Wyle LaboratoriesTI AUTHORIZED DISTRIBUTORS INCANADACESCO Electronics, Inc.Future ElectronicsITT ComponentsL.A. Varah, Ltd.ALABAMA: Arrow (205) 882·2730;Kierulff (205) 883·6070; Marshall (205) 881·9235.ARIZONA: Arrow (602) 968·4800;Kierulff (602) 243·4101; Marshall (602) 968·6181;Wyle (602) 249·2232.CALIFORNIA: Los Angeles/Orange County:Arrow (213) 701-7500, (714) 838·5422;Kierulff (213) 725·0325, (714) 731·5711;Marshall (213) 999·5001, (818) 442·7204,(714) 660·0951; R.v. Weatherford (714) 634·9600,(213) 849·3451, (714) 623·1261; Wyle (213) 322·8100,(714) 863·9953; Sacramento: Arrow (916) 925·7456;Wyle (916) 638·5282; San Diego:Arrow (619) 565·4800; Kierulff (619) 278·2112;Marshall (619) 578·9600; Wyle (619) 565·9171;San FranCisco Bay Area: Arrow (408) 745·6600;(415) 487·4600; Kierulff (408) 971·2600;Marshall (408) 732·1100; Wyle (408) 727·2500;Santa Barbara: R.V. Weatherford (805) 965·8551.COLORADO: Arrow (303) 696·1111;Kierulff (303) 790·4444; Wyle (303) 457·9953CONNECTICUT: Arrow (203) 265·7741;Diplomat (203) 797·9674; Kierulff (203) 265·1115;Marshall (203) 265·3822; Milgray (203) 795·0714.FLORIDA: Ft. Lauderdale: Arrow (305) 776·7790;Diplomat (305) 974·8700; Kierulff (305) 486·4004;Orlando: Arrow (305) 725·1480;Milgray (305) 647·5747; Tampa:Diplomat (813) 443·4514; Kierulff (813) 576·1966.GEORGIA: Arrow (404) 449·8252;Kierulff (404) 447·5252; Marshall (404) 923·5750.TEXASINSTRUMENTSCreating useful productsand services for you.ILLINOIS: Arrow (312) 397·3440;Diplomat (312) 595·1000; Kierulff (312) 640·0200;Marshall (312) 490·0155; Newark (312) 638·4411.INDIANA: Indianapolis: Arrow (317) 243·9353;Graham (317) 634·8202;Ft. Wayne: Graham (219) 423·3422.IOWA: Arrow (319) 395·7230.KANSAS: Kansas City: Marshall (913) 492·3121;Wichita: LCOMP (316) 265·9507.MARYLAND: Arrow (301) 247·5200;Diplomat (301) 995·1226; Kierulff (301) 636·5800;Milgray (301) 793·3993MASSACHUSETTS: Arrow (617) 933·8t30;Diplomat (617) 935·6611; Kierulff (617) 667·8331;Marshall (617) 272-8200; Time (617) 935·8080.MICHIGAN: Detroit: Arrow (313) 971·8220;Marshall (313) 525·5850; Newark (313) 967·0600;Grand Rapids: Arrow (616) 243·0912.MINNESOTA: Arrow (612) 830·1800;Kierulff (612) 941·7500; Marshall (612) 559·2211.M ISSOU RI: Kansas City: lCOM P (816) 221·2400;SI. Louis: Arrow (314) 567·6888;Kierulff (314) 739·0855.NEW HAMPSHIRE: Arrow (603) 668·6968.NEW JERSEY: Arrow (201) 575·5300. (609) 596·8000;Diplomat (201) 785·1830;General Radio (609) 964·8560; Kierulff (201) 575·6750;(609) 235·1444; Marshall (201) 882·0320,(609) 234·9100, (609) 235-1444; Milgray (609) 983·5010.NEW MEXICO: Arrow (505) 243·4566;International Electronics (505) 345·8t27.NEW YORK: Long Island: Arrow (516) 231·1000;Diplomat (516) 454·6400; JACO (516) 273·5500;Marshall (516) 273·2424; Milgray (516) 420·9800;Rochester: Arrow (716) 275·0300;Marshall (716) 235·7620;Rochester Radio Supply (716) 454·7800; Syracuse:Arrow (315) 652·1000; Diplomat (315) 652·5000;Marshall (607) 754·1570.NORTH CAROLINA: Arrow (919) 876·3132,(919) 725·8711; Kierulff (919) 872·8410.OHIO: Cincinnati: Graham (513) 772·1661;Cleveland: Arrow (216) 248·3990;Kierulff (216) 587·6558; Marshall (216) 248·1788Columbus: Graham (614) 895·1590;Dayton: Arrow (513) 435·5563;ESCO (513) 226·1133; Kierulff (513) 439·0045;Marshall (513) 236·8088.OKLAHOMA: Arrow (918) 665·7700;Kierulff (918) 252·7537.OREGON: Arrow (503) 684·7690;Wyle (503) 640·6000.PENNSYLVANIA: Arrow (412) 856·7000,(215) 928·1800; General Radio (215) 922·7037.TEXAS: Austin: Arrow (512) 835·4180;Kierulff (512) 835·2090; Marshall (512) 458·5654;Wyle (512) 834·9957; Dallas: Arrow (214) 386·7500;International Electronics (214) 233·9323;Kierulff (214) 343·2400; Marshall (214) 233-5200;Wyle (214) 235·9953;EI Paso: International Electronics (915) 598·3406;Houston: Arrow (713) 530·4700;Marshall (713) 789-6600;Harrison Equipment (713) 879·2600; .Kierulff (713) 530·7030.UTAH: Diplomat (801) 486·4134;Kierulff (801) 973-6913; Wyle (801) 974·9953VIRGINIA: Arrow (804) 282·0413.WASHINGTON: Arrow (206) 643·4800;Kierulff (206) 575·4420; Wyle (206) 453·8300.WISCONSIN: Arrow (414) 764·6600;Kierulff (414) 784·8160.CANADA: Calgary: Future (403) 259·6408; Varah(403) 230·1235; Edmonton: Future (403) 486·0974;Hamilton: Varah (416) 561·9311; Montreal:CESCO (514) 735·5511; Future (514) 694·7710;ITT Components (514) 735·1177; Oltawa:CESCO (613) 226·6903; Future (613) 820·8313; ITTComponents (613) 226·7406; Varah (613) 726·8884;Ouebec City: CESCO (418) 687·423t; Toronto:CESCO (4t6) 661·0220; Future (4t6) 663·5563;ITT Components (4t6) 630·7971; Vancouver:Future (604) 438·5545; Varah (604) 873·3211;ITT Components (604) 270·7805; Winnipeg:Varah (204) 633·6190; Edmonton:Future (403) 486·0974. 81

TI WorldwideSales Offices~~~~~m:: r~3~~~~(~~~ ~~~75fo.ive, Suite 514,ARIZONA: Photnl.: 8102 N. 23rd Ave., Suite B,Phoenix, AZ 85021, (602) 995·1007.CALIFORNIA: Imn.: 17891 Cartwright Rd., Irvine,CA 92714, (714) 660·1200; Sacramento: 1900 PointWest Way, Suite 171, Sacramento, CA 95815,~~i~~ 9l~'~~~' b~:g"o~be.l~2~~~~ ~~) 2~~~~~e.,~~3J:, ~!~8i: i:~~Vo~~~~e~r;9~~5t~a~fl~~nCtr.,Bldg. A, Suite 1, Torrance, CA 90502, (213) 217·7010;Woodland Hills: 21220 Erwin St., Woodland Hills,CA 91367, (213) 704·7759.COLORADO: Aurora: 1400 S. Potomac Ave.,Suite 101, Aurora, CO 80012, (303) 695·2800.CONNEC'tICUT: Wallingford: 9 Barnes Industrial:;r'OO~~2,~~~~i~J~~~~lal Park, Wallingford,FLORIDA: Ft. L8Uderdale: 2765 N.W. 62nd St.,Ft. Lauderdale, FL 33309, (305) 973·8502; Mallllnd:2601 Maitland Center Parkway, Maitland, FL 32751,~~~~ ~~~~~~::.mFtI~Jg, ~i~ee;~2~lvd.,GEORGIA: Allintl: 3300 Northeast Expy., Building 9,Atlanta, GA 30341, (404) 452-4600.~~it~9~~~: ~!?~t':.~LH=~:(gn ~0~4~~quln,INDIANA: FI. WI!.nl: 2020 Inwood Dr., Ft. Wayne,L~n~~r1~: ~JI~~ j.:5d,71~dli~~~~I~:,III'N ~~~~,~.(317) 248·8555.IOWA: Cedar Rlplds: 373 Collins Rd. NE, Suite 200,Cedar Rapids, IA 52402, (319) 395·9550.MARYLAND: Baltimore: I Rutherford PI.,7133 Rutherford Rd., Baltimore, MD 21207(301) 944·8600. .'MASSACHUSETTS: Waltham: 504 Totten Pond Rd.,Waltham, MA 02154, (617) 895-9100.~~~~~~~:~ ~~I~IMlt:80~~I,li~lf)7~l3~sJJ. Mile Rd.,MINNESOTA: Eden Prairie: 11000 W. 78th St.,Eden Prairie, MN 55344 (612) 828·9300.MISSOURI: Kan ... City: 8080 Ward Pkwy., KansasCity, MO 64114, (616) 523·2500; 51. Louis:11861 Westline Industrial Drive, 51. Louis,MO 63141, (314) 569-7600.NEW JERSEY: Iselin: 485E U.S. Route I South,Iselin, NJ 08830 (201) 750-1050NEW MEXICO: Albuquerque: 2620·0 Broadbent PkwyNE, Albuquerque, NM 87107, (505) 345·2555.NEW YORK: East Syracuse: 6365 Old Collamer Dr.,East Syracuse, NY 13057, (315) 463·9291; Endicott:112 Nanticoke Ave., P.O. Box 618, Endicott,NY 13760, (807) 754·3900; Melville: 1 Huntington~~a~f~~ti51'6)1~1~80tp?ri:'~~~~' ~~~~~~'St.,Pittsford, NY 14534, (716) 385-6770; Poughkeepsie:r9e,s4)S~~~~~: I'oughkeepsie, NY 12601,NORTH CAROLINA: Chartotte: 8 Woodlawn Green,Woodlawn Rd., Charlotte, NC 28210, (704) 52H)930;~em~g,~~iR~;~72d5~ Blvd., Suite 100, Raleigh,OHIO: Beachwood: 23408 Commerce Park Rd.,Beachwood, OH 44122, (216) 464-6100; Dayton:~r~S4~~.~~~~:' 4124 Linden Ave., Dayton, OH 45432,OKLAHOMA: Tulsa: 7615 East 63rd Place,3 Memorial Place, Tulsa, OK 74133, (918) 250·0633.OREGON: Beaverton: 6700 SW 105th St., Suite 110,Beaverton, OR 97005, (503) 643-6756.~~~~~~~;~~~~~I'I~~~~I(~~~)n64~~4~~;W York Dr.,Coraopolis: 420 Rouser Rd., 3 Airport Office Park,Coraopolis, PA 15106, (412) 771·8550.PUERTO RICO: Heto Rey: Mercantil Plaza Bldg.,Suite 505, Hato Rey, PR 00919, (809) 753·6700.TEXAS: Austin: 12501 Research Blvd.,P.O. Box 2909, Austin, TX 78723, (512) 250·7655;Richardson: 1001 E. Campbell Rd.,Richardson, TX 75080,~Jli~ 62BJl7~a;~s~g~~~~n~ngg, ~m)h7;ilt9~y·,San Anlonlo: 1000 Central Parkway South,San AntoniO, TX 78232, (512) 496·1779.UTAH: Murray: 5201 South Green SE, Suite 200,Murray, UT 84107, (801) 266·8972.VIRGINIA: Falrt .. : 3001 Prosperity, Fairfax; VA22031, (703) 849·1400.WASHINGTON: Redmond: 2723 152nd Ave .. N.E.Bldg. 6, Redmond, WA 98052, (206) 881·3080.~~~~~~~I~;!~~~~I,eWi ~~OO~: ~~~)~8~.~~:O.CANADA: Nepean: 301 Moodie Drive, MallornCenter, NeGran, Ontario, Canada, K2HIlC4,. WI~3~~~~"J H8i ~!~'~~~~~~~:i;,aga~~~~e 51. E.,b416) 884·9181; St. Laurent: Ville St. Laurenl Quebec,c~6nOaJ~a~~S~~t\~,~ir:i4~3,;"urent, Quebec,ARGENTINA: Texas Instruments ArgentinaS.A.I.C.F.: Esmeralda 130, 15th Floor, 1035 BuenosAires, Argentina, 1 + 394·2963.AUSTRALIA II NEW ZEALAND): Texas InslrumentsAustralia Ltd.: 6·10 Talavera Rd., North Rydeb~~nU~'~~2; ~~htPI:~~~~'lSt~tk~:~a 2~6;d,Melbourne, Victoria, Australia 3004, 03 + 267·4677;6~':~Mt2~RhWay, Elitabeth, South Australia 5112,AUSTRIA: Texas Instruments Ges.m.b.H.:~2~~~~i:ilo~be B/16, A·2345 BrunnlGebitge,~;~;~~M~e~~;:,s ~~~~~,:;:~:s,~~ R~:IS~U~ ~~~~e,1130 Brussels, Belgium, 021720.80.00.BRAZIL: Texas Instruments Electronicos do BrasilLtda.: Rua Paes.Leme, 524·7 Andar Pinhelros, 05424Sao Paulo, arazil, 0615-6166.DENMARK: Texas Instruments AlS, Mairelundvej46E, DK·2730 Herlev, Denmark, 2 • 91 74 00.FINLAND: Texas Instruments Finland OY:6~8:1.~,u33skatu 1900051 I Helsinki 51, Finland, (90)FRANCE: Texas Instruments France: Headquartersand Prod. Plant, BP OS, 06270 Villeneuve·Loubet,~r~~J~~inr:r:i~8~~flc~el~~.tfll~~gu~I:;,ue~~t~~~r'~~;~~~~i~~~sl;>~6~:sk~~~~9~1c~~~'IIY,(7) 833-04·40; Sirasbourg Sales Office, Le Sebastopol3, Quai Kleber, 67055 Strasbourg Cedex,~~6/~2~:~~S~(~~e;i.~U~; ~~~I~~s':u~:I~a~W~~e,k~ l~r\poo~ro:;e,~~f)~I~"d8! I ~~g~~~s~~re d~~I:;m:r~::~~ll~7~~~~iS-146 Rue Paradis, 13006 Marseille,~TEXASINSTRUMENTSCreating useful productsand services for youGERMANY (Fed. Republic of Germany): TexasInstruments DeutSChland GmbH: Haggertystrasse 1,~:~~:~~~'~:rl~n' ;5~ogjoK+u:2:~~e5~~~~agen431Klbbelstrasse, .19, 0..,300 Essen, 0201·24250;Frankfurter Allee 6-8, 0-6236 Eschborm "06198+43074; Hamburgerstrasse II, 0·2000Hamburg 76,040+220·1154, Klrchhorsterstrasse 2,0-3000 Hannover 51, 0511 +648021; Arabeilistrasse21,0·8000 Munich 81, 089+911006; Maybachstrabe11, 0·7302 Ostfildern 2·Nellngen, 0711 + 547001;~~~\~~~~~3'J'9, ~~~t7:s'~~u,r3. ~5~~ K~~ie~~';0261 + 35044.HONG KONG 1+ PEOPLES REPUBLIC OF CHINA):Texas Instruments Asia Ltd., 8th Floor, WorldShipping Ctr., Harbour City, 7 Canton Rd., Kowloon,Hong Kong, 3 + 722·1223.IRELAND: Texas Instruments (Ireland) limited:gfe8'rJW', ~d., Stillorgan, County Dublin, Eire,ITALY: Texas Instruments Semlconduttorl Italla Spa:Vlale Delle Sclenze, 1,02015 Clttaducale (R1etl),Italy, 0746 694.1; Via Salarla KM 24 (Palazzo Cosma),Monterotondo Scalo (Rome), Italy, 6 + 9003241; Vialeg~r~t3~5~~'~~o~~9Jvg~~~,n~8~0,nti~ t~;II~g~ltaIY,gJl m~~~: Via J. Baroul 6, 45100 Bologna, Italy,JAPAN: Texas Instruments Asia Ltd.: 4F AoyamaFuji Bldg., 6·12, Kita Aoyama 3·Chome, Mlnato·ku,Tokyo, Japan 107,03-498·2111; Osaka BranCh, SF,Nissho Iwal Bldg., 30 Imabashl 3· Chome,Hlgashl·ku, Osaka, Japan 541, 06·204·1881; NagoyaBranch, 7F Daln; Toyota West Bldg., 10·27, Melekl4·Chome, Nakamura·ku Nagoya, Japan450, 052·583·8691.KOREA: Texas Instruments Supply Co.: 3rd Floor,~~g'S~0~\?~o~~~~a:4~f~80~angnam.ku,MEXICO: Texas Instruments de Mexico S-A.:Poniente 116, No. 489, Colonia Vallejo, Mexico, D.F.02300, 567·9200.MIDDLE EAST: Texas Inslruments: No. 13, 1st FloorMannal Bldg., Diplomatic Area, Manama, P.O. Box26335, Bahrain, Arabian Gulf,973 + 274681.NETHERLANDS: Texas Instruments Holland B.V.,P.O. Box 12995, (Bullewljk) 1100 CB Amsterdam,Zuld·Oost, Holland 20 + 560291 1.~~~~:1~i,e~~~d~~I~Uo~~~~ (~)of5t6~!S: PB106,PHILIPPINES: Texas Instruments Asia Ltd.: 14thFloor, Ba· Lepanl0 Bldg., 8747 Paseo de Roxas,Makati, Metro Manila, Philippines, 2+8188987.PORTUGAL: Texas Instruments EQulpamento5\~1~~~~5b (~~~?:15aL~~ia~~~7~nf;ar~~~~~~~al,2·948·1003.SINGAPORE 1+ INDIA, INDONESIA, MALAYSIA,THAILAND): Texas Instruments Asia Ltd.: 12 LorongBakar Batu, Unil 01-02, Kolam Ayer Industrial Estate,Republic of Singapore, 747·2255.SPAIN: Texas Instruments Espana, S-A.: CIJoseLazaro Galdiano No.6, Madrid 16, 11458.14.56.SWEDEN: Texas Instruments lillernatlonal Trade~~;g~~~\~~ ~~:J~~~f~~~e2jS~~ 39103, 10054SWITZERLAND: Texas Instruments, Inc., Reidstrasse6, CH·8953 Dietikon (Zuerich) Switzerland,1-7402220.tAIWAN: Texas Instruments SUPPI~ Co.: Room 903,¥~Tw~~~ ~~~bl~dOf7~~~~~o~i~n~21?~2,:aiPel,UNITED KINGDOM: Texas Instruments Limiled:Manton Lane, Bedford, MK41 7PA, England, 023467466; 51. James House, Wellington Road North,Stockport, SK4 2RT, England, 61 +442·7162. BI

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